16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR
Differential ADC in MSOP/QFN
Preliminary Technical Data
AD7693
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
APPLICATION DIAGRAM
16-bit resolution with no missing codes
AD7693
REF
GND
VDD
IN+
IN
VIO
SDI
SCK
SDO
CNV
+1.8V TO VDD
3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)
+2.5V TO +5V
10V, 5V, ...
+5V
ADA4941-1
-
001
Throughput: 500 kSPS
INL: +/-0.25 LSB typical, 0.65 LSB max (10 ppm of FSR)
Dynamic range: 96.5 dB typical @ 500 kSPS
SINAD: 96 dB typical @ 1 kHz, REF = 5V
THD: -120 dB typical @ 1 kHz. REF = 5V
True differential analog input range: VREF
0 V to V
REF
with V
REF
up to V
DD
on both inputs
No pipeline delay
Figure 2.
Single-supply 5 V operation with
Table 1. MSOP, QFN
1
(LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI/QSPITM/MICROWIRETM/DSP-compatible
400 kSPS
to
500 kSPS
Daisy-chain multiple ADCs and busy indicator
100
kSPS
250
kSPS
ADC
Driver
Power dissipation
Type
4 mW @ 5 V/100 kSPS
18-Bit
AD7691
AD7690
ADA4941-1
40 W @ 5 V/1 kSPS
ADA4841-x
Standby current: 1 nA
AD7684
AD7687
AD7688
10-lead package: MSOP (MSOP-8 size) and
3 mm 3 mm QFN
1
(LFCSP) (SOT-23 size)
Pin-for-pin compatible with the
AD7687, AD7688
and
18-bit
AD7690 and AD7691
APPLICATIONS
Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments
Figure 1. Integral Nonlinearity vs. Code
16-Bit True
Differential
AD7693
ADA4941-1
ADA4841-x
16-Bit Pseudo
AD7683
AD7685
AD7686
ADA4841-x
AD7680
AD7694
Differential/
Unipolar
14-Bit
AD7940
AD7942
AD7946
ADA4841-x
1
QFN package in development. Contact sales for samples and availability.
GENERAL DESCRIPTION
The AD7693 is a 16-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 16-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. On the CNV rising edge, it
samples the voltage difference between the IN+ and IN- pins.
The voltages on these pins swing in opposite phase between 0 V
and REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage, VDD.
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN
1
(LFCSP) with operation specified from -40C to +85C.
1
QFN package in development. Contact sales for samples and availability.
AD7693
Preliminary Technical Data
Rev. PrB | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Application Diagram........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Typical Connection Diagram ................................................... 13
Analog Inputs.............................................................................. 14
Driver Amplifier Choice ........................................................... 14
Single-to-Differential Driver .................................................... 15
Voltage Reference Input ............................................................ 15
Power Supply............................................................................... 15
Supplying the ADC from the Reference.................................. 16
Digital Interface.......................................................................... 16
CS Mode 3-Wire, No BUSY Indicator..................................... 17
CS Mode 3-Wire with BUSY Indicator ................................... 18
CS Mode 4-Wire, No BUSY Indicator..................................... 19
CS Mode 4-Wire with BUSY Indicator ................................... 20
Chain Mode, NO BUSY Indicator ........................................... 21
Chain Mode with BUSY Indicator ........................................... 22
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the AD7693's Performance.................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
Preliminary Technical Data
AD7693
Rev. PrB | Page 3 of 24
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION 18
Bits
ANALOG INPUT
Voltage Range
IN+ - (IN-)
-V
REF
+V
REF
V
Absolute Input Voltage
IN+, IN-
-0.1
V
REF
+ 0.1
V
Common-Mode Input Range
IN+, IN-
0
V
REF
/2 V
REF
/2 + 0.1
V
Analog Input CMRR
f
IN
= 250 kHz
65
dB
Leakage Current at 25C
Acquisition phase
1
nA
Input Impedance
1
THROUGHPUT
Conversion Rate
0
500
kSPS
Transient Response
Full-scale step
400
ns
ACCURACY
No Missing Codes
16
Bits
Integral Linearity Error
-0.65
0.25
+0.65
LSB
Differential Linearity Error
-0.5
0.2
+0.5
LSB
2
Transition Noise
REF = VDD = 5 V
0.16
LSB
Gain Error
3
-30
1.5
+30
LSB
Gain Error Temperature Drift
0.5
ppm/C
Zero Error
3
-10
+10
LSB
Zero Temperature Drift
1
ppm/C
Power Supply Sensitivity
VDD = 5 V
5%
1
ppm
AC ACCURACY
Dynamic Range
V
REF
= 5 V
96
96.5
dB
4
Signal-to-Noise f
IN
= 1 kHz, V
REF
= 5 V
95.5
96
dB
f
IN
= 1 kHz, V
REF
= 2.5 V
93
dB
Spurious-Free Dynamic Range
f
IN
= 1 kHz, V
REF
= 5 V
-120
dB
Total Harmonic Distortion
f
IN
= 1 kHz, V
REF
= 5 V
-120
dB
Signal-to-(Noise + Distortion)
f
IN
= 1 kHz, V
REF
= 5 V
95.5
96
dB
Intermodulation Distortion
5
TBD
dB
1
See the Analog Inputs section.
2
LSB means least significant bit. With the 5 V input range, one LSB is 152.6 V.
3
See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5
f
IN1
= 21.4 kHz and f
IN2
= 18.9 kHz, with each tone at -7 dB below full scale.
AD7693
Preliminary Technical Data
Rev. PrB | Page 4 of 24
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Conditions/Comments
Min
Typ
Max
Unit
REFERENCE
Voltage Range
0.5
VDD + 0.3
V
Load Current
500 kSPS, REF = 5 V
100
A
SAMPLING DYNAMICS
-3 dB Input Bandwidth
9
MHz
Aperture Delay
VDD = 5V
2.5
ns
DIGITAL INPUTS
Logic Levels
V
IL
-0.3
+0.3
VIO
V
V
IH
0.7 VIO
VIO + 0.3
V
I
IL
-1
+1
A
I
IH
-1
+1
A
DIGITAL OUTPUTS
Data Format
Serial 16 bits twos
complement
Pipeline Delay
1
V
OL
I
SINK
= +500 A
0.4
V
V
OH
I
SOURCE
= -500 A
VIO - 0.3
V
POWER SUPPLIES
VDD
Specified performance
4. 5
5.5
V
VIO
Specified performance
2.3
VDD + 0.3
V
VIO Range
1.8
VDD + 0.3
V
Standby Current
2 , 3
VDD and VIO = 5 V, 25C
1
50
nA
Power Dissipation
100 SPS throughput
5
W
100 kSPS throughput
5
mW
500 kSPS throughput
15
mW
Energy per Conversion
50
nJ/sample
TEMPERATURE RANGE
4
Specified Performance
T
MIN
to T
MAX
-40
+85
C
1
Conversion results available immediately after completed conversion.
2
With all digital inputs forced to VIO or GND as required.
3
During acquisition phase.
4
Contact an Analog Devices sales representative for extended temperature range.
Preliminary Technical Data
AD7693
Rev. PrB | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
1
Parameter
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available
t
CONV
0.5
1.6
s
Acquisition Time
t
ACQ
400
ns
Time Between Conversions
t
CYC
2.0
s
CNV Pulse Width (CS Mode)
t
CNVH
10
ns
SCK Period (CS Mode)
t
SCK
15
ns
SCK Period (Chain Mode)
t
SCK
VIO Above 4.5 V
17
ns
VIO Above 3 V
18
ns
VIO Above 2.7 V
19
ns
VIO Above 2.3 V
20
ns
SCK Low Time
t
SCKL
7
ns
SCK High Time
t
SCKH
7 ns
SCK Falling Edge to Data Remains Valid
t
HSDO
4 ns
SCK Falling Edge to Data Valid Delay
t
DSDO
VIO Above 4.5 V
14
ns
VIO Above 3 V
15
ns
VIO Above 2.7 V
16
ns
VIO Above 2.3 V
17
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
t
EN
VIO Above 4.5 V
15
ns
VIO Above 2.7 V
18
ns
VIO Above 2.3 V
22
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
25
ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
t
SSDICNV
15
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
t
HSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
t
SSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
t
HSCKCNV
10
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
t
SSDISCK
3
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
t
HSDISCK
4
ns
SDI High to SDO High (Chain Mode with BUSY Indicator)
t
DSDOSDI
VIO Above 4.5 V
15
ns
VIO Above 2.3 V
26
ns
1
See Figure 3 and Figure 4 for load conditions.
AD7693
Preliminary Technical Data
Rev. PrB | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter Rating
Analog Inputs
IN+, IN-
GND - 0.3 V to VDD + 0.3 V
or 130 mA
1
1
REF
GND - 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND
-0.3 V to +7 V
VDD to VIO
7 V
Digital Inputs to GND
-0.3 V to VIO + 0.3 V
Digital Outputs to GND
-0.3 V to VIO + 0.3 V
Storage Temperature Range
-65C to +150C
Junction Temperature
150C
JA
Thermal Impedance (MSOP-10)
200C/W
JC
Thermal Impedance (MSOP-10)
44C/W
Lead Temperature Range
JEDEC J-STD-20
1
See the Analog Inputs section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500A
I
OL
500A
I
OH
1.4V
TO SDO
C
L
50pF
-
002
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO ABOVE 2.5V, VIO 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
-003
Figure 4. Voltage Levels for Timing
Preliminary Technical Data
AD7693
Rev. PrB | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
REF
2
VDD
3
IN+
4
IN
5
GND
10 VIO
NOTES
1. QFN PACKAGE IN DEVELOPMENT. CONTACT
SALES FOR SAMPLES AND AVAILABILITY.
9 SDI
8 SCK
7 SDO
6 CNV
TOP VIEW
(Not to Scale)
AD7693
-005
REF
1
VDD
2
IN+
3
IN
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7693
TOP VIEW
(Not to Scale)
-
004
Figure 5. 10-Lead MSOP Pin Configuration
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1
1 REF
AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This
pin should be decoupled closely to the pin with a 10 F capacitor.
2 VDD
P
Power
Supply.
3
IN+
AI
Differential Positive Analog Input.
4
IN-
AI
Differential Negative Analog Input.
5
GND
P
Power Supply Ground.
6 CNV
DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part; chain or CS mode. In chain mode, the data should be
read when CNV is high. In CS mode, it enables the SDO pin when low.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK
DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this
clock.
9 SDI
DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC
as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.
The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV
can enable the serial output signals when low, and if SDI or CNV is low when the conversion is
complete, the BUSY indicator feature is enabled.
10 VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
AD7693
Preliminary Technical Data
Rev. PrB | Page 8 of 24
TERMINOLOGY
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital con-
verter with N bits of resolution, the LSB expressed in volts is
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINAD
dB
- 1.76)/6.02
N
INp-p
V
V
LSB
2
)
(
=
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs LSB before the first
code transition. Positive full scale is defined as a level 1 LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
Figure 25).
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity Error (DNL)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Signal-to-(Noise + Distortion) Ratio (SINAD)
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level LSB above nominal negative full scale (-4.999847 V
for the 5 V range). The last transition (from 011 ... 10 to
011 ... 11) should occur for an analog voltage 1 LSB below the
nominal full scale (+4.999771 V for the 5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Preliminary Technical Data
AD7693
Rev. PrB | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Integral Nonlinearity vs. Code
Figure 10. Differential Nonlinearity vs. Code
Figure 11. Histogram of a DC Input at the Code Transition
Figure 8. Histogram of a DC Input at the Code Center
Figure 9. FFT Plot
Figure 12. SNR vs. Input Level
AD7693
Preliminary Technical Data
Rev. PrB | Page 10 of 24
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 16. THD, SFDR vs. Reference Voltage
Figure 14. SNR vs. Temperature
Figure 17. THD vs. Temperature
Figure 15. SINAD vs. Frequency
Figure 18. THD vs. Frequency
Preliminary Technical Data
AD7693
Rev. PrB | Page 11 of 24
1000
0
SUPPLY (V)
V
DD O
P
E
RAT
I
NG
C
URRE
NT
(
A)
05
79
2-
04
1
4.50
5.50
750
500
250
f
S
= 100kSPS
VDD
VIO
4.75
5.00
5.25
Figure 22. Offset and Gain Error vs. Temperature
Figure 19. Operating Currents vs. Supply
SDO CAPACITIVE LOAD (pF)
120
0
20
40
60
80
100
t
DSD
O
DE
L
AY
(
n
s
)
25
20
15
10
5
0
VDD = 5V, 85C
VDD = 5V, 25C
0
57
92
-
03
4
TEMPERATURE (
C)
P
O
W
E
R-
DO
W
N CU
RRE
N
T
(
n
A)
1000
750
500
250
0
55
35
15
5
25
45
65
85
105
125
VDD + VIO
0
57
92
-
03
3
Figure 20. Power-Down Currents vs. Temperature
Figure 23. t
DSDO
Delay vs. Capacitance Load and Supply
1000
6
SUPPLY (V)
O
P
E
RAT
I
NG
CURRE
NT
(
A)
05
79
2-
04
2
55
125
750
500
250
f
S
= 100kSPS
VDD
VIO
35
15
5
25
45
65
85
105
Figure 21. Operating Currents vs. Temperature
AD7693
Preliminary Technical Data
Rev. PrB | Page 12 of 24
THEORY OF OPERATION
SW+
MSB
16,384C
IN+
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN
4C
2C
C
C
32,768C
SW
MSB
16,384C
LSB
4C
2C
C
C
32,768C
-
024
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7693 is a fast, low power, single-supply, precise, 16-bit
ADC using a successive approximation architecture.
The AD7693 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 1 kSPS, for example, it consumes 40 W
typically, ideal for battery-powered applications.
The AD7693 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.
The AD7693 is specified from 4.5 V to 5.5 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines
space savings and allows flexible configurations.
It is pin-for-pin compatible with the 16-bit
AD7687
and
AD7688
and with the 18-bit
AD7690
and
AD7691
.
CONVERTER OPERATION
The AD7693 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator's input are connected to GND via SW+ and SW-.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN- inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW- are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN- captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (V
REF
/2, V
REF
/4 ... V
REF
/32,768).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.
Because the AD7693 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Preliminary Technical Data
AD7693
Rev. PrB | Page 13 of 24
TYPICAL CONNECTION DIAGRAM
Transfer Functions
Figure 26 shows an example of the recommended connection
diagram for the AD7693 when multiple supplies are available.
The ideal transfer characteristic for the AD7693 is shown in
Figure 25 and Table 7.
100...000
100...001
100...010
011...101
011...110
011...111
ADC CODE (TWOS COMPLEMENT)
ANALOG INPUT
+FSR 1.5LSB
+FSR 1LSB
FSR + 1LSB
FSR
FSR + 0.5LSB
-025
Figure 25. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Analog Input
V
REF
= 5 V
Digital Output
Code (Hex)
Description
FSR - 1 LSB
+4.999847 V
0x7FFF
1
Midscale + 1 LSB
+152.6 V
0x0001
Midscale
0 V
0x0000
Midscale - 1 LSB
-152.6 V
0xFFFF
-FSR + 1 LSB
-4.999847 V
0x8001
-FSR
-5 V
0x8000
2
1
This is also the code for an overranged analog input (V
IN+
- V
IN-
above V
REF
- V
GND
).
2
This is also the code for an underranged analog input (V
IN+
- V
IN-
below V
GND
).
AD7693
REF
GND
VDD
IN
IN+
VIO
SDI
SCK
SDO
CNV
3- OR 4-WIRE INTERFACE
5
100nF
100nF
5V
10F
2
V+
V+
V
1.8V TO VDD
REF
1
0 TO V
REF
2.7nF
4
V+
V
V
REF
TO 0
2.7nF
ADA4841-2
3
ADA4841-2
3
4
1
SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2
C
REF
IS USUALLY A 10F CERAMIC CAPACITOR (X5R).
3
SEE TABLE 8 FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5
SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
-
026
15
15
Figure 26. Typical Application Diagram with Multiple Supplies
AD7693
Preliminary Technical Data
Rev. PrB | Page 14 of 24
When the source impedance of the driving circuit is low, the
AD7693 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
ANALOG INPUTS
Figure 27 shows an equivalent circuit of the input structure of
the AD7693.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN-. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer's
(U1) supplies are different from VDD. In such a case, for
example, an input buffer with a short-circuit, the current
limitation can be used to protect the part.
DRIVER AMPLIFIER CHOICE
Although the AD7693 is easy to drive, the driver amplifier must
meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7693. The noise coming from
the driver is filtered by the AD7693 analog input circuit's
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of
the AD7693 is 56 V rms, the SNR degradation due to the
amplifier is
C
IN
R
IN
D1
D2
C
PIN
IN+
OR IN
GND
VDD
-027
+
+
=
-
-
2
dB
3
2
dB
3
2
)
(
2
)
(
2
56
56
log
20
N
N
LOSS
Ne
f
Ne
f
SNR
Figure 27. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN-. By using these
differential inputs, signals common to both inputs are rejected.
where:
f
-3 dB
is the input bandwidth in megahertz of the AD7693
(9 MHz) or the cutoff frequency of the input filter, if one is
used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
e
N
is the equivalent input noise voltage of the op amp, in
nV/Hz.
90
40
1
10000
FREQUENCY (kHz)
CM
RR (dB)
-028
10
100
1000
85
80
75
70
65
60
55
50
45
V
REF
= VDD = 5V
For ac applications, the driver should have a THD
performance commensurate with the AD7693.
For multichannel multiplexed applications, the driver
amplifier and the AD7693 analog input circuit must settle
for a full-scale step onto the capacitor array at an 16-bit
level (0.0015%, 15 ppm). In the amplifier's data sheet,
settling at 0.1% to 0.01% is more commonly specified. This
could differ significantly from the settling time at an 16-bit
level and should be verified prior to driver selection.
Figure 28. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN-) can be modeled as a parallel combination
of the capacitor, C
PIN
, and the network formed by the series
connection of R
IN
and C
IN
. C
PIN
is primarily the pin capacitance.
R
IN
is typically 600 and is a lumped component made up of
serial resistors and the on resistance of the switches. C
IN
is
typically 30 pF and is mainly the ADC sampling capacitor.
Table 8. Recommended Driver Amplifiers
Amplifier Typical
Application
ADA4941-1
Very low noise, low power single to differential
ADA4841-x
Very low noise, small, and low power
AD8655
5 V single supply, low noise
AD8021
Very low noise and high frequency
During the conversion phase, where the switches are opened,
the input impedance is limited to C
PIN
. R
IN
and C
IN
make a 1-
pole, low-pass filter that reduces undesirable aliasing effects and
limits the noise.
AD8022
Low noise and high frequency
OP184
Low power, low noise, and low frequency
AD8605
,
AD8615
5 V single supply, low power
Preliminary Technical Data
AD7693
Rev. PrB | Page 15 of 24
If desired, smaller reference decoupling capacitor values down
to 2.2 F can be used with a minimal impact on performance,
especially DNL.
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the
ADA4941-1
single-ended-to-differential
driver allows for a differential input into the part. The
schematic is shown in
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
Figure 29.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (V
REF
). R1, R2, and C
F
will be chosen depending
on the desired input resistance, signal bandwidth, antialiasing
and noise contribution. For example, for the 10 V range with a
4 k impedance, R2 = 1 k and R1 = 4 k.
POWER SUPPLY
The AD7693 uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and V
DD
. To
reduce the supplies needed, the VIO and VDD pins can be tied
together. The AD7693 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in
R3 and R4 set the common mode on the IN- input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to V
REF
/2; however, if single
supply is desired, it can be set slightly above V
REF
/2 to provide
some headroom for the
Figure 30.
ADA4941-1
output stage. For example,
for the 10 V range with a single supply, R3 = 8.45 k, R4 =
11.8 k, R5 = 10.5 k, and R6 = 9.76 k.
90
40
1
10000
FREQUENCY (kHz)
CMRR (dB)
-030
10
100
1000
85
80
75
70
65
60
55
50
45
V
REF
= VDD = 5V
AD7693
REF
GND
VDD
IN+
2.7nF
100nF
2.7nF
IN
+5V REF
10V, 5V, ...
+5.2V
+5.2V
15
10F
R2
C
F
ADA4941
R1
R3
100nF
R5
R4
R6
-
029
15
Figure 30. PSRR vs. Frequency
The AD7693 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (even a few hertz) and low battery-powered applications.
Figure 29. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7693 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the
1000
10
0.1
0.001
10
1M
SAMPLING RATE (SPS)
OPERATING CURRENT (
A)
-031
100
1k
100k
10k
VDD = 5V
VIO
10000
100
1
0.01
Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the
AD8031
or the
AD8605
, a
10 F (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 F (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using low temperature drift
ADR43x
and
ADR44x
references.
Figure 31. Operating Currents vs. Sample Rate
AD7693
Preliminary Technical Data
Rev. PrB | Page 16 of 24
SUPPLYING THE ADC FROM THE REFERENCE
ADSP-219x. In this mode, the AD7693 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections useful, for instance,
in isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the
conversions, to be independent of the readback timing (SDI).
This is useful in low jitter sampling or simultaneous sampling
applications.
For simplified applications, the AD7693, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 32. The reference line can be driven by
The system power supply directly.
A reference voltage with enough current output capability,
such as the
ADR43x
.
When in chain mode, the AD7693 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
A reference buffer, such as the
AD8031
, which can also
filter the system power supply, as shown in Figure 32.
AD8031
AD7693
VIO
REF
VDD
10F
1F
10
10k
5V
5V
5V
1F
1
-032
1
OPTIONAL REFERENCE BUFFER AND FILTER.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
In either mode, the AD7693 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
Figure 32. Example of Application Circuit
DIGITAL INTERFACE
The busy indicator feature is enabled
Though the AD7693 has a reduced number of pins, it offers
flexibility in its serial interface modes.
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 36 and Figure 40).
CS
When in
mode, the AD7693 is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin ADSP-BF53x or
In the chain mode if SCK is high during the CNV rising
edge (see Figure 44).
Preliminary Technical Data
AD7693
Rev. PrB | Page 17 of 24
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33, and the corresponding timing is given in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7693 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
th
SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7693
-033
CS
Figure 33. 3-Wire
Mode Without Busy Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D13
D1
D0
t
DIS
SCK
1
2
3
14
15
16
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
034
CS
Figure 34. 3-Wire
Mode Without Busy Indicator Serial Interface Timing (SDI High)
AD7693
Preliminary Technical Data
Rev. PrB | Page 18 of 24
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7693 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17
th
SCK falling edge,
or when CNV goes high, whichever is earlier, SDO returns to
high impedance.
If multiple AD7693s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
CNV
SCK
SDO
SDI
VIO
AD7693
-035
CS
Figure 35. 3-Wire
Mode with Busy Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D1
D0
t
DIS
SCK
1
2
3
15
16
17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
-
036
CS
Figure 36. 3-Wire
Mode with Busy Indicator Serial Interface Timing (SDI High)
Preliminary Technical Data
AD7693
Rev. PrB | Page 19 of 24
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7693s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7693s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7693 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
th
SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7693
can be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
AD7693
AD7693
-037
CS
Figure 37. 4-Wire
Mode Without Busy Indicator Connection Diagram
SDO
D15
D14
D13
D1
D0
t
DIS
SCK
1
2
3
30
31
32
t
HSDO
t
DSDO
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
14
15
t
SCK
t
SCKL
t
SCKH
D0
D16
D15
17
18
16
SDI(CS2)
-038
CS
Figure 38. 4-Wire
Mode Without Busy Indicator Serial Interface Timing
AD7693
Preliminary Technical Data
Rev. PrB | Page 20 of 24
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7693
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17
th
SCK falling edge,
or SDI going high, whichever is earlier, SDO returns to high
impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
CNV
SCK
SDO
SDI
AD7693
-
039
CS
Figure 39. 4-Wire
Mode with Busy Indicator Connection Diagram
SDO
D15
D14
D1
D0
t
DIS
SCK
1
2
3
15
16
17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
-
040
CS
Figure 40. 4-Wire
Mode with Busy Indicator Serial Interface Timing
Preliminary Technical Data
AD7693
Rev. PrB | Page 21 of 24
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7693s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7693s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7693 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7693s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.
CLK
CONVERT
DATA IN
DIGITAL HOST
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
AD7693
B
AD7693
A
-041
Figure 41. Chain Mode Without Busy Indicator Connection Diagram
SDO
A
= SDI
B
D
A
15
D
A
14
D
A
13
SCK
1
2
3
30
31
32
t
SSDISCK
t
HSDISC
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
D
A
1
14
15
t
SCK
t
SCKL
t
SCKH
D
A
0
17
18
16
SDI
A
= 0
SDO
B
D
B
15
D
B
14
D
B
13
D
A
1
D
B
1
D
B
0
D
A
15
D
A
14
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
D
A
0
-042
Figure 42. Chain Mode Without Busy Indicator Serial Interface Timing
AD7693
Preliminary Technical Data
Rev. PrB | Page 22 of 24
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy chain multiple AD7693s
on a 3-wire serial interface while providing a BUSY indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7693s is shown
in Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7693 ADC labeled C in Figure 43) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7693 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7693s in the
chain, provided the digital host has an acceptable hold time.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
AD7693
B
AD7693
C
AD7693
A
-043
Figure 43. Chain Mode with Busy Indicator Connection Diagram
SDO
A
= SDI
B
D
A
15 D
A
14 D
A
13
SCK
1
2
3
35
47
48
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDI
A
D
A
1
4
15
t
SCK
t
SCKH
t
SCKL
D
A
0
17
34
16
SDO
B
= SDI
C
D
B
15 D
B
14 D
B
13
D
A
1
D
B
1
D
B
0 D
A
15 D
A
14
49
t
SSDISCK
t
HSDISC
t
HSDO
t
DSDO
SDO
C
D
C
15 D
C
14 D
C
13
D
A
1
D
A
0
D
C
1
D
C
0
D
A
14
19
31
32
18
33
D
B
1
D
B
0 D
A
15
D
B
15 D
B
14
t
DSDOSDI
t
SSCKCNV
t
HSCKCNV
D
A
0
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
-
044
Figure 44. Chain Mode with Busy Indicator Serial Interface Timing
Preliminary Technical Data
AD7693
Rev. PrB | Page 23 of 24
APPLICATION HINTS
-
045
LAYOUT
The printed circuit board that houses the AD7693 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7693, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7693 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7693s.
Figure 45. Example Layout of the AD7693 (Top Layer)
-046
The AD7693 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7693
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7693 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of a layout following these rules is shown in
Figure 45 and Figure 46.
EVALUATING THE AD7693'S PERFORMANCE
Figure 46. Example Layout of the AD7693 (Bottom Layer)
Other recommended layouts for the AD7693 are outlined
in the documentation of the evaluation board for the AD7693
(
EVAL-AD7693-CB
). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3
.
AD7693
Preliminary Technical Data
Rev. PrB | Page 24 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.23
0.08
0.80
0.60
0.40
8
0
0.15
0.05
0.33
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10
6
5
1
0.50 BSC
PIN 1
COPLANARITY
0.10
3.10
3.00
2.90
3.10
3.00
2.90
5.15
4.90
4.65
Figure 47.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
3.00
BSC SQ
INDEX
ARE A
TOP VIEW
1.50
BCS SQ
EXPOSED
PAD
(BOT TOM VIEW)
1.74
1.64
1.49
2.48
2.38
2.23
1
6
10
0.50
BSC
0.50
0.40
0.30
5
PIN 1
INDICATOR
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.55 TYP
SIDE VIEW
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
QFN Package in development. Contact sales for samples and availability.
Figure 48. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature
Range
Ordering
Quantity
Package Description
Package Option
Branding
EVAL-AD7693CB
Evaluation Board
1
EVAL-CONTROL BRD2
Controller
Board
2
EVAL-CONTROL BRD3
Controller
Board
2
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
2
These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05793-9/06(PrB)
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