AD7762 625 kSPS, 24-Bit, 109 dB Sigma-Delta ADC With On-Chip Buffer Data Sheet (Rev. 0)
625 kSPS, 24-Bit, 109 dB
- ADC
With On-Chip Buffer
AD7762
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
120 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 625 kHz output data rate
112 dB SNR at 78 kHz output data rate
106 dB SNR at 625 kHz output data rate
625 kHz maximum fully filtered output word rate
Programmable over-sampling rate (32 to 256)
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or
user-programmable coefficients
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power-down modes
Synchronization of multiple devices via SYNC pin
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
05477-001
AD7762
V
IN+
V
IN
AV
DD1
AGND
MCLK
DGND
V
DRIVE
AV
DD2
AV
DD3
AV
DD4
DV
DD
DECAPA/B
R
BIAS
SYNC
RESET
DB0 TO DB15
CS
DRDY
RD/WR
CONTROL LOGIC
I/O
OFFSET AND GAIN
REGISTERS
DIFF
MULTIBIT
-
MODULATOR
RECONSTRUCTION
V
REF+
FIR FILTER
ENGINE
PROGRAMMABLE
DECIMATION
BUF
Figure 1.
GENERAL DESCRIPTION
The AD7762 is a high performance, 24-bit - analog-to-
digital converter (ADC). It combines wide input bandwidth
and high speed with the benefits of - conversion with a
performance of 106 dB SNR at 625 kSPS, making it ideal for
high speed data acquisition. Wide dynamic range combined
with significantly reduced antialiasing requirements simplify
the design process. An integrated buffer to drive the reference,
a differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7762 a compact, highly integrated
data acquisition device requiring minimal peripheral com-
ponent selection. In addition, the device offers programmable
decimation rates, and the digital FIR filter can be adjusted if
the default characteristics are not appropriate to the application.
The AD7762 is ideal for applications demanding high SNR
without a complex front end signal processing design.
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of low-
pass filters, the final filter having default or user-programmable
coefficients. The sample rate, filter corner frequencies, and output
word rate are set by a combination of the external clock frequency
and the configuration registers of the AD7762.
The reference voltage supplied to the AD7762 determines the
analog input range. With a 4 V reference, the analog input range
is 3.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.
The AD7762 is available in an exposed paddle, 64-lead TQFP
and is specified over the industrial temperature range from
-40C to +85C.
Table 1. Related Devices
Part No.
Description
AD7760
24-bit, 2.5 MSPS, 100 dB -, parallel interface
AD7763
24-bit, 625 kSPS, 109 dB -, serial interface
AD7762
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
General Description ......................................................................... 1
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
AD7762 Interface............................................................................ 14
Reading Data............................................................................... 14
Sharing the Parallel Bus ............................................................. 14
Writing to the AD7762 .............................................................. 14
Reading Status and Other Registers......................................... 14
Clocking the AD7762 ................................................................ 15
Example 1 .................................................................................... 15
Example 2 .................................................................................... 15
Driving the AD7762....................................................................... 16
Using the AD7762 ...................................................................... 17
Bias Resistor Selection ............................................................... 17
Decoupling and Layout Recommendations................................ 18
Supply Decoupling ..................................................................... 19
Additional Decoupling .............................................................. 19
Reference Voltage Filtering ....................................................... 19
Differential Amplifier Components ........................................ 19
Layout Considerations............................................................... 19
Programmable FIR Filter............................................................... 20
Downloading a User-Defined Filter ............................................ 21
Example Filter Download ......................................................... 21
AD7762 Registers ........................................................................... 23
Control Register 1--Reg 0x0001 .............................................. 23
Control Register 2--Address 0x0002 ...................................... 23
Status Register (Read Only) ...................................................... 24
Offset Register--Address 0x0003............................................. 24
Gain Register--Address 0x0004............................................... 24
Overrange Register--Address 0x0005..................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
8/05--Revision 0: Initial Version
AD7762
Rev. 0 | Page 3 of 28
SPECIFICATIONS
AV
DD1
= DV
DD
= V
DRIVE
= 2.5 V, AV
DD2
= AV
DD3
= AV
DD4
= 5 V, V
REF
= 4.096 V, MCLK amplitude = 5 V, T
A
= 25C, normal mode,
using on-chip amplifier with components as shown in Table 8, unless otherwise noted.
1
Table 2.
Parameter Test
Conditions/Comments
Specification
Unit
DYNAMIC PERFORMANCE
Decimate by 256
MCLK = 40 MHz, ODR = 78 kHz, FIN = 1 kHz
Dynamic Range
Modulator inputs shorted
119
120.5
dB min
dB typ
Signal-to-Noise Ratio (SNR)
2
Input amplitude = -0.5 dBFS
112
dB typ
Input amplitude = -60 dBFS
59
dB typ
Spurious-Free Dynamic Range (SFDR)
Nonharmonic, input amplitude = -6 dBFS
126
dBc typ
Input amplitude = -60 dBFS
77
dBc typ
Total Harmonic Distortion (THD)
Input amplitude = -0.5 dBFS
-105
dB typ
Input amplitude = -6 dBFS
-106
dB typ
Input amplitude = -60 dBFS
-75
dB typ
Decimate by 64
MCLK = 40 MHz, ODR = 312.5 kHz, F
IN
= 1 kHz
Dynamic Range
Modulator inputs shorted
112
114
dB min
dB typ
Signal-to-Noise Ratio (SNR)
2
Input amplitude = -0.5 dBFS
109.5
dB typ
Spurious-Free Dynamic Range (SFDR)
Nonharmonic, input amplitude = -6 dBFS
126
dBc typ
Decimate by 32
MCLK = 40 MHz, ODR = 625 kHz, FIN =100 kHz
Dynamic Range
Modulator inputs shorted
108
109.5
dB min
dB typ
Signal-to-Noise Ratio (SNR)
2
Input amplitude = -0.5 dBFS
107
dB typ
Spurious-Free Dynamic Range (SFDR)
Nonharmonic, input amplitude = -6 dBFS
120
dBc typ
Total Harmonic Distortion (THD)
Input amplitude = -0.5 dBFS
-108
dB typ
Input amplitude = -6 dBFS
-106
dB typ
DC ACCURACY
Resolution
24
Bits
Differential Nonlinearity
Guaranteed monotonic to 24 bits
Integral Nonlinearity
0.00076
% typ
Zero Error
0.014
% typ
0.02
%
max
Gain Error
0.015
% typ
Zero Error Drift
0.019
%/C typ
Gain Error Drift
0.0002
%/C typ
DIGITAL FILTER RESPONSE
Decimate by 32
Group Delay
MCLK = 40 MHz
47
s typ
Decimate by 64
Group Delay
MCLK = 40 MHz
91.5
s typ
Decimate by 256
Group Delay
MCLK = 40 MHz
358
s typ
ANALOG INPUT
Differential Input Voltage
V
IN
(+) V
IN
(-), V
REF
= 2.5 V
2
V p-p
V
IN
(+) V
IN
(-), V
REF
= 4.096 V
3.25
V p-p
Input Capacitance
At internal buffer inputs
5
pF typ
At modulator inputs
55
pF typ
AD7762
Rev. 0 | Page 4 of 28
Parameter Test
Conditions/Comments
Specification
Unit
REFERENCE INPUT/OUTPUT
V
REF
Input Voltage
V
DD3
= 3.3 V 5%
+2.5
V max
V
DD3
= 5 V 5%
+4.096
V max
V
REF
Input DC Leakage Current
6
A max
V
REF
Input Capacitance
5
pF max
POWER DISSIPATION
Total Power Dissipation
Normal mode
958
mW max
Low power mode
661
mW max
Standby Mode
Clock stopped
6.35
mW max
POWER REQUIREMENTS
AV
DD1
(Modulator Supply)
5%
+2.5
V
AV
DD2
(General Supply)
5%
+5
V
AV
DD3
(Diff Amp Supply)
+3.15/+5.25
V min/max
AV
DD4
(Ref Buffer Supply)
+3.15/+5.25
V min/max
DV
DD
5%
+2.5
V
V
DRIVE
+1.65/+2.7
V
min/max
Normal Mode
AI
DD1
(Modulator)
49/51
mA typ/max
AI
DD2
(General)
40/42
mA typ/max
AI
DD4
(Reference Buffer)
AV
DD4
= 5 V
34/36
mA typ/max
Low Power Mode
AI
DD1
(Modulator)
26/28
mA typ/max
AI
DD2
(General)
20/23
mA typ/max
AI
DD4
(Reference Buffer)
AV
DD4
= 5 V
9/10
mA typ/max
AI
DD3
(Diff Amp)
AV
DD3
= 5 V, both modes
41/44
mA typ/max
DI
DD
Both modes
63/70
mA typ/max
DIGITAL I/O
MCLK Input Amplitude
3
5
V typ
Input Capacitance
7.3
pF typ
Input Leakage Current
5
A max
Three-State Leakage Current (D15:D0)
5
A max
V
INH
0.7
V
DRIVE
V
min
V
INL
0.3
V
DRIVE
V
max
V
OH
4
1.5
V
min
V
OL
4
0.1
V
max
1
See the Terminology section.
2
SNR specifications in dBs are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
3
While the AD7762 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated.
4
Tested with a 400 A load current.
AD7762
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
AV
DD1
= DV
DD
= V
DRIVE
= 2.5 V, AV
DD2
= AV
DD3
= AV
DD4
= 5 V, T
A
= 25C, normal mode, unless otherwise noted.
Table 3.
Parameter
Limit at T
MIN
, T
MAX
Unit
Description
f
MCLK
1
MHz min
Applied master clock frequency
40
MHz
max
f
ICLK
500
kHz min
Internal modulator clock derived from MCLK
20
MHz
max
t
1
1 , 2
0.5 t
ICLK
typ
DRDY pulse width
t
2
10
ns
min
DRDY falling edge to CS falling edge
t
3
3
ns
min
RD/WR setup time to CS falling edge
t
4
(0.5 t
ICLK
) + 16 ns
max
Data access time
t
5
t
ICLK
min
CS low read pulse width
t
6
t
ICLK
min
CS high pulse width between reads
t
7
3
ns
min
RD/WR hold time to CS rising edge
t
8
11
ns max
Bus relinquish time
t
9
4 t
ICLK
min
CS low write pulse width
t
10
4 t
ICLK
min
CS high period between address and data
t
11
5
ns min
Data setup time
t
12
0
ns min
Data hold time
1
t
ICLK
= 1/f
ICLK
.
2
When ICLK = MCLK, DRDY pulse width depends on the mark/space ratio of applied MCLK.
TIMING DIAGRAMS
DATA MSW
LSW + STATUS
05477-002
t
5
t
8
t
7
t
6
t
3
t
4
t
2
t
1
D[0:15]
CS
RD/WR
DRDY
Figure 2. Parallel Interface Timing Diagram
t
9
D[0:15]
CS
RD/WR
t
10
t
11
t
12
REGISTER ADDRESS
REGISTER DATA
05477-004
Figure 3. AD7762 Register Write
AD7762
Rev. 0 | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Table 4.
Parameters Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AV
DD1
to GND
-0.3 V to +3 V
AV
DD2
AV
DD4
to GND
-0.3 V to +6 V
DV
DD
to GND
-0.3 V to +3 V
V
DRIVE
to GND
-0.3 V to +3 V
V
IN+
, V
IN
to GND
-0.3 V to +6 V
Digital input voltage to GND
1
-0.3 V to DV
DD
+ 0.3 V
-0.3 V to +6 V
MCLK to MCLKGND
V
REF
to GND
2
-0.3 V to AV
DD4
+ 0.3 V
AGND to DGND
-0.3 V to +0.3 V
10 mA
Input Current to Any Pin
Except Supplies
3
Operating Temperature Range
-40C to +85C
Commercial
-65C to +150C
Storage Temperature Range
150C
Junction Temperature
TQFP Exposed Paddle Package
JA
Thermal Impedance
92.7C/W
JC
Thermal Impedance
5.1C/W
Lead Temperature, Soldering
215C
Vapor Phase (60 sec)
220C
Infrared (15 sec)
ESD 600
V
1
Absolute maximum voltage on digital inputs is 3.0 V or DV
DD
+ 0.3 V,
whichever is lower.
2
Absolute maximum voltage on V
REF
input is 6.0 V or AV
DD4
+ 0.3 V,
whichever is lower.
3
Transient currents of up to 200 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7762
Rev. 0 | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
DGND
63
V
DRIV
E
62
DGND
61
DB0
60
DB1
59
DB2
58
DB3
57
DB4
56
DB5
55
DB6
54
DB7
53
DGND
52
DB8
51
DB9
50
DB1
0
49
DB1
1
47
DB13
46
DB14
45
DB15
42
DGND
43
DGND
44
V
DRIVE
48
DB12
41
DV
DD
40
CS
39
RD/WR
37
RESET
36
SYNC
35
DGND
34
AGND1
33
AV
DD1
38
DRDY
2
MCLKGND
3
MCLK
4
AV
DD2
7
AGND1
6
AV
DD1
5
AGND2
1
DGND
8
DECAPA
9
REFGND
10
V
REF+
12
AV
DD4
13
AGND2
14
AV
DD2
15
AV
DD2
16
AGND2
11
AGND4
PIN 1
17
R
BIAS
18
AGND2
19
V
IN
A+
20
V
IN
A
21
V
OUT
A
22
V
OUT
A+
23
AGND3
24
AV
DD3
25
V
IN
+
26
V
IN
27
AV
DD2
28
AGND2
29
AGND3
30
DE
CAP
B
31
AGND3
32
AGND3
AD7762
TOP VIEW
(Not to Scale)
05477-005
Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
6, 33
AV
DD1
2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 with 100 nF and 10 F
capacitors on each pin.
4, 14, 15, 27
AV
DD2
5 V Power Supply. These pins should be decoupled to AGND2 with 100 nF capacitors on each of Pin 4,
Pin 14, and Pin 15. Pin 27 should be connected to Pin 14 via a 15 nH inductor.
24 AV
DD3
3.3 V to 5 V Power Supply for Differential Amplifier. These pins should be decoupled to AGND3 with a
100 nF capacitor.
12 AV
DD4
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND4 with a
10 nF capacitor in series with a 10 resistor.
7, 34
AGND1
Power Supply Ground for Analog Circuitry Powered by AV
DD1
.
5, 13, 16, 18, 28
AGND2
Power Supply Ground for Analog Circuitry Powered by AV
DD2
.
23, 29, 31, 32
AGND3
Power Supply Ground for Analog Circuitry Powered by AV
DD3
.
11
AGND4
Power Supply Ground for Analog Circuitry Powered by AV
DD4
.
9
REFGND
Reference Ground. Ground connection for the reference voltage.
41 DV
DD
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a
100 nF capacitor.
44, 63
V
DRIVE
Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating
voltage of the logic interface. Both these pins must be connected together and tied to the same supply.
Each pin should also be decoupled to DGND with a100 nF capacitor.
DGND
Ground Reference for Digital Circuitry.
1, 35, 42, 43,
53, 62, 64
19 V
IN
A+
Positive Input to Differential Amplifier.
20 V
IN
A-
Negative Input to Differential Amplifier.
21 V
OUT
A-
Negative Output from Differential Amplifier.
22 V
OUT
A+ Positive
Output
from
Differential Amplifier.
25 V
IN
+
Positive Input to the Modulator.
26 V
IN
-
Negative Input to the Modulator.
10 V
REF+
Reference Input. The input range of this pin is determined by the reference buffer supply voltage
(AV
DD4
). See the Reference Voltage Filtering section for more details.
8
DECAPA
Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1.
AD7762
Rev. 0 | Page 8 of 28
Pin No.
Mnemonic
Description
30
DECAPB
Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
17 R
BIAS
Bias Current Setting Pin. A resistor must be inserted between this pin and AGND1. For more details, see
the Bias Resistor Selection section.
45 to 52,
54 to 61
DB15 to DB8
DB7 to DB0
16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR
pin. The operating voltage for these pins is determined by the V
DRIVE
voltage. See the AD7762 Interface
section for more details.
37
RESET
A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin
low keeps the AD7762 in a reset state.
3 MCLK
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends
on the frequency of this clock. See the section Clocking the AD7762 for more details.
2
MCLKGND
Master Clock Ground Sensing Pin.
36
SYNC
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to
synchronize multiple devices in a system.
39
RD/WR
Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and
from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a
write occurs. See the AD7762 Interface section for more details.
38
DRDY
Data Ready Output. Each time that new conversion data is available, an active low pulse,
ICLK period
wide, is produced on this pin. See the AD7762 Interface section for more details.
40
CS
Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the
AD7762. See the AD7762 Interface section for more details.
AD7762
Rev. 0 | Page 9 of 28
TERMINOLOGY
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1-LSB
change between any two adjacent codes in the ADC.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7762, it is defined as
Zero Error Drift
The change in the actual zero error value due to a temperature
change of 1C. It is expressed as a percentage of the zero error at
room temperature.
( )
1
6
5
4
3
2
V
V
V
V
V
V
THD
2
2
2
2
2
log
20
dB
+
+
+
+
=
where:
Gain Error
The first transition (from 100...000 to 100...001) should occur
for an analog voltage 1/2 LSB above the nominal negative full
scale. The last transition (from 011...110 to 011...111) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale. The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition, from the difference between the ideal levels.
V
1
is the rms amplitude of the fundamental.
V
2
, V
3
, V
4
, V
5
,.and V
6
are the rms amplitudes of the second to
the sixth harmonics.
Nonharmonic Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, excluding harmonics.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Gain Error Drift
The change in the actual gain error value due to a temperature
change of 1C. It is expressed as a percentage of the gain error at
room temperature.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
AD7762
Rev. 0 | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
AV
DD1
= DV
DD
= V
DRIVE
= 2.5 V, AV
DD2
= AV
DD3
= AV
DD4
= 5 V, V
REF
= 4.096 V, T
A
= 25C, normal mode, unless otherwise noted. All FFTs
are generated from 65536 samples using a 7-term Blackman-Harris window.
0
4000
8000
12000
16000
20000
200
0
25
50
75
100
125
150
175
24000
FREQUENCY (Hz)
AMP
L
ITUDE
(dB)
05477-009
0
4000
8000
12000
16000
20000
200
0
25
50
75
100
125
150
175
24000
FREQUENCY (Hz)
AMP
LITUDE
(dB)
05477-006
Figure 8. Low Power FFT, 1 kHz, -0.5 dB Input Tone, 256 Decimation
Figure 5. Normal Mode FFT, 1 kHz, -0.5 dB Input Tone, 256 Decimation
0
4000
8000
12000
16000
20000
200
0
25
50
75
100
125
150
175
24000
FREQUENCY (Hz)
AMP
LITUDE
(dB)
05477-010
0
4000
8000
12000
16000
20000
200
0
25
50
75
100
125
150
175
24000
FREQUENCY (Hz)
AMP
LITUDE
(dB)
05477-007
Figure 6. Normal Mode FFT, 1 kHz, -6 dB Input Tone, 256 Decimation
Figure 9. Low Power FFT, 1 kHz, -6 dB Input Tone, 256 Decimation
0
4000
8000
12000
16000
20000
200
0
25
50
75
100
125
150
175
24000
FREQUENCY (Hz)
AMP
LITUDE
(dB)
05477-011
0
4000
8000
12000
16000
20000
200
0
25
50
75
100
125
150
175
24000
FREQUENCY (Hz)
AMP
LITUDE
(dB)
05477-008
Figure 7. Normal Mode FFT, 1 kHz, -60 dB Input Tone, 256 Decimation
Figure 10. Low Power FFT, 1 kHz, -60 dB Input Tone, 256 Decimation
AD7762
Rev. 0 | Page 11 of 28
05477-060
FREQUENCY (Hz)
AMP
LITUDE
(dB)
25
0
50
75
100
125
150
175
200
60000
0
120000
180000
240000
300000
05477-063
FREQUENCY (Hz)
AMP
LITUDE
(dB)
25
0
50
75
100
125
150
175
200
60000
0
120000
180000
240000
300000
Figure 11. Normal Mode FFT, 100 kHz, -0.5 dB Input Tone, 32 Decimation
Figure 14. Low Power FFT, 100 kHz, -0.5 dB Input Tone, 32 Decimation
05477-061
FREQUENCY (Hz)
AMP
LITUDE
(dB)
25
0
50
75
100
125
150
175
200
60000
0
120000
180000
240000
300000
05477-064
FREQUENCY (Hz)
AMP
LITUDE
(dB)
25
0
50
75
100
125
150
175
200
60000
0
120000
180000
240000
300000
Figure 12. Normal Mode FFT, 100 kHz, -6 dB Input Tone, 32 Decimation
Figure 15. Low Power FFT, 100 kHz, -6 dB Input Tone, 32 Decimation
05477-062
DECIMATION RATE (x)
S
NR (dBFS
)
120
106
0
256
118
116
114
112
110
108
64
128
192
0.5dB
60dB
6dB
05477-065
DECIMATION RATE (x)
S
NR (dBFS
)
116
104
0
256
64
128
192
112
108
60dB
0.5dB
6dB
Figure 13. Normal Mode SNR vs. Decimation Rate, 1 kHz Input Tone
Figure 16. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone
AD7762
Rev. 0 | Page 12 of 28
4500
0
8385222
05477-055
24-BIT CODE
OCCURRE
NCE
4000
3500
3000
2500
2000
1500
1000
500
8385238
8385254
8385270
3000
0
8383530
05477-058
24-BIT CODE
OCCURRE
NCE
2500
2000
1500
1000
500
83835246 8383562 8383578 8383594 8383610
Figure 17. Normal Mode, 24-Bit Histogram, 256 Decimation
Figure 20. Low Power, 24-Bit Histogram, 256 Decimation
0.0010
0.0010
0
16777216
05477-056
24-BIT CODE
INL (
%
)
0.0005
0
0.0005
4194304
8388608
12582912
+25
C
40
C
+85
C
0.0015
0.0010
0
16777216
05477-059
24-BIT CODE
INL (
%
)
0.0005
0.0010
0
0.0005
4194304
8388608
12582912
+25
C
40
C
+85
C
Figure 18. 24-Bit INL, Normal Mode
Figure 21. 24-Bit INL, Low Power Mode
0.6
0.6
0
16777216
05477-057
24-BIT CODE
DNL (LS
B
)
4194304
8388608
12582912
0.4
0.2
0
0.2
0.4
Figure 19. 24-Bit DNL
AD7762
Rev. 0 | Page 13 of 28
THEORY OF OPERATION
The AD7762 employs a - conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
rate to be chosen from 4 to 32. The third filter has a fixed
decimation rate of 2, is user programmable, and has a default
configuration. It is described in detail in the Programmable FIR
Filter section. This filter can be bypassed.
Due to the high oversampling rate, that spreads the
quantization noise from 0 to f
ICLK
, the noise energy contained in
the band of interest is reduced (
Table 6 lists some characteristics of the default filter. The group
delay of the filter is defined to be the delay to the center of the
impulse response and is equal to the computation + filter delays.
The delay until valid data is available (the DVALID status bit is
set) is equal to 2 the filter delay + the computation delay.
Figure 22 a). To further reduce
the quantization noise, a high order modulator is employed to
shape the noise spectrum; so that most of the noise energy is
shifted out of the band of interest (Figure 22 b).
04975-037
QUANTIZATION NOISE
f
ICLK
\2
BAND OF INTEREST
a.
f
ICLK
\2
NOISE SHAPING
BAND OF INTEREST
b.
f
ICLK
\2
BAND OF INTEREST
DIGITAL FILTER CUTOFF FREQUENCY
c.
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (Figure 22 c) while also
reducing the data rate from f
ICLK
at the input of the filter to
f
ICLK
/8 or less at the output of the filter, depending on the
decimation rate used.
Digital filtering has certain advantages over analog filtering. It
does not introduce significant noise or distortion and can be
made perfectly linear phase.
The AD7762 employs three FIR filters in series. By using
different combinations of decimation ratios and filter selection
and bypassing, data can be obtained from the AD7762 at a large
range of data rates. The first filter receives data from the
modulator at ICLK MHz where it is decimated by four to
output data at ICLK/4 MHz. This partially filtered data can also
be output at this stage. The second filter allows the decimation
Figure 22. - ADC
Table 6. Configuration with Default Filter
ICLK
Frequency
Computation
Delay
Filter 1
Filter 2
Filter 3
Data State
Filter
Delay
Pass-Band
Bandwidth
Output Data
Rate (ODR)
20 MHz
4
4
2
Fully filtered
1.775 s
44.4 s
250 kHz
625 kHz
20 MHz
4
8
Bypassed
Partially filtered
2.6 s
10.8 s
140.625 kHz
625 kHz
20 MHz
4
8
2
Fully filtered
2.25 s
87.6 s
125 kHz
312.5 kHz
20 MHz
4
16
Bypassed
Partially filtered
4.175 s
20.4 s
70.3125 kHz
312.5 kHz
20 MHz
4
16
2
Fully filtered
3.1 s
174 s
62.5 kHz
156.25 kHz
20 MHz
4
32
Bypassed
Partially filtered
7.325 s
39.6 s
35.156 kHz
156.25 kHz
20 MHz
4
32
2
Fully filtered
4.65 s
346.8 s
31.25 kHz
78.125 kHz
12.288 MHz
4
8
2
Fully filtered
3.66 s
142.6 s
76.8 kHz
192 kHz
12.288 MHz
4
16
2
Fully filtered
5.05 s
283.2 s
38.4 kHz
96 kHz
12.288 MHz
4
32
Bypassed
Partially filtered
11.92 s
64.45 s
21.6 kHz
96 kHz
12.288 MHz
4
32
2
Fully filtered
7.57 s
564.5 s
19.2 kHz
48 kHz
AD7762
Rev. 0 | Page 14 of 28
AD7762 INTERFACE
READING DATA
The AD7762 uses a 16-bit bidirectional parallel interface. This
interface is controlled by the RD/WR and CS pins.
When a new conversion result is available, an active low pulse is
output on the DRDY pin. To read a conversion result from the
AD7762, two 16-bit read operations are performed. The DRDY
pulse indicates that a new conversion result is available. Both
RD/WR and CS go low to perform the first read operation.
Shortly after both these lines go low, the data bus becomes
active and the 16 most significant bits (MSBs) of the conversion
result are output. The RD/WR and CS lines must return high
for a full ICLK period before the second read is performed. This
second read contains the 8 least significant bits (LSBs) of the
conversion result along with 6 status bits. These status bits are
shown in Table 7. Descriptions of the other status bits are in
Table 15.
Table 7. Status Bits During Data Read
D7
D0
DValid Ovr UFilt LPwr FiltOk DLOk 0
0
Shortly after RD/WR and CS return high, the data bus returns
to a high impedance state. Both read operations must be
completed before a new conversion result is available because
the new result overwrites the contents on the output register.
If a DRDY pulse occurs during a read operation, the data read
is invalid.
SHARING THE PARALLEL BUS
By its nature, the high accuracy of the AD7762 makes it
sensitive to external noise sources. These include digital activity
on the parallel bus. For this reason, it is recommended that the
AD7762 data lines are isolated from the system data bus by
means of a latch or buffer to ensure that there is no digital
activity on the D0 to D15 pins that is not controlled by the
AD7762. If multiple, synchronized AD7762 parts that share a
properly distributed common MCLK signal exist in a system,
these parts can share a common bus without being isolated
from each other. This bus can then be isolated from the system
bus by a single latch or buffer.
WRITING TO THE AD7762
While the AD7762 is configured to convert analog signals with
the default settings on reset, there are many features and
parameters on this part that the user can change by writing to
the device. Because some of the programmable registers are
16 bits wide, two write operations are required to program a
register. The first write contains the register address while the
second write contains the register data. An exception is when a
user filter is being downloaded to the AD7762. This is
described in detail in the Downloading a User-Defined Filter
section. The AD7762 Registers section contains the register
addresses and more details.
Figure 3 shows a write operation to the AD7762. The RD/WR
line is held high while the CS line is brought low for a minimum
of 4 ICLK periods. The register address is latched during this
period. The CS line is brought high again for a minimum of
4 ICLK periods before the register data is put onto the data bus.
If a read operation occurs between the writing of the register
address and the register data, the register address is cleared and
the next write must be the register address again. This also
provides a method to get back to a known situation if the user
forgets whether the next write is an address or data.
Generally, the AD7762 is written to and configured on power-
up and very infrequently, if at all, after that. Following any write
operation, the full group delay of the filter must pass before
valid data is output from the AD7762.
READING STATUS AND OTHER REGISTERS
The AD7762 features a number of programmable registers. To
read back the contents of these registers or the status register, the
user must first write to the control register of the device, setting
a bit corresponding to the register to be read. The next read
operation outputs the contents of the selected register instead
of a conversion result. The AD7762 Registers section provides
more information on the relevant bits in the control register.
AD7762
Rev. 0 | Page 15 of 28
CLOCKING THE AD7762
EXAMPLE 2
The AD7762 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal.
The ICLK controls the internal operations of the AD7762. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
Take a second example from Table 6, where:
ODR
= 48 kHz
f
ICLK
= 12.288 MHz
f
IN
(max) = 19.2 kHz
SNR
= 120 dB
ps
133
10
10
2
.
19
2
256
6
3
)
(
=
=
rms
j
t
ICLK = MCLK
(CDIV = 1)
The input amplitude also has an effect on these jitter figures.
If, for example, the input level was 3 dB below full scale, the
allowable jitter would be increased by a factor of 2, increasing
the first example to 2.53 ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
ICLK = MCLK
/2 (CDIV = 0)
These options are selected from the control register (see the
AD7762 Registers section for more details). On power-up, the
default is ICLK = MCLK/2 to ensure that the part can handle
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in
Figure 23 and Figure 24 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.
Table 6, output data rates
of 192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.
1
1.0
04975-038
0.5
0
0.5
The MCLK jitter requirements depend on a number of factors
and are given by
20
)
dB
(
)
(
10
2
SNR
IN
rms
j
f
OSR
t
=
where:
OSR
= Over-sampling ratio =
ODR
f
ICLK
f
IN
= Maximum input frequency
Figure 23. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p
SNR
(dB) = Target SNR
EXAMPLE 1
1
1.0
04975-039
0.5
0
0.5
This example can be taken from Table 6, where:
ODR
= 625 kHz
f
ICLK
= 20 MHz
f
IN
(max) = 250 kHz
SNR
= 108 dB
ps
6
.
3
10
10
250
2
32
6
3
)
(
=
=
rms
j
t
This is the maximum allowable clock jitter for a full-scale,
250 kHz input tone with the given ICLK and output data rate.
Figure 24. Maximum Slew Rate of Same Frequency Sine Wave with
Amplitude of 1 V p-p
AD7762
Rev. 0 | Page 16 of 28
DRIVING THE AD7762
04975-041
+2.5V
0V
2.5V
+2.5V
0V
2.5V
+3.685V
+2.048V
+0.410V
+3.685V
+2.048V
+0.410V
A
V
IN
+
V
IN
B
The AD7762 has an on-chip differential amplifier that operates
with a supply voltage (AV
DD3
) from 3.15 V to 5.25 V. For a 4.096
V reference, the supply voltage must be 5 V.
To achieve the specified performance in normal mode, the
differential amplifier should be configured as a first-order
antialias filter, as shown in Figure 25. Any additional filtering
should be carried out in previous stages using low noise, high
performance op amps, such as the AD8021.
Suitable component values for the first-order filter are listed in
Table 8. The values in Table 8 yield a 10 dB attenuation at the
first alias point of 19 MHz.
Figure 26. Differential Amplifier Signal Conditioning
04975-040
A1
R
IN
R
FB
C
FB
R
IN
R
M
R
M
C
S
R
FB
C
FB
V
IN
A
B
V
IN
+
04975-042
A1
R
IN
R
FB
C
FB
R
IN
R
M
R
M
C
S
R
FB
C
FB
V
IN
V
IN
V
IN
+
AD8021
2R
2R
R
Figure 25. Differential Amplifier Configuration
Table 8. Normal Mode Component Values
Figure 27. Single-Ended-to-Differential Conversion
V
REF
R
IN
R
FB
R
M
C
S
C
FB
4.096 V
1 k
655
18
5.6 pF
33 pF
05477-043
CS2
CPB2
SS4
SH4
CPA
SS2
SH2
CS1
CPB1
SS3
SH3
SS1
SH1
ANALOG
MODULATOR
V
IN
+
Figure 26 shows the signal conditioning that occurs using the
circuit in Figure 25 with a 2.5 V input signal biased around
ground and having the component values and conditions in
Table 8. The differential amplifier always biases the output
signal to sit on the optimum common mode of V
REF
/2, in this
case 2.048 V. The signal is also scaled to give the maximum
allowable voltage swing with this reference value. This is
calculated as 80% of V
REF
, that is, 0.8 4.096 V 3.275 V p-p
on each input.
To obtain maximum performance from the AD7762, it is
advisable to drive the ADC with differential signals.
Figure 28. Equivalent Input Circuit
Figure 27
shows how a bipolar, single-ended signal biased around ground
can drive the AD7762 with the use of an external op amp, such
as the AD8021.
The AD7762 employs a double sampling front end, as shown in
Figure 28. For simplicity, only the equivalent input circuit for V
IN
+
is shown. The equivalent input circuitry for V
IN
- is the same.
With a 4.096 V reference, a 5 V supply must be provided to the
reference buffer (AV
DD4
). With a 2.5 V reference, a 3.3 V supply
must be provided to AV
DD4
.
AD7762
Rev. 0 | Page 17 of 28
The sampling switches SS1 and SS3 are driven by ICLK, whereas
the sampling switches SS2 and SS4 are driven by ICLK. When
ICLK is high, the analog input voltage is connected to CS1. On
the falling edge of ICLK, the SS1 and SS3 switches open, and the
analog input is sampled on CS1. Similarly, when ICLK is low, the
analog input voltage is connected to CS2. On the rising edge of
ICLK, the SS2 and SS4 switches open, and the analog input is
sampled on CS2.
Capacitors CPA, CPB1, and CPB2 represent parasitic capacitances
that include the junction capacitances associated with the MOS
switches.
Table 9. Equivalent Component Values
Mode CS1 CS2 CPA CPB1/2
Normal
51 pF
51 pF
12 pF
20 pF
Low Power
13 pF
13 pF
12 pF
5 pF
USING THE AD7762
The following is the recommended sequence for powering up
and using the AD7762.
1.
Apply power.
2.
Start the clock oscillator, applying MCLK.
3.
Take RESET low for a minimum of 1 MCLK cycle.
4.
Wait a minimum of 2 MCLK cycles after RESET has been
released.
5.
Write to Control Register 2 to power up the ADC and the
differential amplifier as required. The correct clock divider
(CDIV) ratio should be programmed now.
6.
Write to Control Register 1 to set the output data rate.
7.
Wait a minimum of 5 MCLK cycles after CS has been
released.
8.
Take SYNC low for a minimum of 4 MCLK cycles, if
required, to synchronize multiple parts.
Data can then be read from the part using the default filter,
offset, gain, and overrange threshold values. The conversion
data read is not valid, however, until the group delay of the filter
has passed. When this has occurred, the DVALID bit read with
the data LSW is set, indicating that the data is indeed valid.
The user can then download a different filter, if required
(see Downloading a User-Defined Filter). Values for gain, offset,
and overrange threshold registers can be written or read at this
stage.
BIAS RESISTOR SELECTION
The AD7762 requires a resistor to be connected between the
R
BIAS
pin and AGND1. The value for this resistor is dependant
on the reference voltage being applied to the device. The resistor
value should be selected to give a current of 25 A through the
resistor to ground. For a 2.5 V reference voltage, the correct
resistor value is 100 k and for a 4.096 V reference, the correct
resistor value is 160 k.
AD7762
Rev. 0 | Page 18 of 28
DECOUPLING AND LAYOUT RECOMMENDATIONS
Due to the high performance nature of the AD7762, correct decoupling and layout techniques are required to obtain the performance as
stated within this datasheet. Figure 29 shows a simplified connection diagram for the AD7762.
V
IN
A+
V
IN
A
V
OUT
A
V
OUT
A+
INA+
INA
OUTA
OUTA+
DECAPA
DECAPB
V
IN
+
V
IN
V
REF
+
VIN+
VIN
VREF
REFGND
R
BIAS
DGND
DGND
DGND
DGND
DGND
DGND
DGND
19
20
21
22
8
30
25
26
10
9
17
1
35
42
43
53
62
64
DB0
DB2
DB1
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB0
DB2
DB1
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
CS
RD/WR
RESET
SYNC
DRDY
MCLK
MCLKGND
CS
RD/WR
RESET
SYNC
DRDY
MCLK
AGND1
AGND1
AGND2
AGND2
AGND2
AGND2
AGND2
AGND3
AGND3
AGND3
AGND3
AGND4
7
34
5
13
16
18
28
23
29
31
32
11
AV
DD2
AV
DD2
AV
DD2
AV
DD4
AV
DD1
AV
DD1
AV
DD3
AV
DD2
V
DRI
VE
V
DRI
VE
DV
DD
PIN 1
4
PIN 1
5
PIN 4
PIN 12
PIN 6
PIN 3
3
PIN 2
4
PIN 2
7
PIN 4
4
PIN 6
3
PIN 41
14
15
4
12
6
33
24
27
44
63
41
AD7762BSV
61
60
59
58
55
54
50
49
46
45
40
37
36
38
3
2
57
56
52
51
48
47
39
R19
160k
C64
33pF
C7
100nF
DB (0:15)
U2
AV
DD3
PIN 24
(VDIF1)
C54
100nF
L6
DV
DD
PIN 41
(DVDD)
C58
100nF
L8
AV
DD2
PIN 4
(RHS)
C48
100nF
L1
PIN 15
(VBIAS)
C50
100nF
L3
PIN 14
(LHS)
PIN 27
C62
100nF
L2
L9
AV
DD4
PIN 12
(VBUF)
C59
10nF
L4
R38
10
AV
DD1
PIN 5
(VMOD1)
C52
100nF
L5
PIN 33
(VMOD2)
C53
100nF
L11
V
DRIVE
PIN 44
(VDRV1)
C56
100nF
L7
PIN 63
(VDRV2)
C57
100nF
L12
05477-
046
Figure 29. Simplified Connection Diagram
AD7762
Rev. 0 | Page 19 of 28
SUPPLY DECOUPLING
DIFFERENTIAL AMPLIFIER COMPONENTS
Every supply pin must be connected to the appropriate supply
via a ferrite bead and decoupled to the correct ground pin with
a 100 nF, 0603 case size, X7R dielectric capacitor. There are two
exceptions to this:
The correct components for use around the on-chip differential
amplifier are detailed in Table 8. Matching the components on
both sides of the differential amplifier is important to minimize
distortion of the signal applied to the amplifier. A tolerance of
0.1% or better is required for these components. Symmetrical
routing of the tracks on both sides of the differential amplifier
also assists in achieving stated performance.
Pin 12 (AV
DD4
) must have a 10 resistor inserted between
the pin and a 10 nF decoupling capacitor.
Pin 27 (AV
DD2
) does not require a separate decoupling
capacitor or a direct connection to the supply, but instead
is connected to Pin 14 via a 15 nH inductor.
LAYOUT CONSIDERATIONS
While using the correct components is essential to achieve
optimum performance, the correct layout is just as important.
The Design Tools section of the AD7762 product page on
the Analog Devices website contains the gerber files for the
AD7762 evaluation board. These files should be used as a
reference when designing any system using the AD7762.
ADDITIONAL DECOUPLING
There are two other decoupling pins on the AD7762--Pin 8
(DECAPA) and Pin 30 (DECAPB). Pin 8 should be decoupled
with a 100 nF capacitor, and Pin 30 requires a 33 pF capacitor.
The location and orientation of some of the components
mentioned in previous sections is critical, and particular
attention must be paid to the components which are located
close to the AD7762. Locating these components further away
from the devices can have a direct impact on the maximum
performance achievable.
REFERENCE VOLTAGE FILTERING
A low noise reference source, such as the ADR431 (2.5 V) or
ADR434 (4.096 V), is suitable for use with the AD7762. The
reference voltage supplied to the AD7762 should be decoupled
and filtered, as shown in Figure 30.
The recommended scheme for the reference voltage supply
is a 100 series resistor connected to a 100 F tantalum
capacitor, followed by series resistor of 10 , and finally a
10 nF decoupling capacitor very close to the V
REF+
pin.
The use of ground planes also should be carefully considered.
To ensure that the return currents through the decoupling
capacitors are flowing to the correct ground pin, the ground
side of the capacitors should be as close to the ground pin
associated with that supply. A ground plane should not be relied
on as the sole return path for decoupling capacitors because the
return current path using ground planes is not easily
predictable.
04975-
047
+12V
PIN10
VOUT
2 +VIN
6
4
C15
10
F
C9
100nF
C10
100nF
R30
100
R17
10
+
C46
10nF
C11
100
F
+
ADR434
GND
U3
Figure 30. Reference Connection
AD7762
Rev. 0 | Page 20 of 28
PROGRAMMABLE FIR FILTER
As previously mentioned, the third FIR filter on the AD7762 is
user programmable. The default coefficients that are loaded on
reset are given in
To create a filter, note the following:
The filter must be even, symmetrical FIR.
Table 10 and the frequency responses are
shown in Figure 31. The frequencies quoted in Figure 31 scale
directly with the output data rate.
The coefficients are in sign-and-magnitude format with
26 magnitude bits and sign coded as positive = 0.
Table 10. Default Filter Coefficients
The filter length must be between 12 taps and 96 taps in
steps of 12.
No.
Dec.
Value
Hex
Value
No.
Dec.
Value
Hex
Value
0 53656736 332BCA0 24
700847 AB1AF
Because the filter is symmetrical, the number of
coefficients that must be downloaded is half the filter
length. The default filter coefficients exemplify this with
only 48 coefficients listed for a 96-tap filter.
1 25142688 17FA5A0 25
-70922 401150A
2 -4497814 444A196 26
-583959
408E917
3 -11935847
4B62067 27
-175934
402AF3E
4 -1313841 4140C31 28
388667 5EE3B
5 6976334 6A734E 29
294000 47C70
Coefficients are written from the center of impulse
response (adjacent to the point of symmetry) outwards.
6 3268059 31DDDB 30
-183250
402CBD2
7 -3794610 439E6B2 31
-302597
4049E05
The coefficients are scaled so that the in-band gain of the
filter is equal to 134217726 with the coefficients rounded
to the nearest integer. For a low-pass filter, this is the
equivalent of having the coefficients sum arithmetically
(including sign) to a 67108863 (0x3FF FFFF) positive
value over the half-impulse response coefficient set
(maximum 48 coefficients). Any deviation from this
introduces a gain error.
8 -3747402 4392E4A 32
16034 3EA2
9 1509849 1709D9 33
238315 3A2EB
10 3428088
344EF8
34 88266
158CA
11 80255
1397F
35 -143205 4022F65
12 -2672124 428C5FC 36 -128919 401F797
13 -1056628 4101F74 37 51794
CA52
14 1741563
1A92FB 38 121875 1DC13
15 1502200
16EBF8 39 16426
402A
16 -835960
40CC178 40 -90524 401619C
20
40
60
80
100
120
140
160
0
100
400
500
300
200
600
FREQUENCY (kHz)
AMP
L
ITUDE
(dB)
0
05477-044
0.1dB FREQUENCY = 251kHz
PASS-BAND RIPPLE = 0.05dB
STOP BAND = 312.5kHz
3dB FREQUENCY = 256kHz
17 -1528400 4175250 41 -63899 400F99B
18 93626
16DBA
42 45234
B0B2
19 1269502
135EFE
43 114720 1C020
20 411245
6466D
44 102357 18FD5
21 -864038
40D2F26 45 52669
CDBD
22 -664622
40A242E 46 15559
3CC7
23 434489
6A139
47 1963
7AB
The default filter should be sufficient for almost all applications.
It is a standard brick wall filter with a symmetrical impulse
response. The default filter has a length of 96 taps in non-
aliasing with 120 dB of attenuation at Nyquist. This filter not
only performs signal antialiasing, but also suppresses out-of-
band quantization noise produced by the analog-to-digital
conversion process. Any significant relaxation in the stop-band
attenuation or transition bandwidth relative to the default filter
can result in a failure to meet the SNR specifications.
Figure 31. Default Filter Frequency Response (625 kHz ODR)
The procedure for downloading a user-defined filter is detailed
in the Downloading a User-Defined Filter section.
AD7762
Rev. 0 | Page 21 of 28
DOWNLOADING A USER-DEFINED FILTER
EXAMPLE FILTER DOWNLOAD
As previously mentioned, the filter coefficients are 27 bits in
length; 1 sign and 26 magnitude bits. Because the AD7762
has a 16-bit parallel bus, the coefficients are padded with
5 MSB 0s to generate a 32-bit word and split into two 16-bit
words for downloading. The first 16-bit word for each coefficient
becomes (00000, Sign bit, Magnitude [25:16]), while the second
word becomes (Magnitude [15:0]). To ensure that a filter is
down-loaded correctly, a checksum must also be generated and
then downloaded following the final coefficient. The checksum
is a 16-bit word generated by splitting each 32-bit word into
4 bytes and summing all bytes from all coefficients up to a
maximum of 192 bytes (48 coefficients 4 bytes). The same
checksum is generated internally in the AD7762 and compared
with the checksum downloaded. The DL_OK bit in the status
register is set if these two checksums agree.
The following is an example of downloading a short user-
defined filter with 24 taps. The frequency response is shown
in Figure 32.
10
80
0
600
04975-045
FREQUENCY (kHz)
AMP
L
ITUDE
(dB)
0
10
20
30
40
50
60
70
100
200
300
400
500
To download a user filter:
1.
Write to Control Register 1, setting the DL_Filt bit and
also the correct filter length bits corresponding to the
length of the filter to be downloaded (see
Table 11).
Figure 32. 24-Tap FIR Frequency Response
2.
Write the first half of the current coefficient data
(00000, Sign bit, Magnitude [25:16]). The first coefficient
to be written must be the one adjacent to the point of filter
symmetry.
The coefficients for the filter are listed in Table 12 and are
shown from the center of symmetry outwards. The raw
coefficients were generated using a commercial filter
design tool and scaled appropriately so their sum equals
67108863 (0x3FF FFFF).
3.
Write the second half of the current coefficient data
(Magnitude [15:0]).
Table 12. 24-Tap FIR Coefficients
Coefficient Raw
Scaled
4.
Repeat Step 2 and Step 3 for each coefficient.
1 0.365481974
53188232
2 0.201339905
29300796
5.
Write the 16-bit checksum.
3 0.009636604
1402406
6.
Use these methods to verify that the filter coefficients are
downloaded correctly:
4 -0.075708848
-11017834
5 -0.042856209
-6236822
6 0.019944246
2902466
a.
Read the status register, checking the DL_OK bit.
7 0.036437914
5302774
b.
Read data and observe the status of the DL_OK bit.
8 0.007592007
1104856
9 -0.021556583
-3137108
Note that because the user coefficients are stored in RAM, they
are cleared after a
10 -0.024888355
-3621978
RESET operation or a loss of power.
11 -0.012379538
-1801582
Table 11. Filter Length Values
12 -0.001905756
-277343
FLEN[3:0]
Number of Coefficients
Filter Length
0000 Default
Default
0001 6
12
0011 12
24
0101 18
36
0111 24
48
1001 30
60
1011 36
72
1101 42
84
1111 48
96
AD7762
Rev. 0 | Page 22 of 28
Table 13 shows the hex values (in sign and magnitude format)
that are downloaded to the AD7762 to realize this filter. The
table is also split into the bytes that are all summed to produce
the checksum. The checksum generated from these coefficients
is 0x0E6B.
Table 13. Filter Hex Values
Word 1
Word 2
Coefficient
Byte 1
Byte 2
Byte 3
Byte 4
1
03 2B 96 88
2
01 BF 18 3C
3
00 15 66 26
4 04
A8
1E
6A
5 04
5F
2A
96
6
00 2C 49 C2
7 00
50
E9
F6
8 00
10
DB
D8
9 04
2F
DE
54
10
04 37 44 5A
11 04
1B
7D
6E
12 04
04
3B
5F
Table 14 lists the 16-bit words the user would write to the
AD7762 to set up the ADC and download this filter, assuming
an output data rate of 625 kHz has already been selected.
Table 14.
Word Description
0x0001
Address of Control Register 1.
0x8079
Control register data. DL filter, set filter length = 24,
set output data rate = 625 kHz.
0x032B
First coefficient, Word 1.
0x9688
First coefficient, Word 2.
0x01BF
Second coefficient, Word 1.
0x183C
Second coefficient, Word 2.
...
Other coefficients.
0x0404
Twelfth (final) coefficient, Word 1.
0x3B5F
Final coefficient, Word 2.
0x0E6B
Checksum. Wait (0.5 t
ICLK
Number of Unused
Coefficients) for AD7762 to fill remaining unused
coefficients with 0s.
0x0001
Address of control register.
0x0879
Control register data. Set read status and maintain
filter length and decimation settings. Read contents
of status register. Check Bit 7 (DL_OK) to determine
that the filter was downloaded correctly.
AD7762
Rev. 0 | Page 23 of 28
AD7762 REGISTERS
The AD7762 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter
configuration, the clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing to these registers
involves writing the register address first, then a 16-bit data-word. Register addresses, details of individual bits, and default values are
given here.
CONTROL REGISTER 1--REG 0X0001
Default Value 0x001A
MSB
LSB
DL_
Filt RD
Ovr RD
Gain RD
Off RD
Stat 0 SYNC FLEN3 FLEN2 FLEN1 FLEN0 BYP F3
1 DEC2 DEC1 DEC0
Table 15.
Bit Mnemonic Description
15 DL_Filt
1
Download Filter. Before downloading a user-defined filter, this bit must be set. The Filter Length bits must also be set at
this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until all the
coefficients and the checksum have been written.
14 RD
Ovr
1, 2
Read Overrange. If this bit has been set, the next read operation outputs the contents of the Overrange Threshold
Register instead of a conversion result.
13 RD
Gain
1, 2
Read Gain. If this bit has been set, the next read operation outputs the contents of the digital gain register.
12 RD
Off
1, 2
Read Offset. If this bit has been set, the next read operation outputs the contents of the digital offset register.
11 RD
Stat
1, 2
Read Status. If this bit has been set, the next read operation outputs the contents of the status register.
10
0
0 must be written to this bit.
9 SYNC
1
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple
devices synchronizes all filters.
8-5
FLEN3:0
Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded.
4
BYP F3
Bypass Filter 3. If this bit is 0, Filter 3 (programmable FIR) is bypassed.
3
1
1 must be written to this bit.
2-0 DEC2:0
Decimation Rate. These bits set the decimation rate of Filter 2. All 0s implies that the filter is bypassed. A value of 1
corresponds to 2 decimation, a value of 2 corresponds to 4 decimation, and so on up to the maximum value of 5,
corresponding to 32 decimation.
1
Bit 15 to Bit 9 are all self clearing bits.
2
Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation.
CONTROL REGISTER 2--ADDRESS 0X0002
Default Value 0x009B
MSB
LSB
0 0 0 0 0 0 0 0
0
0
CDIV
0 PD
LPWR
1
D1PD
Table 16.
Bit Mnemonic Description
5
CDIV
Clock Divider Bit. This sets the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV = 0 divides the
MCLK by 2. If CDIV = 1, then the ICLK frequency is equal to the MCLK.
3
PD
Power Down. Setting this bit powers down the AD7762, reducing the power consumption to 6.35 mW.
2 LPWR
Low Power. If this bit is set, the AD7762 is operating in a low power mode. The power consumption is reduced for a 6 dB
reduction in noise performance.
1
1
Write 1 to this bit.
0
D1PD
Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.
AD7762
Rev. 0 | Page 24 of 28
STATUS REGISTER (READ ONLY)
MSB
LSB
PART 1
PART 0
DIE 2
DIE 1
DIE 0
DVALID
LPWR
OVR
DL OK
Filter OK
U Filter
BYP F3
1 DEC2 DEC1 DEC0
Table 17.
Bit Mnemonic
Comment
15, 14
PART1:0
Part Number. These bits are constant for the AD7762.
13 to 11
DIE2:0
Die Number. These bits reflect the current AD7762 die number for identification purposes within a system.
10
DVALID
Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation.
9
LPWR
Low Power. If the AD7762 is operating in low power mode, this bit is set to 1.
8
OVR
If the current analog input exceeds the current overrange threshold, this bit is set.
7 DL
OK
When downloading a user filter to the AD7762, a checksum is generated. This checksum is compared to the one
downloaded following the coefficients. If these checksums agree, this bit is set.
6 Filter
OK
When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This
generated checksum is compared to the one downloaded. If they match, this bit is set.
5
U Filter
If a user-defined filter is in use, this bit is set.
4
BYP F3
Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
3
1
This bit is always set.
2-0
DEC2:0
Decimation Rate. These correspond to the bits set in Control Register 1.
OFFSET REGISTER--ADDRESS 0X0003
Non-bitmapped, Default Value 0x0000
The offset register uses twos complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum
negative value) correspond to an offset of +0.78125% and -0.78125%, respectively. Offset correction is applied after any gain correction.
Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately 25 mV.
GAIN REGISTER--ADDRESS 0X0004
Non-bitmapped, Default Value 0xA000
The gain register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a
full-scale digital output when the input is at 80% of V
REF
. This ties in with the maximum analog input range of 80% of V
REF
p-p.
OVERRANGE REGISTER--ADDRESS 0X0005
Non-bitmapped, Default Value 0xCCCC
The overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum
propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of V
REF
(the maximum permitted analog input voltage). Assuming V
REF
= 4.096 V, the bit is then set when the input voltage exceeds
approximately 6.55 V p-p differential. Note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of V
REF
for more than four consecutive samples at the modulator rate.
AD7762
Rev. 0 | Page 25 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90
CCW
SEATING
PLANE
0 MIN
7
3.5
0
0.15
0.05
49
64
1
17
16
32
33
48
1.20
MAX
0.75
0.60
0.45
VIEW A
TOP VIEW
(PINS DOWN)
PIN 1
49
64
17
1
16
32
33
48
0.50
BSC
LEAD PITCH
0.38
0.32
0.22
BOTTOM VIEW
(PINS UP)
7.50
BSC SQ
EXPOSED
PAD
12.20
12.00 SQ
11.80
10.20
10.00 SQ
9.80
Figure 33. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7762BSVZ
-40C to +85C
64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
SV-64-4
1
AD7762BSVZ-REEL
-40C to +85C
64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
SV-64-4
1
EVAL-AD7762EB
Evaluation
Board
1
Z = Pb-free part.
AD7762
Rev. 0 | Page 26 of 28
NOTES
AD7762
Rev. 0 | Page 27 of 28
AD7762
Rev. 0 | Page 28 of 28
NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0547708/05(0)
Document Outline
- FEATURES
- APPLICATIONS
-
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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