FUNCTIONAL BLOCK DIAGRAM
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
250 MHz, Voltage Output
4-Quadrant Multiplier
AD835
PRODUCT DESCRIPTION
The AD835 is a complete four-quadrant voltage output analog
multiplier fabricated on an advanced dielectrically isolated
complementary bipolar process. It generates the linear product
of its X and Y voltage inputs, with a 3 dB output bandwidth of
250 MHz (a small signal rise time of 1 ns). Full-scale (1 V to
+1 V) rise/fall times are 2.5 ns (with the standard R
L
of 150
)
and the settling time to 0.1% under the same conditions is typi-
cally 20 ns.
Its differential multiplication inputs (X, Y) and its summing in-
put (Z) are at high impedance. The low impedance output volt-
age (W) can provide up to
2.5 V and drive loads as low as
25
. Normal operation is from
5 V supplies.
Though providing state-of-the-art speed, the AD835 is simple
to use and versatile. For example, as well as permitting the addi-
tion of a signal at the output, the Z input provides the means
to operate the AD835 with voltage gains up to about
10. In
this capacity, the very low product noise of this multiplier
(50 nV
Hz
) makes it much more useful than earlier products.
The AD835 is available in an 8-pin plastic mini-DIP package
(N) and an 8-pin SOIC (R) and is specified to operate over the
40
C to +85
C industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD835 is the first monolithic 250 MHz four quadrant
voltage output multiplier.
2. Minimal external components are required to apply the
AD835 to a variety of signal processing applications.
3. High input impedances (100 k
2 pF) make signal source
loading negligible.
4. High output current capability allows low impedance loads
to be driven.
5. State of the art noise levels achieved through careful device
optimization and the use of a special low noise bandgap volt-
age reference.
6. Designed to be easy to use and cost effective in applications
which formerly required the use of hybrid or board level
solutions.
FEATURES
Simple: Basic Function is W = XY + Z
Complete: Minimal External Components Required
Very Fast: Settles to 0.1% of FS in 20 ns
DC-Coupled Voltage Output Simplifies Use
High Differential Input Impedance X, Y and Z Inputs
Low Multiplier Noise: 50 nV/
Hz
APPLICATIONS
Very Fast Multiplication, Division, Squaring
Wideband Modulation and Demodulation
Phase Detection and Measurement
Sinusoidal Frequency Doubling
Video Gain Control and Keying
Voltage Controlled Amplifiers and Filters
Y1
Y2
Z INPUT
Y = Y1
Y2
X = X1
X2
XY + Z
X1
X2
W OUTPUT
XY
AD835
+1
Analog Devices, Inc., 1994
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD835SPECIFICATIONS
Model
AD835AN/AR
TRANSFER FUNCTION
W
=
( X 1 X 2)(Y 1 Y 2)
U
+
Z
Parameter
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS (X, Y)
Differential Voltage Range
V
CM
= 0
1
V
Differential Clipping Level
1.2
1.4
V
Low Frequency Nonlinearity
X =
1 V, Y = 1 V
0.3
0.5
% FS
Y =
1 V, X = 1 V
0.1
0.3
% FS
vs. Temperature
T
MIN
to T
MAX
1
X =
1 V, Y = 1 V
0.7
% FS
Y =
1 V, X = 1 V
0.5
% FS
Common-Mode Voltage Range
2.5
+3
V
Offset Voltage
3
20
mV
vs. Temperature
T
MIN
to T
MAX
1
25
mV
CMRR
f
100 kHz;
1 V p-p
70
dB
Bias Current
10
20
A
vs. Temperature
T
MIN
to T
MAX
1
27
A
Offset Bias Current
2
A
Differential Resistance
100
k
Single-Sided Capacitance
2
pF
Feedthrough, X
X =
1 V, Y = 0 V
46
dB
Feedthrough, Y
Y =
1 V, X = 0 V
60
dB
DYNAMIC CHARACTERISTICS
3 dB Small-Signal Bandwidth
150
250
MHz
0.1 dB Gain Flatness Frequency
15
MHz
Slew Rate
W = 2.5 V to +2.5 V
1000
V/
s
Differential Gain Error, X
f = 3.58 MHz
0.3
%
Differential Phase Error, X
f = 3.58 MHz
0.2
Degrees
Differential Gain Error, Y
f = 3.58 MHz
0.1
%
Differential Phase Error, Y
f = 3.58 MHz
0.1
Degrees
Harmonic Distortion
X or Y = 10 dBm, 2nd and 3rd Harmonic
Fund = 10 MHz
70
dB
Fund = 50 MHz
40
dB
Settling Time, X or Y
To 0.1%, W = 2 V p-p
20
ns
SUMMING INPUT (Z)
Gain
From Z to W, f
10 MHz
0.990
0.995
3 dB Small-Signal Bandwidth
250
MHz
Differential Input Resistance
60
k
Single Sided Capacitance
2
pF
Maximum Gain
X, Y to W, Z Shorted to W, f = 1 kHz
50
dB
Bias Current
50
A
OUTPUT CHARACTERISTICS
Voltage Swing
2.2
2.5
V
vs. Temperature
T
MIN
to T
MAX
1
2.0
V
Voltage Noise Spectral Density
X = Y = 0, f < 10 MHz
50
nV/
Hz
Offset Voltage
25
75
mV
vs. Temperature
2
T
MIN
to T
MAX
1
10
mV
Short Circuit Current
75
mA
Scale Factor Error
5
8
% FS
vs. Temperature
T
MIN
to T
MAX
1
9
% FS
Linearity (Relative Error)
3
0.5
1.0
% FS
vs. Temperature
T
MIN
to T
MAX
1
1.25
% FS
POWER SUPPLIES
Supply Voltage
For Specified Performance
4.5
5
5.5
V
Quiescent Supply Current
16
25
mA
vs. Temperature
T
MIN
to T
MAX
1
26
mA
PSRR at Output vs. Vp
+4.5 V to +5.5 V
0.5
%/V
PSRR at Output vs. Vn
4.5 V to 5.5 V
0.5
%/V
NOTES
1
T
MIN
= 40
C, T
MAX
= +85
C.
2
Normalized to zero at +25
C.
3
Linearity is defined as residual error after compensating for input offset, output voltage offset and scale factor errors.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
REV. A
2
(T
A
= +25 C, V
S
= 5 V, R
L
= 150
, C
L
5 pF unless otherwise noted)
AD835
REV. A
3
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . 300 mW
Operating Temperature Range . . . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . . +300
C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
NOTES
1
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
2
Thermal Characteristics:
8-Pin Plastic DIP (N):
JC
= 35
C/W;
JA
= 90
C/W
8-Pin Plastic SOIC (R):
JC
= 45
C/W;
JA
= 115
C/W.
PIN CONNECTIONS
8-Pin Plastic DIP (N)
8-Pin Plastic SOIC (R)
Y1
Y2
VN
Z
X1
X2
VP
W
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD835
ORDERING GUIDE
Model
Temperature Range
Package Options*
AD835AN
40
C to +85
C
N-8
AD835AR
40
C to +85
C
R-8
*N = Plastic DIP; R = Small Outline IC Plastic Package (SOIC).
Figure 1. Typical Composite Output Differential Gain &
Phase, NTSC for X Channel; f = 3.58 MHz, R
L
= 150
Figure 3. Gain & Phase vs. Frequency of X, Y, Z Inputs
FREQUENCY Hz
1G
0.2
0.3
0.4
0.5
0.6
0.1
0
MAGNITUDE dB
X, Y CH = OdBm
R
L
= 150
C
L
5pF
1M
10M
100M
300k
Figure 4. Gain Flatness to 0.1 dB
0.20
0.20
0.10
0.10
0.00
0.03
0.00
0.16
0.10
0.07
0.04
0.01
0.00
0.20
0.01
0.00
0.00
DIFFERENTIAL
PHASE Degrees
DIFFERENTIAL
GAIN %
2ND
1ST
6TH
5TH
4TH
3RD
2ND
1ST
6TH
5TH
4TH
3RD
0.3
0.0
0.2
0.1
0.2
0.3
0.1
MIN = 0.02
MAX = 0.01
p-p/MAX = 0.03
MIN = 0.00
MAX = 0.16
p-p = 0.16
DG DP (NTSC) FIELD = 1 LINE = 18 Wfm FCC COMPOSITE
1M
10M
1G
100M
2
4
6
8
10
0
2
MAGNITUDE dB
FREQUENCY Hz
PHASE Degrees
0
90
180
90
180
PHASE
X, Y, Z CH = 0dBm
R
L
= 150
C
L
5pF
GAIN
Figure 2. Typical Composite Output Differential Gain &
Phase, NTSC for Y Channel; f = 3.58 MHz, R
L
= 150
0.4
0.4
0.2
0.2
0.0
0.02
0.00
0.06
0.03
0.03
0.02
0.06
0.00
0.20
0.19
0.16
0.11
DIFFERENTIAL
PHASE Degrees
DIFFERENTIAL
GAIN %
2ND
1ST
6TH
5TH
4TH
3RD
2ND
1ST
6TH
5TH
4TH
3RD
0.3
0.0
0.2
0.1
0.2
0.3
0.1
MIN = 0.00
MAX = 0.20
p-p/MAX = 0.20
MIN = 0.00
MAX = 0.06
p-p = 0.06
DG DP (NTSC) FIELD = 1 LINE = 18 Wfm FCC COMPOSITE
Typical Performance Characteristics
AD835
REV. A
4
Figure 7. Large Signal Pulse Response at W Output, R
L
=
150
, C
L
5 pF, X Channel =
1.0 V, Y Channel =
1.0 V
30
40
50
60
20
10
MAGNITUDE dB
FREQUENCY Hz
1M
10M
1G
100M
X FEEDTHROUGH
Y FEEDTHROUGH
X FEEDTHROUGH
Y FEEDTHROUGH
X, Y CH = 5dBm
R
L
= 150
C
L
< 5pF
Figure 6. Small Signal Pulse Response at W Output, R
L
=
150
, C
L
5 pF, X Channel =
0.2 V, Y Channel =
1.0 V
500mV
1V
GND
1V
10ns
Figure 9. PSRR vs. Frequency for V+ and V Supply
Figure 10. Harmonic Distortion at 10 MHz; 10 dBm Input
to X or Y Channels, R
L
= 150
, C
L
=
5 pF
40
50
60
20
10
30
PSRR dB
FREQUENCY Hz
1M
10M
1G
100M
300k
PSRR ON V+
PSRR ON V
0dBm ON SUPPLY
X, Y = 1V
60
80
0
40
20
CMRR dB
FREQUENCY Hz
1M
10M
1G
100M
Figure 8. CMRR vs. Frequency for X or Y Channel,
R
L
= 150
, C
L
5 pF
Figure 5. X and Y Feedthrough vs. Frequency
100mV
0.200V
GND
0.200V
10ns
10MHz
20MHz
30MHz
10dB/DIV
AD835
REV. A
5
Figure 16. Fixed IF vs. LO Frequency on Y Channel
Figure 12. Harmonic Distortion at 100 MHz, 10 dBm Input
to X or Y Channel, R
L
= 150
, C
L
5 pF
Figure 15. Fixed LO on Y Channel vs. RF Frequency
Input to X Channel
50MHz
100MHz
150MHz
10dB/DIV
15
15
10
0
5
10
5
125
35
55
45
25
5
15
105
85
65
TEMPERATURE
C
V
OS
OUTPUT DRIFT mV
OUTPUT V
OS
DRIFT, NORMALIZED TO 0 AT 25
C
OUTPUT OFFSET DRIFT WILL
TYPICALLY BE WITHIN SHADED AREA
Figure 14. V
OS
Output Drift vs. Temperature
Figure 11. Harmonic Distortion at 50 MHz, 10 dBm Input
to X or Y Channel, R
L
= 150
, C
L
5 pF
100MHz
200MHz
300MHz
10dB/DIV
1V
10ns
+2.5V
GND
2.5V
Figure 13. Maximum Output Voltage Swing, R
L
= 50
,
C
L
5 pF
35
0
15
5
10
20
25
30
200
20
0
180
160
80
60
40
140
120
100
LO FREQUENCY ON Y CH MHz
3RD ORDER INTERCEPT dBm
X CH = 6dBm
Y CH = 10dBm
R
L
= 100
35
0
15
5
10
20
25
30
200
20
0
180
160
80
60
40
140
120
100
RF FREQUENCY INPUT X CHANNEL MHz
3RD ORDER INTERCEPT dBm
X CH = 6dBm
Y CH = 10dBm
R
L
= 100
AD835
REV. A
6
Simplified representations of this sort, where all signals are pre-
sumed to be expressed in volts, are used throughout this data
sheet, to avoid the needless use of less-intuitive subscripted vari-
ables (such as V
X1
). We can view all variables as being normal-
ized to 1 V. For example, the input X can either be stated as
being in the range 1 V to +1 V, or simply 1 to +1. The latter
representation will be found to facilitate the development of new
functions using the AD835. The explicit inclusion of the de-
nominator, U, is also less helpful, as in the case of the AD835, if
it is not an electrical input variable.
Scaling Adjustment
The basic value of U in Equation 1 is nominally 1.05 V. Figure
18, which shows the basic multiplier connections, also
shows how the effective value of U can be adjusted to have any
lower voltage (usually 1 V) through the use of a resistive-divider
between W (Pin 5) and Z (Pin 4). Using the general resistor val-
ues shown, we can rewrite Equation 1 as
W
=
XY
U
+
kW
+
(1 k)Z ' (3)
(where Z' is distinguished from the signal Z at Pin 4). It follows
that
(4)
In this way, we can modify the effective value of U to
U '
=
(1 k)U (5)
without altering the scaling of the Z' input. (This is to be ex-
pected, since the only "ground reference" for the output is
through the Z' input.)
Thus, to set U' to 1 V, remembering that the basic value of U is
1.05 V, we need to choose R1 to have a nominal value of 20
times R2. The values shown here allow U to be adjusted
through the nominal range 0.95 V to 1.05 V, that is, R2 pro-
vides a 5% gain adjustment.
Figure 18. Multiplier Connections
Note that in many applications, the exact gain of the multiplier
may not be very important; in which case, this network may be
omitted entirely, or R2 fixed at 100
.
PRODUCT DESCRIPTION
The AD835 is a four-quadrant, voltage output, analog multi-
plier fabricated on an advanced, dielectrically isolated, comple-
mentary bipolar process. In its basic mode, it provides the linear
product of its X and Y voltage inputs. In this mode, the 3 dB
output voltage bandwidth is 250 MHz (a small signal rise time
of 1 ns). Full-scale (1 V to +1 V) rise/fall times are 2.5 ns (with
the standard R
L
of 150
) and the settling time to 0.1% under
the same conditions is typically 20 ns.
As in earlier multipliers from Analog Devices, a unique sum-
ming feature is provided at the Z-input. As well as providing in-
dependent ground references for inputs and output, and
enhanced versatility, this feature allows the AD835 to operate
with voltage
gain. Its X-, Y- and Z-input voltages are all nomi-
nally
1 V FS, with overrange of at least 20%. The inputs are
fully differential and at high impedance (100 k
2 pF) and pro-
vide a 70 dB CMRR (f
1 MHz).
The low impedance output is capable of driving loads as small
as 25
. The peak output can be as large as
2.2 V minimum
for R
L
= 150
, or
2.0 V minimum into R
L
= 50
. The
AD835 has much lower noise than the AD534 or AD734, mak-
ing it attractive in low level signal-processing applications, for
example, as a wideband gain-control element or modulator.
Basic Theory
The multiplier is based on a classic form, having a translinear
core, supported by three (X, Y, Z) linearized voltage-to-current
converters, and the load driving output amplifier. The scaling
voltage (the denominator U, in the equations below) is provided
by a bandgap reference of novel design, optimized for ultralow
noise. Figure 17 shows the functional block diagram.
In general terms, the AD835 provides the function
W
=
( X 1 X 2)(Y 1 Y 2)
U
+
Z
(1)
where the variables W, U, X, Y and Z are all voltages. Con-
nected as a simple multiplier, with X = X1 X2, Y = Y1 Y2
and Z = 0, and with a scale factor adjustment (see below) which
sets U = 1 V, the output can be expressed as
W = XY
(2)
Figure 17. Functional Block Diagram
Y1
Y2
Z INPUT
Y = Y1
Y2
X = X1
X2
XY + Z
X1
X2
W OUTPUT
XY
AD835
+1
W
=
XY
(1 k)U
+
Z '
R1 = (1k) R
2k
W
R2 = kR
200
+5V
+5V
X1
X2
VP
W
Z
VN
Y2
Y1
X1
AD835
FB
+5V
X
Y
5V
Z
1
FB
3
4
2
1
5
7
0.01
F CERAMIC
4.7
F TANTALUM
8
0.01
F CERAMIC
4.7
F TANTALUM
6
AD835
REV. A
7
APPLICATIONS
The AD835 is both easy to use and versatile. The capability for
adding another signal to the output at the Z input is frequently
valuable. Three applications of this feature are presented here: a
wideband voltage controlled amplifier, an amplitude modulator
and a frequency doubler. Of course, the AD835 may also be
used as a square law detector (with its X- and Y-inputs con-
nected in parallel) in which mode it is useful at input frequen-
cies to well over 250 MHz, since that is the bandwidth
limitation only of the output amplifier.
Multiplier Connections
Figure 18 shows the basic connections for multiplication. The
inputs will often be single sided, in which case the X2 and Y2
inputs will normally be grounded. Note that by assigning Pins 7
and 2 to these (inverting) inputs, respectively, an extra measure
of isolation between inputs and output is provided. The X and
Y inputs may, of course, be reversed to achieve some desired
overall sign with inputs of a particular polarity, or they may be
driven fully differentially.
Power supply decoupling and careful board layout are always
important in applying wideband circuits. The decoupling rec-
ommendations shown in Figure 18 should be followed closely.
In remaining figures in this data sheet, these power supply
decoupling components have been omitted for clarity, but
should be used wherever optimal performance with high speed
inputs is required. However, they may be omitted if the full high
frequency capabilities of AD835 are not being exploited.
A Wideband Voltage Controlled Amplifier
Figure 19 shows the AD835 configured to provide a gain of
nominally 0 to 12 dB. (In fact, the control range extends from
well under 12 dB to about +14 dB.) R1 and R2 set the gain to
be nominally
4. The attendant bandwidth reduction that
comes with this increased gain can be partially offset by the ad-
dition of the peaking capacitor C1. Although this circuit shows
the use of dual supplies, the AD835 can operate from a single
9 V supply with slight revision.
Figure 19. Voltage Controlled 50 MHz Amplifier Using the
AD835
The ac response of this amplifier for gains of 0 dB (V
G
=
0.25 V), 6 dB (V
G
= 0.5 V) and 12 dB (V
G
= 1 V) is shown in
Figure 20. In this application, the resistor values have been
slightly adjusted to reflect the nominal value of U = 1.05 V. The
overall sign of the gain may be controlled by the sign of V
G
.
V
IN
(SIGNAL)
R2
301
VOLTAGE
OUTPUT
X1
X2
VP
W
Z
VN
Y2
Y1
X1
AD835
+5V
5V
R1
97.6
3
4
2
1
5
6
7
8
C1
33pF
V
G
(GAIN CONTROL)
Figure 20. AC Response of VCA
An Amplitude Modulator
Figure 21 shows a simple modulator. The carrier is applied both
to the Y-input and the Z-input, while the modulating signal is
applied to the X-input. For zero modulation, there is no product
term, so the carrier input is simply replicated at unity gain by
the voltage follower action from the Z-input. At X = 1 V, the
RF output is doubled, while for X = 1 V, it is fully suppressed.
That is, an X-input of approximately
1 V (actually
U, or
about 1.05 V) corresponds to a modulation index of 100%. Car-
rier and modulation frequencies can be up to 300 MHz, some-
what beyond the nominal 3 dB bandwidth.
Of course, a suppressed carrier modulator can be implemented
by omitting the feedforward to the Z-input, grounding that pin
instead.
Figure 21. Simple Amplitude Modulator Using the AD835
Squaring and Frequency Doubling
Amplitude domain squaring of an input signal, E, is achieved
simply by connecting the X- and Y-inputs in parallel to pro-
duce an output of E
2
/U. The input may have either polarity, but
the output in this case will always be positive. The output polar-
ity may be reversed by interchanging either the X or Y inputs.
When the input is a sine wave E sin
t, a signal squarer behaves
as a frequency doubler, since
(6)
While useful, Equation 6 shows a dc term at the output which
will vary strongly with the amplitude of the input, E.
MODULATED
CARRIER
OUTPUT
MODULATION
INPUT
CARRIER
OUTPUT
X1
X2
VP
W
Z
VN
Y2
Y1
X1
AD835
+5V
5V
3
4
2
1
5
6
7
8
E sin
t
(
)
2
U
=
E
2
2U
(1 cos 2
t )
100k
100M
10M
1M
10k
12dB
(V
G
= 1V)
0dB
(V
G
= 0.25V)
6dB
(V
G
= 0.5V)
START 10 000.000Hz
STOP 100 000 000.000Hz
AD835
REV. A
8
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic DIP
(N Package)
8-Pin Plastic SOIC
(R Package)
PIN 1
0.280 (7.11)
0.240 (6.10)
4
5
8
1
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.430 (10.92)
0.348 (8.84)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
4
5
1
8
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.0098 (0.25)
0.0040 (0.10)
0.1968 (5.00)
0.1890 (4.80)
0.102 (2.59)
0.094 (2.39)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
Figure 22 shows a frequency doubler which overcomes this limi-
tation and provides a relatively constant output over a moder-
ately wide frequency range, determined by the time-constant C1
and R1. The voltage applied to the X- and Y-inputs are exactly
in quadrature at a frequency f = 1/2
C1R1 and their ampli-
tudes are equal. At higher frequencies, the X-input becomes
smaller while the Y-input increases in amplitude; the opposite
happens at lower frequencies. The result is a double frequency
output, centered on ground, whose amplitude of 1 V for a 1 V
input varies by only 0.5% over a frequency range of
10%. Be-
cause there is no "squared" dc component at the output, sud-
den changes in the input amplitude do not cause a "bounce" in
the dc level.
Figure 22. Broadband "Zero-Bounce" Frequency Doubler
This circuit is based on the identity
cos
sin
=
1
2
sin 2
( 7)
At
O
= 1/C1R1, the X input leads the input signal by 45
(and
is attenuated by
2
, while the Y input lags the input signal by
45
, and is also attenuated by
2.
Since the X and Y inputs are
90
out of phase, the response of the circuit will be
W
=
1
U
E
2
( sin
t 45
)
E
2
( sin
t
+
45
)
=
E
2
2U
( sin 2
t ) (8)
which has no dc component, R2 and R3 are included to restore
the output to 1 V for an input amplitude of 1 V (the same gain
adjustment as mentioned earlier). Because the voltage across the
capacitor, C1, decreases with frequency, while that across the
resistor, R1, increases, the amplitude of the output varies only
slightly with frequency. In fact, it is only 0.5% below its full
value (at its center frequency
= 1/C1R1) at 90% and 110%
of this frequency.
R1
R3
301
VOLTAGE
OUTPUT
X1
X2
VP
W
Z
VN
Y2
Y1
X1
AD835
+5V
5V
R2
97.6
3
4
2
1
5
6
7
8
C1
V
G
PRINTED IN U.S.A.
C1903a312/94
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