ChipFind - документация

Электронный компонент: AD8354

Скачать:  PDF   ZIP

Document Outline

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
2003 Analog Devices, Inc. All rights reserved.
AD8354
100 MHz to 2.7 GHz
RF Gain Block
FEATURES
Fixed Gain of 20 dB
Operational Frequency of 100 MHz to 2.7 GHz
Linear Output Power-Up to 4 dBm
Input/Output Internally Matched to 50
Temperature and Power Supply Stable
Noise Figure 4.2 dB
Power Supply 3 V or 5 V
APPLICATIONS
VCO Buffers
General Tx/Rx Amplification
Power Amplifier Predriver
Low Power Antenna Driver
FUNCTIONAL BLOCK DIAGRAM
BIAS AND VREF
COM1
INPT
VOUT
VPOS
COM2
AD8354
GENERAL DESCRIPTION
The AD8354 is a broadband, fixed-gain linear amplifier that
operates at frequencies from 100 MHz up to 2.7 GHz. It is
intended for use in a wide variety of wireless devices including
cellular, broadband, CATV, and LMDS/MMDS applications.
By taking advantage of Analog Devices' high performance
complementary Si bipolar process, these gain blocks provide
excellent stability over process, temperature, and power supply.
This amplifier is single-ended and internally matched to 50
with a return loss of greater than 10 dB over the full operating
frequency range.
The AD8354 provides linear output power of nearly 4.3 dBm
with 20 dB of gain at 900 MHz when biased at 3 V and an
external RF choke is connected between the power supply and
the output pin. The dc supply current is 24 mA. At 900 MHz,
the output third order intercept (OIP3) is greater than 18 dBm;
at 2.7 GHz, the OIP3 is 14 dBm.
The noise figure is 4.2 dB at 900 MHz. The reverse isolation
(S
12
) is 33 dB at 900 MHz.
The AD8354 can also operate with a 5 V power supply, in which
case no external inductor is required. Under these conditions,
the AD8354 delivers 4.8 dBm with 20 dB of gain at 900 MHz.
The dc supply current is 26 mA. At 900 MHz, the OIP3 is
greater than 19 dBm, and at 2.7 GHz, the OIP3 is 15 dBm.
The noise figure is 4.4 dB at 900 MHz. The reverse isolation
(S
12
) is 33 dB.
The AD8354 is fabricated on Analog Devices' proprietary, high
performance 25 GHz Si complementary bipolar IC process. The
AD8354 is available in a chip scale package that utilizes an exposed
paddle for excellent thermal impedance and low impedance
electrical connection to ground. It operates over a 40
C to
+85
C temperature range.
An evaluation board is available.
REV. A
2
AD8354SPECIFICATIONS
(V
S
= 3 V, T
A
= 25 C, 100 nH external inductor between VOUT and VPOS, Z
O
= 50
,
unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
0.1
2.7
GHz
Gain
f = 900 MHz
19.5
dB
f = 1.9 GHz
18.6
dB
f = 2.7 GHz
17.1
dB
Delta Gain
f = 900 MHz, 40
C T
A
+85C
0.97
dB
f = 1.9 GHz, 40
C T
A
+85C
1.05
dB
f = 2.7 GHz, 40
C T
A
+85C
1.33
dB
Gain Supply Sensitivity
VPOS
10%, f = 900 MHz
0.54
dB/V
f = 1.9 GHz
0.37
dB/V
f = 2.7 GHz
0.2
dB/V
Reverse Isolation (S
12
)
f = 900 MHz
33.5
dB
f = 1.9 GHz
38
dB
f = 2.7 GHz
32.9
dB
RF INPUT INTERFACE
Pin RFIN
Input Return Loss
f = 900 MHz
24.4
dB
f = 1.9 GHz
23
dB
f = 2.7 GHz
12.7
dB
RF OUTPUT INTERFACE
Pin VOUT
Output Compression Point
f = 900 MHz, 1 dB compression
4.6
dBm
f = 1.9 GHz
3.7
dBm
f = 2.7 GHz
2.7
dBm
Delta Compression Point
f = 900 MHz, 40
C T
A
+85C
0.7
dB
f = 1.9 GHz, 40
C T
A
+85C
0.7
dB
f = 2.7 GHz, 40
C T
A
+85C
0.8
dB
Output Return Loss
f = 900 MHz
23.6
dB
f = 1.9 GHz
16.5
dB
f = 2.7 GHz
14.6
dB
DISTORTION/NOISE
Output Third Order Intercept
f = 900 MHz, f = 1 MHz, P
IN
= 28 dBm
19
dBm
f = 1.9 GHz, f = 1 MHz, P
IN
= 28 dBm
16
dBm
f = 2.7 GHz, f = 1 MHz, P
IN
= 28 dBm
14.2
dBm
Output Second Order Intercept
f = 900 MHz, f = 1 MHz, P
IN
= 28 dBm
29.7
dBm
Noise Figure
f = 900 MHz
4.2
dB
f = 1.9 GHz
4.8
dB
f = 2.7 GHz
5.4
dB
POWER INTERFACE
Pin VPOS
Supply Voltage
2.7
3
3.3
V
Total Supply Current
16
23
31
mA
Supply Voltage Sensitivity
6.2
mA/V
Temperature Sensitivity
40
C T
A
+85C
33
A/C
Specifications subject to change without notice.
REV. A
AD8354
3
SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
0.1
2.7
GHz
Gain
f = 900 MHz
19.5
dB
f = 1.9 GHz
18.7
dB
f = 2.7 GHz
17.3
dB
Delta Gain
f = 900 MHz, 40
C T
A
+85C
0.93
dB
f = 1.9 GHz, 40
C T
A
+85C
0.99
dB
f = 2.7 GHz, 40
C T
A
+85C
1.21
dB
Gain Supply Sensitivity
VPOS
10%, f = 900 MHz
0.32
dB/V
f = 1.9 GHz
0.21
dB/V
f = 2.7 GHz
0.08
dB/V
Reverse Isolation (S
12
)
f = 900 MHz
33.5
dB
f = 1.9 GHz
37.6
dB
f = 2.7 GHz
32.9
dB
RF INPUT INTERFACE
Pin RFIN
Input Return Loss
f = 900 MHz
24.4
dB
f = 1.9 GHz
23.9
dB
f = 2.7 GHz
13.5
dB
RF OUTPUT INTERFACE
Pin VOUT
Output 1 dB Compression
f = 900 MHz
4.8
dBm
f = 1.9 GHz
4.6
dBm
f = 2.7 GHz
3.6
dBm
Delta Compression Point
f = 900 MHz, 40
C T
A
+85C
0.37
dB
f = 1.9 GHz, 40
C T
A
+85C
0.14
dB
f = 2.7 GHz, 40
C T
A
+85C
0.05
dB
Output Return Loss
f = 900 MHz
23.7
dB
f = 1.9 GHz
22.5
dB
f = 2.7 GHz
17.6
dB
DISTORTION/NOISE
Output Third Order Intercept
f = 900 MHz, f = 50 MHz, P
IN
= 30 dBm
19.3
dBm
f = 1.9 GHz, f = 50 MHz, P
IN
= 30 dBm
17.3
dBm
f = 2.7 GHz, f = 50 MHz, P
IN
= 30 dBm
15.3
dBm
Output Second Order Intercept
f = 900 MHz, f = 1 MHz, P
IN
= 28 dBm
28.7
dBm
Noise Figure
f = 900 MHz
4.4
dB
f = 1.9 GHz
5
dB
f = 2.7 GHz
5.6
dB
POWER INTERFACE
Pin VPOS
Supply Voltage
4.5
5
5.5
V
Total Supply Current
T
A
= 27
C
17
25
34
mA
Supply Voltage Sensitivity
4
mA/V
Temperature Sensitivity
40
C T
A
+85C
28
A/C
Specifications subject to change without notice.
(V
S
= 5 V, T
A
= 25 C, no external inductor between VOUT and VPOS, Z
O
= 50
, unless otherwise noted.)
REV. A
4
AD8354
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8354 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Power (re: 50
) . . . . . . . . . . . . . . . . . . . . . . . . 10 dBm
Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . 700 mV rms
Internal Power Dissipation
Paddle Not Soldered . . . . . . . . . . . . . . . . . . . . . . . . 325 mW
Paddle Soldered . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 mW
JA
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 200
C/W
JA
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . . 80
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150
C
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 240
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
1
NC = NO CONNECT
COM1
NC
INPT
COM1
VOUT
VPOS
COM2
COM2
AD8354
2
3
4
7
6
5
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
Branding
AD8354ACP-R2
40
C to +85C
8-Lead LFCSP
CP-8
JCA
AD8354ACP-REEL7
40
C to +85C
8-Lead LFCSP
CP-8
JCA
AD8354-EVAL
Evaluation Board
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1, 8
COM1
Device Common. Connect to low
impedance ground.
2
NC
No Connection.
3
INPT
RF Input Connection. Must be
ac-coupled.
4, 5
COM2
Device Common. Connect to low
impedance ground.
6
VPOS
Positive Supply Voltage.
7
VOUT
RF Output Connection. Must be
ac-coupled.
REV. A
Typical Performance CharacteristicsAD8354
5
180
150
120
90
60
30
0
330
300
270
240
210
TPC 1. S
11
vs. Frequency, V
S
= 3 V, T
A
= 25 C,
100 MHz
f 3.0 GHz
FREQUENCY (MHz)
0
0
3000
GAIN (dB)
1000
1500
2000
2500
25
20
15
GAIN AT 3.0V
GAIN AT 3.3V
GAIN AT 2.7V
10
5
500
TPC 2. Gain vs. Frequency, V
S
= 2.7 V, 3.0 V, and
3.3 V, T
A
= 25 C
FREQUENCY (MHz)
40
500
REVERSE ISOLA
T
ION (dB)
1000
15
20
25
30
35
S
12
AT 3.0V
S
12
AT 3.3V
S
12
AT 2.7V
1500 2000 2500 3000
10
5
0
0
TPC 3. Reverse Isolation vs. Frequency, V
S
= 2.7 V,
3 V, and 3.3 V, T
A
= 25 C
180
150
120
90
60
30
0
330
300
270
240
210
TPC 4. S
22
vs. Frequency, V
S
= 3 V, T
A
= 25 C,
100 MHz
f 3.0 GHz
FREQUENCY (MHz)
0
500
GAIN (dB)
1000
25
20
15
10
5
GAIN AT 40 C
GAIN AT +85 C
GAIN AT +25 C
1500
2000
2500
3000
0
TPC 5. Gain vs. Frequency, V
S
= 3 V, T
A
= 40 C,
+25 C, and +85 C
FREQUENCY (MHz)
40
500
REVERSE ISOLA
T
ION (dB)
1000
15
20
25
30
35
S
12
AT 40 C
1500 2000 2500 3000
10
5
0
S
12
AT +25 C
S
12
AT +85 C
0
TPC 6. Reverse Isolation vs. Frequency, V
S
= 3 V,
T
A
= 40 C, +25 C, and +85 C
REV. A
6
AD8354
FREQUENCY (MHz)
1
500
1000 1500 2000 2500 3000
P
1 d
B
(d
B
m
)
4
3
2
1
0
P
1 dB
AT 3.3V
5
6
7
P
1 dB
AT 3.0V
P
1 dB
AT 2.7V
0
TPC 7. P
1 dB
vs. Frequency, V
S
= 2.7 V, 3 V, and 3.3 V,
T
A
= 27 C
OUTPUT 1dB COMPRESSION POINT (dBm)
0
2.5
PERCENT
A
G
E
2.6
25
20
15
10
5
30
35
40
2.7 2.8
2.9 3.0 3.1
3.2 3.3
3.4
3.5 3.6 3.7
3.8
45
50
TPC 8. Distribution of P
1 dB
, V
S
= 3 V, T
A
= 25 C,
f = 2.2 GHz
FREQUENCY (MHz)
10
500
OIP3 (dBm)
1000
20
18
16
14
12
OIP3 AT 3.3V
1500 2000 2500 3000
22
OIP3 AT 3.0V
OIP3 AT 2.7V
0
TPC 9. OIP3 vs. Frequency, V
S
= 2.7 V, 3 V, and
3.3 V, T
A
= 25 C
FREQUENCY (MHz)
500
P
1 d
B
(dBm)
4
3
2
1
0
P
1 dB
AT 40 C
5
6
P
1 dB
AT +25 C
P
1 dB
AT +85 C
1000
1500
2000
2500
3000
0
TPC 10. P
1 dB
vs. Frequency, V
S
= 3 V, T
A
= 40 C,
+27 C, and +85 C
OIP3 (dBm)
0
14.4
PERCENT
A
G
E
25
20
15
10
5
30
35
40
45
50
14.6
14.8
15.0
15.2
15.4
15.6
15.8
16.0
TPC 11. Distribution of OIP3, V
S
= 3 V, T
A
= 25 C,
f = 2.2 GHz
FREQUENCY (MHz)
10
500
OIP3 (dBm)
20
18
16
14
12
1500 2000 2500 3000
22
1000
OIP3 AT +85 C
OIP3 AT 40 C
OIP3 AT +25 C
0
TPC 12. OIP3 vs. Frequency, V
S
= 3 V, T
A
= 40 C,
+25 C, and +85 C
REV. A
AD8354
7
FREQUENCY (MHz)
4.0
500
NOISE FIGURE (dB)
1000
NF AT 3.3V
NF AT 3.0V
NF AT 2.7V
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
2000
2500
1500
3000
0
TPC 13. Noise Figure vs. Frequency, V
S
= 2.7 V, 3 V,
and 3.3 V, T
A
= 25 C
NOISE FIGURE (dB)
0
4.70
PERCENT
A
G
E
25
20
15
10
5
30
35
40
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
TPC 14. Distribution of Noise Figure, V
S
= 3 V,
T
A
= 25 C, f = 2.2 GHz
180
150
120
90
60
30
0
330
300
270
240
210
TPC 15. S
11
vs. Frequency, V
S
= 5 V, T
A
= 25 C, 100
MHz
f 3 GHz
FREQUENCY (MHz)
3.0
500
NOISE FIGURE (dB)
1500
NF AT 40 C
3.5
4.0
4.5
5.0
5.5
6.5
6.0
NF AT +25 C
NF AT +85 C
1000
2500
2000
3000
0
TPC 16. Noise Figure vs. Frequency, V
S
= 3 V,
T
A
= 40 C, +25 C, and +85 C
TEMPERATURE ( C)
0
60
SUPPL
Y CURRENT (mA)
5
10
15
20
25
30
I
S
AT 3.0V
I
S
AT 3.3V
I
S
AT 2.7V
40
20
0
20
40
60
80
100
TPC 17. Supply Current vs. Temperature, V
S
= 2.7 V,
3 V, and 3.3 V
180
150
120
90
60
30
0
330
300
270
240
210
TPC 18. S
22
vs. Frequency, V
S
= 5 V, T
A
= 25 C,
100 MHz
f 3 GHz
REV. A
8
AD8354
FREQUENCY (MHz)
500
3000
GAIN (dB)
1000
1500
2000
2500
25
5
0
10
15
20
GAIN AT 5.0V
GAIN AT 4.5V
GAIN AT 5.5V
0
TPC 19. Gain vs. Frequency, V
S
= 4.5 V, 5.0 V, and
5.5 V, T
A
= 25 C
FREQUENCY (MHz)
40
500
REVERSE ISOLA
T
ION (dB)
1000
S
12
AT 5.0V
S
12
AT 4.5V
S
12
AT 5.5V
35
30
25
20
15
10
5
0
1500
2000
2500
3000
0
TPC 20. Reverse Isolation vs. Frequency, V
S
= 4.5 V,
5 V, and 5.5 V, T
A
= 25 C
0
P
1 d
B
(dBm)
P
1 dB
AT 5.0V
1
2
3
4
5
6
7
P
1 dB
AT 4.5V
P
1 dB
AT 5.5V
FREQUENCY (MHz)
500
1000
1500
2000
2500
3000
0
TPC 21. P
1 dB
vs. Frequency, V
S
= 4.5 V, 5 V, and
5.5 V, T
A
= 25 C
FREQUENCY (MHz)
0
500
GAIN (dB)
25
20
15
10
5
GAIN AT 40 C
GAIN AT +25 C
GAIN AT +85 C
1500
2000
2500
3000
0
1000
TPC 22. Gain vs. Frequency, V
S
= 5 V, T
A
= 40 C,
+25 C, and +85 C
FREQUENCY (MHz)
500
REVERSE ISOLA
T
ION (dB)
S
12
AT 40 C
30
25
20
15
10
5
0
S
12
AT +85 C
1000
1500
2000
2500
3000
0
S
12
AT +25 C
35
40
TPC 23. Reverse Isolation vs. Frequency, V
S
= 5 V,
T
A
= 40 C, +25 C, and +85 C
0
P
1 d
B
(dBm)
1
2
3
4
5
6
P
1 dB
AT 40 C
P
1 dB
AT +85 C
P
1 dB
AT +25 C
FREQUENCY (MHz)
500
1000
1500
2000
2500
3000
0
TPC 24. P
1 dB
vs. Frequency, V
S
= 5 V, T
A
= 40 C,
+25 C, and +85 C
REV. A
AD8354
9
OUTPUT 1 dB COMPRESSION POINT (dBm)
0
3.95
PERCENT
A
G
E
4.00
25
20
15
10
5
30
35
40
45
50
4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50
TPC 25. Distribution of P
1 dB
, V
S
= 5 V, T
A
= 25 C,
f = 2.2 GHz
10
12
14
16
18
20
22
OIP3 AT 5.5V
OIP3 AT 5.0V
OIP3 AT 4.5V
FREQUENCY (MHz)
500
1000
1500
2000
2500
3000
0
OIP3 (dBm)
TPC 26. OIP3 vs. Frequency, V
S
= 4.5 V, 5 V, and
5.5 V, T
A
= 25 C
FREQUENCY (MHz)
4.0
500
NOISE FIGURE (dB)
1000
NF AT 4.5V
NF AT 5.5V
NF AT 5.0V
4.5
5.0
6.0
1500
2000
2500
3000
6.5
5.5
7.0
0
TPC 27. Noise Figure vs. Frequency, V
S
= 4.5 V,
5 V, and 5.5 V, T
A
= 25 C
OIP3 (dBm)
0
16.0
PERCENT
A
G
E
25
20
15
10
5
30
35
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 17.0 17.1 17.2
TPC 28. Distribution of OIP3, V
S
= 5 V, T
A
= 25 C,
f = 2.2 GHz
10
OIP3 (dBm)
12
14
16
18
20
22
OIP3 AT 40 C
OIP3 AT +25 C
OIP3 AT +85 C
FREQUENCY (MHz)
1000
1500
2000
2500
3000
500
0
TPC 29. OIP3 vs. Frequency, V
S
= 5 V, T
A
= 40 C,
+25 C, and +85 C
FREQUENCY (MHz)
4.0
500
NOISE FIGURE (dB)
1000
NF AT 40 C
4.5
5.0
6.0
1500
2000
2500
3000
6.5
5.5
7.0
7.5
3.0
3.5
NF AT +85 C
NF AT +25 C
0
TPC 30. Noise Figure vs. Frequency, V
S
= 5 V,
T
A
= 40 C, +25 C, and +85 C
REV. A
10
AD8354
NOISE FIGURE (dB)
0
4.5
PERCENT
A
G
E
25
20
15
10
5
30
35
40
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
5.6
TPC 31. Distribution of Noise Figure, V
S
= 5 V,
T
A
= 25 C, f = 2.2 GHz
TEMPERATURE ( C)
0
60
SUPPL
Y CURRENT (mA)
5
10
15
20
25
30
I
S
AT 5.0V
I
S
AT 5.5V
I
S
AT 4.5V
40
20
0
20
40
60
80
100
35
TPC 32. Supply Current vs. Temperature, V
S
= 4.5 V,
5 V, and 5.5 V
P
IN
(dBm)
15
15
30
25
P
OUT
(dBm)
20
15
10
5
0
10
5
0
5
10
20
14
19
18
17
16
15
GAIN (dB)
TPC 33. Output Power and Gain vs. Input Power,
V
S
= 3 V, T
A
= 25 C, f = 900 MHz
P
IN
(dBm)
30
25
20
15
10
5
0
15
P
OUT
(dBm)
10
5
0
10
20
14
19
18
17
16
15
GAIN (dB)
5
15
TPC 34. Output Power and Gain vs. Input Power,
V
S
= 5 V, T
A
= 25 C, f = 900 MHz
REV. A
AD8354
11
THEORY OF OPERATION
The AD8354 is a two-stage feedback amplifier employing both
shunt-series and shunt-shunt feedback. The first stage is degen-
erated and resistively loaded, and provides approximately 10 dB
of gain. The second stage is a PNP-NPN Darlington output
stage, which provides another 10 dB of gain. Series-shunt feed-
back from the emitter of the output transistor sets the input
impedance to 50
over a broad frequency range. Shunt-shunt
feedback from the amplifier output to the input of the Darlington
stage helps to set the output impedance to 50
. The amplifier
can be operated from a 3 V supply by adding a choke inductor
from the amplifier output to VPOS. Without this choke inductor,
operation from a 5 V supply is also possible.
BASIC CONNECTIONS
The AD8354 RF gain block is a fixed-gain amplifier with single-
ended input and output ports whose impedances are nominally
equal to 50
over the frequency range 100 MHz to 2.7 GHz.
Consequently, it can be directly inserted into a 50
system
with no impedance matching circuitry required. The input and
output impedances are sufficiently stable versus variations in
temperature and supply voltage that no impedance matching
compensation is required. A complete set of scattering parameters
is available at the Analog Devices website (www.analog.com).
The input pin (INPT) is connected directly to the base of the
first amplifier stage, which is internally biased to approximately
1 V, so a dc-blocking capacitor should be connected between
the source that drives the AD8354 and the input pin, INPT.
It is critical to supply very low inductance ground connections
to the ground pins (Pins 1, 4, 5, and 8) as well as to the back-
side exposed paddle. This will ensure stable operation.
The AD8354 is designed to operate over a wide supply voltage
range from 2.7 V to 5.5 V. The output of the part, VOUT, is
taken directly from the collector of the output amplifier stage.
This node is internally biased to approximately 3.2 V when the
supply voltage is 5 V. Consequently, a dc-blocking capacitor
should be connected between the output pin, VOUT, and the
load that it drives. The value of this capacitor is not critical, but
it should be 100 pF or larger.
When the supply voltage is 3 V, it is recommended that an external
RF choke be connected between the supply voltage and the
output pin, VOUT. This will increase the dc voltage applied to
the collector of the output amplifier stage, which will improve
performance of the AD8354 to be very similar to the perfor-
mance produced when 5 V is used for the supply voltage. The
inductance of the RF choke should be approximately 100 nH.
Care should be taken to ensure that the lowest series self-resonant
frequency of this choke is well above the maximum frequency of
operation for the AD8354.
The supply voltage input, VPOS, should be bypassed using a large
value capacitance (approximately 0.47
F or larger) and a smaller,
high frequency bypass capacitor (approximately 100 pF) physi-
cally located close to the VPOS pin.
The recommended connections and components are shown in
the schematic of the AD8354 evaluation board (Figure 3).
APPLICATIONS
The AD8354 RF gain block may be used as a general-purpose
fixed-gain amplifier in a wide variety of applications, such as a
driver for a transmitter power amplifier (Figure 1). Its excellent
reverse isolation also makes this amplifier suitable for use as a
local oscillator buffer amplifier that would drive the local oscilla-
tor port of an up or down converter mixer (Figure 2).
AD8354
HIGH POWER
AMPLIFIER
Figure 1. AD8354 as a Driver Amplifier
MIXER
AD8354
LOCAL
OSCILLATOR
Figure 2. AD8354 as a LO Driver Amplifier
NC = NO CONNECT
COM1
NC
INPT
COM1
VOUT
VPOS
COM2
COM2
AD8354
C3
100pF
C4
0.47 F
VP
OUTPUT
1
2
3
4
5
6
7
8
C2
1000pF
C1
1000pF
INPUT
L1
Figure 3. Evaluation Board Schematic
EVALUATION BOARD
Figure 3 shows the schematic of the AD8354 evaluation board.
Note that L1 is shown as an optional component, which is used
to obtain maximum gain only when V
P
= 3 V. The board is
powered by a single supply in the 2.7 V to 5.5 V range. The
power supply is decoupled by 0.47
F and 100 pF capacitors.
Table I. Evaluation Board Configuration Options
Component
Function
Default Value
C1, C2
AC Coupling Capacitors.
1000 pF, 0603
C3
High Frequency Bypass
Capacitor.
100 pF, 0603
C4
Low Frequency Bypass
Capacitor.
0.47
F, 0603
L1
Optional RF Choke. Used
to increase current through
output stage when V
P
= 3 V.
Not recommended for use
when V
P
= 5 V.
100 nH, 0603
REV. A
12
AD8354
Figure 4. Silkscreen Top
Figure 5. Component Side
REV. A
AD8354
13
OUTLINE DIMENSIONS
8-Lead Lead Frame Chip Scale Package [LFCSP]
2mm x 3 mm Body
(CP-8)
Dimensions shown in millimeters
0.30
0.23
0.18
SEATING
PLANE
12
0
0.20 REF
0.80 MAX
0.65 NOM
1.00
0.90
0.80
0.05
0.02
0.00
1.89
1.74
1.59
0.50 BSC
0.60
0.45
0.30
0.55
0.40
0.30
0.15
0.10
0.05
0.25
0.20
0.15
BOTTOM VIEW
4
5
8
1
3.25
3.00
2.75
1.95
1.75
1.55
2.95
2.75
2.55
PIN 1
INDICATOR
2.25
2.00
1.75
NOTES
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2. PADDLE IS COPPER PLATED WITH LEAD FINISH.
REV. A
14
AD8354
Revision History
Location
Page
6/02--Data Sheet changed from REV. 0 to REV. A.
Change to ORDERING GIUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Replaced TPC 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15
C0272206/03(A)
16