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14-Bit, 80 MSPS, 3 V A/D Converter
AD9245
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 87.6 dBc to Nyquist
Low power: 366 mW
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = 0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
High end medical imaging equipment
IF sampling in communications receivers:
WCDMA, CDMA-One, CDMA-2000, TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
Power sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit, 80 MSPS
analog-to-digital converter featuring a high performance
sample-and-hold amplifier (SHA) and voltage reference. The
AD9245 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy at
80 MSPS and guarantee no missing codes over the full operat-
ing temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels, and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
FUNCTIONAL BLOCK DIAGRAM
03583-B-001
DRVDD
AVDD
AGND
0.5V
CLK
PDWN
MODE DGND
OTR
VIN+
VIN
REFT
REFB
AD9245
VREF
SENSE
SHA
A/D
MDAC1
4
16
14
3
A/D
8-STAGE
1 1/2-BIT PIPELINE
REF
SELECT
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
CORRECTION LOGIC
OUTPUT BUFFERS
D13 (MSB)
D0 (LSB)
Figure 1. Functional Block Diagram
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (40C to +85C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
2. Operating at 80 MSPS, the AD9245 consumes a low 366 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.
4. The AD9245 is pin compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulsewidths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
Rev. B
AD9245
TABLE OF CONTENTS
AD9245DC Specifications ............................................................ 3
AD9245AC Specifications............................................................. 4
AD9245Digital Specifications....................................................... 5
AD9245Switching Specifications ................................................. 6
Explanation of Test Levels........................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Definitions of Specifications ........................................................... 8
Pin Configuration and Functional Descriptions.......................... 9
Equivalent Circuits ......................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
Analog Input and Reference Overview ................................... 14
Clock Input Considerations...................................................... 15
Jitter Considerations .................................................................. 16
Power Dissipation and Standby Mode .................................... 16
Digital Outputs ........................................................................... 16
Timing ......................................................................................... 17
Voltage Reference ....................................................................... 17
Internal Reference Connection ................................................ 17
External Reference Operation .................................................. 18
Operational Mode Selection ..................................................... 18
Evaluation Board ........................................................................ 18
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
Revision B
10/03--Data Sheet Changed from REV. A to REV. B
Changes to Figure 33 ..................................................................... 17
5/03--Data Sheet Changed from REV. 0 to REV. A
Changes to Figure 30 .................................................................... 15
Changes to Figure 37 ..................................................................... 19
Changes to Figure 38..................................................................... 20
Changes to Figure 39...................................................................... 21
Changes to Table 10 ....................................................................... 24
Changes to the ORDERING GUIDE........................................... 25
Rev. B | Page 2 of 28
AD9245
AD9245DC SPECIFICATIONS
Table 1. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, unless
otherwise noted
AD9245BCP
Parameter
Temp
Test Level
Min Typ
Max
Unit
RESOLUTION Full
VI
14
Bits
ACCURACY
No Missing Codes
Full
VI
Guaranteed
Offset Error
1
Full
VI
0.30
1.2
%
FSR
Gain Error
25C
V
0.28
% FSR
Gain Error
1
Full
VI
0.70
4.16
%
FSR
Differential Nonlinearity (DNL)
2
Full
VI
0.5
1.0
LSB
Integral Nonlinearity (INL)
2
Full
VI
1.4
5.15
LSB
TEMPERATURE DRIFT
Offset Error
1
Full
V
10
ppm/C
Gain Error
Full
V
12
ppm/C
Gain Error
1
Full
V
17
ppm/C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
VI
3
34
mV
Load Regulation @ 1.0 mA
25C
V
2
mV
Output Voltage Error (0.5 V Mode)
25C
V
6
mV
Load Regulation @ 0.5 mA
25C
V
1
mV
INPUT REFERRED NOISE
VREF = 0.5 V
25C
V
1.86
LSB rms
VREF = 1.0 V
25C
V
1.17
LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V
Full
IV
1
V p-p
Input Span, VREF = 1.0 V
Full
IV
2
V p-p
Input Capacitance
3
Full
V
7
pF
REFERENCE INPUT RESISTANCE
Full
V
7
k
POWER SUPPLIES
Supply Voltage
AVDD Full
IV
2.7
3.0
3.6
V
DRVDD Full
IV
2.25
2.5
3.6
V
Supply Current
IAVDD
2
Full
VI
122
138
mA
IDRVDD
2
25C
V
9
mA
PSRR 25C
V
0.01
%
FSR
POWER CONSUMPTION
Low Frequency Input
4
25C
V
366
mW
Standby Power
5
25C
V
1.0
mW
1
With a 1.0 V internal reference.
2
Measured at the maximum clock rate, f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to
for the equivalent analog input structure.
Figure 4
4
Measured at AC Specification conditions without output drivers.
5
Standby power is measured with a dc input, CLK pin inactive (i.e., set to AVDD or AGND).
Rev. B | Page 3 of 28
AD9245
AD9245AC SPECIFICATIONS
Table 2. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference,
AIN = 0.5 dBFS, DCS Off, unless otherwise noted
AD9245BCP
Parameter
Temp
Test Level
Min Typ Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 2.4 MHz
Full
VI
71.1
dB
25C
V
73.3
dB
f
IN
= 40 MHz
25C
V
72.7
dB
f
IN
= 70 MHz
Full
IV
70.5
dB
25C
V
71.7
dB
f
IN
= 100 MHz
25C
V
70.2
dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
f
IN
= 2.4 MHz
Full
VI
70.7
dB
25C
V
73.2
dB
f
IN
= 40 MHz
25C
V
72.5
dB
f
IN
= 70 MHz
Full
IV
69.9
dB
25C
V
71.2
dB
f
IN
= 100 MHz
25C
V
69.6
dB
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 2.4 MHz
Full
VI
11.5
Bits
25C
V
11.9
Bits
f
IN
= 40 MHz
25C
V
11.8
Bits
f
IN
= 70 MHz
Full
IV
11.3
Bits
25C
V
11.5
Bits
f
IN
= 100 MHz
25C
V
11.3
Bits
WORST SECOND OR THIRD
f
IN
= 2.4 MHz
Full
VI
76.5
dBc
25C
V
92.8
dBc
f
IN
= 40 MHz
25C
V
87.6
dBc
f
IN
= 70 MHz
Full
IV
75.7
dBc
25C
V
81.6
dBc
f
IN
= 100 MHz
25C
V
79.0
dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 2.4 MHz
Full
VI
76.5
dBc
25C
V
92.8
dBc
f
IN
= 40 MHz
25C
V
87.6
dBc
f
IN
= 70 MHz
Full
IV
75.7
dBc
25C
V
81.6
dBc
f
IN
= 100 MHz
25C
V
79.0
dBc
Rev. B | Page 4 of 28
AD9245
AD9245DIGITAL SPECIFICATIONS
Table 3. AVDD = 3 V, DRVDD = 2.5 V, 1.0 V External Reference, unless otherwise noted
AD9245BCP
Parameter
Temp
Test Level
Min Typ Max
Unit
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Full
IV
2.0
V
Low Level Input Voltage
Full
IV
0.8
V
High Level Input Current
Full
IV
10
+10
A
Low Level Input Current
Full
IV
10
+10
A
Input
Capacitance
Full
V
2
pF
DIGITAL OUTPUT BITS (D0D13, OTR)
1
DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 A)
Full
IV
3.29
V
High Level Output Voltage (IOH = 0.5 mA)
Full
IV
3.25
V
Low Level Output Voltage (IOH = 1.6 mA)
Full
IV
0.2
V
Low Level Output Voltage (IOH = 50 A)
Full
IV
0.05
V
DRVDD = 2.5 V
High Level Output Voltage (IOH = 50 A)
Full
IV
2.49
V
High Level Output Voltage (IOH = 0.5 mA)
Full
IV
2.45
V
Low Level Output Voltage (IOH = 1.6 mA)
Full
IV
0.2
V
Low Level Output Voltage (IOH = 50 A)
Full
IV
0.05
V
1
Output voltage levels measured with 5 pF load on each output.
Rev. B | Page 5 of 28
AD9245
AD9245SWITCHING SPECIFICATIONS
Table 4. AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted
AD9245BCP
Parameter
Temp
Test Level
Min Typ Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
VI
80
MSPS
Minimum Conversion Rate
Full
V
1
MSPS
CLK Period
Full
V
12.5
ns
CLK Pulsewidth High
1
Full
V
4.6
ns
CLK Pulsewidth Low
1
Full
V
4.6
ns
DATA
OUTPUT
PARAMETERS
Output Propagation Delay (t
PD
)
2
Full V
4.2
ns
Pipeline Delay (Latency)
Full
V
7
Cycles
Aperture Delay (t
A
) Full
V
1
ns
Aperture Uncertainty (Jitter, t
J
) Full V
0.3
ps
rms
Wake-Up Time
3
Full
V
7
ms
OUT-OF-RANGE RECOVERY TIME
Full
V
2
Cycles
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3
Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB.
t
A
2.0ns MIN
t
PD
= 6.0ns MAX
03583-B-002
N9
N8
N7
N6
N5
N4
N3
N2
N1
N
ANALOG
INPUT
CLK
DATA
OUT
N1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level
Definitions
I
100% production tested.
II
100% production tested at 25C and guaranteed by design and characterization at specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI
100% production tested at 25C and guaranteed by design and characterization for industrial temperature range.
Rev. B | Page 6 of 28
AD9245
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9245 Absolute Maximum Ratings
Parameter
With Respect to
Min
Max
Unit
ELECTRICAL
AVDD AGND
0.3
+3.9
V
DRVDD DGND
0.3
+3.9
V
AGND DGND
0.3
+0.3
V
AVDD DRVDD
3.9
+3.9
V
D0D13
DGND
0.3
DRVDD + 0.3
V
CLK, MODE
AGND
0.3
AVDD + 0.3
V
VIN+, VIN
AGND
0.3
AVDD + 0.3
V
VREF
AGND
0.3
AVDD + 0.3
V
SENSE
AGND
0.3
AVDD + 0.3
V
REFT, REFB
AGND
0.3
AVDD + 0.3
V
PDWN
AGND
0.3
AVDD + 0.3
V
ENVIRONMENTAL
Storage Temperature
65
+125
C
Operating Temperature Range
40
+85
C
Lead Temperature Range
(Soldering 10 sec)
300
C
Junction Temperature
150
C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
JA
is specified for the worst-case conditions on a 4-layer board
in still air, in accordance with EIA/JESD51-1.
Table 6. Thermal Resistance
Package Type
JA
JC
Unit
CP-32 32.5
32.71
C/W
Airflow increases heat dissipation, effectively reducing
JA
.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the
JA
. It is recommended that the exposed paddle be
soldered to the ground plane for the LFCSP package. There is an
increased reliability of the solder joints, and maximum thermal
capability of the package is achieved with the exposed paddle
soldered to the customer board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 28
AD9245
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
--The analog
input frequency at which the spectral power of the fundamental
frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay (t
A
)
--The delay between the 50% point of the
rising edge of the clock and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter, t
J
)
--The sample-to-sample varia-
tion in aperture delay.
Integral Nonlinearity (INL
)--The deviation of each individual
code from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs LSB
before the first code transition. Positive full scale is defined as a
level 1 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Differential Nonlinearity (DNL, No Missing Codes)
--An
ideal ADC exhibits code transitions that are exactly 1 LSB apart.
DNL is the deviation from this ideal value. Guaranteed no miss-
ing codes to 14-bit resolution indicates that all 16384 codes
must be present over all operating ranges.
Offset Error
--The major carry transition should occur for an
analog value LSB below VIN+ = VIN. Offset error is
defined as the deviation of the actual transition from that point.
Gain Error
--The first code transition should occur at an
analog value LSB above negative full scale. The last transition
should occur at an analog value 1 LSB below the positive
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
Temperature Drift
--The temperature drift for offset error and
gain error specifies the maximum change from the initial
(25C) value to the value at T
MIN
or T
MAX
.
Power Supply Rejection Ratio
--The change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Total Harmonic Distortion (THD)
1
--
The ratio of the rms
input signal amplitude to the rms value of the sum of the first
six harmonic components.
Signal-to-Noise and Distortion (SINAD)
1
--
The ratio of the
rms input signal amplitude to the rms value of the sum of all
other spectral components below the Nyquist frequency, includ-
ing harmonics but excluding dc.
Effective Number of Bits (ENOB)--
The effective number of
bits for a sine wave input at a given input frequency can be cal-
culated directly from its measured SINAD using the following
formula:
(
)
02
.
6
76
.
1
-
= SINAD
ENOB
Signal-to-Noise Ratio (SNR)
1
--
The ratio of the rms input
signal amplitude to the rms value of the sum of all other spec-
tral components below the Nyquist frequency, excluding the
first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
1
--
The difference in dB
between the rms input signal amplitude and the peak spurious
signal. The peak spurious component may or may not be a
harmonic.
Two-Tone SFDR
1
--
The ratio of the rms value of either input
tone to the rms value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
Clock Pulsewidth and Duty Cycle
--Pulsewidth high is the
minimum amount of time that the clock pulse should be left in
the Logic 1 state to achieve rated performance. Pulsewidth low
is the minimum time the clock pulse should be left in the
Logic 0 state. At a given clock rate, these specifications define an
acceptable clock duty cycle.
Minimum Conversion Rate
--The clock rate at which the SNR
of the lowest analog signal frequency drops by no more than
3 dB below the guaranteed limit.
Maximum Conversion Rate
--The clock rate at which para-
metric testing is performed.
Output Propagation Delay (t
PD
)--
The delay between the clock
rising edge and the time when all bits are within valid logic
levels.
Out-of-Range Recovery Time
--The time it takes for the ADC
to reacquire the analog input after a transition from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. B | Page 8 of 28
AD9245
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
03583-B-022
DNC 1
CLK 2
DNC 3
PDWN 4
(LSB) D0 5
D1 6
D2 7
D3 8
24 VREF
23 SENSE
22 MODE
21 OTR
20 D13 (MSB)
19 D12
18 D11
17 D10
32 A
V
D
D
31 A
G
N
D
30 VIN
29 VIN
+
28 A
G
N
D
27 A
V
D
D
26 R
E
FT
25 R
E
FB
D4
9
D5
1
0
D6
1
1
D7
1
2
D8
1
3
D9
1
4
DGND 1
5
DRV
DD 1
6
AD9245
CSP
TOP VIEW
(Not to Scale)
Figure 3. 32-Lead LFCSP
Table 7. Pin Function Descriptions--32-Lead LFCSP (CP Package)
Pin No.
Mnemonic
Description
1, 3
DNC
Do Not Connect
2
CLK
Clock Input Pin
4
PDWN
Power-Down Function Select
5 to 14, 17 to 20
D0 (LSB) to D13 (MSB)
Data Output Bits
15 DGND
Digital
Output
Ground
16
DRVDD
Digital Output Driver Supply
21 OTR
Out-of-Range
Indicator
22
MODE
Data Format Select and DCS Mode Selection (see
)
23
SENSE
Reference Mode Selection (see Table 8)
24
VREF
Voltage Reference Input/Output
25
REFB
Differential Reference ()
26
REFT
Differential Reference (+)
27, 32
AVDD
Analog Power Supply
28, 31
AGND
Analog Ground
29
VIN+
Analog Input Pin (+)
30
VIN
Analog Input Pin ()
Table 9
Rev. B | Page 9 of 28
AD9245
EQUIVALENT CIRCUITS
AVDD
VIN+, VIN
03583-B-003
Figure 4. Equivalent Analog Input Circuit
03583-B-004
AVDD
MODE
20k
Figure 5. Equivalent MODE Input Circuit
D13-D0,
OTR
DRVDD
03583-B-005
Figure 6. Equivalent Digital Output Circuit
03583-B-006
AVDD
CLK,
PDWN
Figure 7. Equivalent Digital Input Circuit
Rev. B | Page 10 of 28
AD9245
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, DCS Disabled, T
A
= 25C, 2 V p-p Differential Input, AIN = 0.5 dBFS,
VREF = 1.0 V External, unless otherwise noted
FREQUENCY (MHz)
AMP
L
ITUDE
(dBFS
)
0
5
10
15
20
25
30
35
120
0
10
20
30
40
50
60
70
80
90
100
110
40
03583-B-032
AIN = 0.5dBFS
SNR = 73.2dBc
ENOB = 11.8 BITS
SFDR = 92.8 dBc
Figure 8. Single Tone 8K FFT @ 2.5 MHz
FREQUENCY (MHz)
AMP
L
ITUDE
(dBFS
)
0
5
10
15
20
25
30
35
120
0
10
20
30
40
50
60
70
80
90
100
110
40
03583-B-023
AIN = 0.5dBFS
SNR = 72.7dBc
ENOB = 11.8 BITS
SFDR = 87.6 dBc
Figure 9. Single Tone 8K FFT @ 39 MHz
FREQUENCY (MHz)
AMP
L
ITUDE
(dBFS
)
0
5
10
15
20
25
30
35
120
0
10
20
30
40
50
60
70
80
90
100
110
40
03583-B-024
AIN = 0.5dBFS
SNR = 71.7dBc
ENOB = 11.5 BITS
SFDR = 81.6 dBc
Figure 10. Single Tone 8K FFT @ 70 MHz
INPUT AMPLITUDE (dBFS)
S
NR/S
F
DR (dBc
AND dBFS
)
30
25
20
15
10
5
40
50
60
70
80
90
100
0
03583-B-033
SFDR (dBFS)
SNR (dBc)
SFDR = 90dBc
REFERENCE LINE
SFDR (dBc)
SNR (dBFS)
Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz
INPUT AMPLITUDE (dBFS)
S
NR/S
F
DR (dBc
AND dBFS
)
30
25
20
15
10
5
40
50
60
70
80
90
100
0
03583-B-034
SFDR (dBFS)
SNR (dBc)
SFDR = 90dBc
REFERENCE LINE
SFDR (dBc)
SNR (dBFS)
Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz
SAMPLE RATE (MSPS)
S
NR/S
F
DR (dBc
)
0
20
40
60
80
50
60
70
80
90
100
100
03583-B-025
SFDR (DIFF)
SFDR (SE)
SNR (DIFF)
SNR (SE)
Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz
Rev. B | Page 11 of 28
AD9245
FREQUENCY (MHz)
AMP
L
ITUDE
(dBFS
)
0
5
10
15
20
25
30
35
120
110
100
90
80
70
60
50
40
30
20
10
0
40
03583-B-029
AIN = 6.5dBFS
SNR = 73.4dBFS
SFDR = 86.0dBFS
Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz
FREQUENCY (MHz)
AMP
L
ITUDE
(dBFS
)
0
5
10
15
20
25
30
35
120
110
100
90
80
70
60
50
40
30
20
10
0
40
03583-B-030
AIN = 6.5dBFS
SNR = 72.7dBFS
SFDR = 78.8dBFS
Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz
CODE
INL (
L
SB)
0
2048
4096
6144
8192
10240 12288 14336
1.5
1.5
1.0
0.5
0
0.5
1.0
16384
03583-B-026
Figure 16. Typical INL
INPUT AMPLITUDE (dBFS)
S
NR/S
F
DR (dBc
AND dBFS
)
30
27
24
21
18
15
12
9
40
100
90
80
70
60
50
6
03583-B-031
SFDR = 90dBc
REFERENCE LINE
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dBc)
Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz
INPUT AMPLITUDE (dBFS)
S
NR/S
F
DR (dBc
AND dBFS
)
30
27
24
21
18
15
12
9
40
100
90
80
70
60
50
6
03583-B-027
SFDR = 90dBc
REFERENCE LINE
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dBc)
Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz
CODE
DNL (LS
B
)
0
2048
4096
6144
8192
10240 12288 14336
1.0
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
16384
03583-B-028
Figure 19. Typical DNL
Rev. B | Page 12 of 28
AD9245
INPUT FREQUENCY (MHz)
S
NR (dBc
)
0
25
50
75
100
65
75
40
C
+85
C
74
73
72
71
70
69
68
67
66
125
03583-B-036
+25
C
Figure 20. SNR vs. Input Frequency
DUTY CYCLE (%)
SN
R
/
SFD
R
(
d
B
c
)
30
35
40
45
50
55
60
65
70
90
88
86
84
82
80
78
76
74
72
70
03583-B-037
SNR (DCS ON)
SNR (DCS OFF)
SFDR (DCS ON)
SFDR (DCS OFF)
Figure 21. SNR/SFDR vs. Clock Duty Cycle
0
10
20
30
40
50
60
70
80
90
100
110
AMP
L
ITUDE
(dBFS
)
120
0
9.6
19.2
28.8
38.4
FREQUENCY (MHz)
03583-B-059
Figure 22. 32K FFT WCDMA Carrier @ F
IN
= 96 MHz; Sample Rate = 76.8 MSPS
INPUT FREQUENCY (MHz)
S
F
DR (dBc
)
0
25
50
75
100
70
100
95
90
85
80
75
125
40
C
+25
C
+85
C
03583-B-038
Figure 23. SFDR vs. Input Frequency
0
10
20
30
40
50
60
70
80
90
100
110
AMP
L
ITUDE
(dBFS
)
120
0
9.6
19.2
28.8
38.4
FREQUENCY (MHz)
03583-B-060
Figure 24. Two 32K FFT CDMA-2000 Carriers @
F
IN
= 46.08 MHz; Sample Rate = 61.44 MSPS
0
10
20
30
40
50
60
70
80
90
100
110
AMP
L
ITUDE
(dBFS
)
120
0
9.6
19.2
28.8
38.4
FREQUENCY (MHz)
03583-B-061
Figure 25. Two 32K FFT WCDMA Carriers @
F
IN
= 76.8 MHz; Sample Rate = 61.44 MSPS
Rev. B | Page 13 of 28
AD9245
THEORY OF OPERATION
The AD9245 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capaci-
tor ADC. The pipelined ADC is divided into three sections,
consisting of a 4-bit first stage followed by eight 1.5-bit stages
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture per-
mits the first stage to operate on a new input sample, while the
remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac-
coupled or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment
of the output voltage swing. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9245 is a differential switched-
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA input
can support a wide common-mode range (VCM) and maintain
excellent performance, as shown in Fi
. An input
common-mode voltage of midsupply minimizes signal-
dependent errors and provides optimum performance.
gure 26
Figure 26. SNR, SFDR vs. Common-Mode Level
COMMON-MODE LEVEL (V)
S
NR/S
F
DR (dBc
)
0.5
1.0
1.5
2.0
2.5
50
100
95
90
85
80
75
70
65
60
55
3.0
03583-B-039
SFDR (2.5MHz)
SFDR (39MHz)
SNR (2.5MHz)
SNR (39MHz)
Referring to F
, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC's
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with
the driving source impedance, they would limit the input
bandwidth.
igure 27
Figure 27. Switched-Capacitor SHA Input
03583-B
-012
H
H
VIN+
VIN
C
PAR
C
PAR
T
T
5pF
5pF
T
T
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as follows:
(
)
(
)
(
)
VREF
REFB
REFT
Span
VREF
AVDD
REFB
VREF
AVDD
REFT
=
-
=
-
=
+
=
2
2
2
1
2
1
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage, and,
by definition, the input span is twice the value of the VREF voltage.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the
section.
Maximum SNR performance is achieved with the AD9245 set
Internal Reference Connection
Rev. B | Page 14 of 28
AD9245
03583-B-014
AD9245
VIN+
VIN
AVDD
AGND
33
33
10pF
49.9
1k
1k
0.1
F
2V p-p
to the largest input span of 2 V p-p. The relative SNR degradation
is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference volt-
age. The minimum and maximum common-mode input levels
are defined as
2
VREF
VCM
MIN
=
(
)
2
VREF
AVDD
VCM
MAX
+
=
The minimum common-mode input level allows the AD9245 to
accommodate ground referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be applied to VIN+ or VIN.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN. The
AD9245 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies.
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9245 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
AD9245
VIN+
VIN
AGND
AVDD
1V p-p
49.9
523
1k
1k
0.1
F
33
33
20pF
499
499
499
AD8138
03583-B
-013
Figure 28. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9245. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The value of the shunt capacitor is dependent on
the input frequency and source impedance and should be
reduced or removed. An example is shown in F
.
igure 29
Figure 29. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing (see F
). However, if
the source impedances on each input are matched, there should
be little effect on SNR performance. F
details a typical
single-ended input configuration.
igure 13
igure 30
Figure 30. Single-Ended Input Configuration
03583-B-015
AD9245
VIN+
VIN
AVDD
AGND
2V p-p
33
33
20pF
49.9
1k
1k
0.33
F
10
F
0.1
F
1k
1k
+
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive
to clock duty cycle. Commonly a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteris-
tics. The AD9245 contains a clock duty cycle stabilizer (DCS) that
retimes the nonsampling edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows a wide range of clock
input duty cycles without affecting the performance of the
AD9245. As shown in Figure 21, noise and distortion perform-
ance is nearly flat for a 30% to 70% duty cycle with the DCS on.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
Rev. B | Page 15 of 28
AD9245
JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input fre-
quency (f
INPUT
) due only to aperture jitter (t
J
) can be calculated
with the following equation:
[
]
J
INPUT
t
f
2
SNR
=
log
20
In the equation, the rms aperture jitter represents the root-mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF undersam-
pling applications are particularly sensitive to jitter (see Figure 31).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9245. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
INPUT FREQUENCY (MHz)
S
NR (dBc
)
1
40
75
70
65
60
55
50
45
1000
100
10
03583-B-041
0.2ps
MEASURED SNR
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
Figure 31. SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND STANDBY MODE
As shown in
, the power dissipated by the AD9245 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(I
DRVDD
) can be calculated as
Figure 32
Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz
Figure 32
N
f
C
V
I
CLK
LOAD
DRVDD
DRVDD
=
where N is the number of output bits, 14 in the case of the
AD9245. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, f
CLK
/2. In practice, the DRVDD current will
be established by the average number of output bits switching,
which will be determined by the sample rate and the character-
istics of the analog input signal.
SAMPLE RATE (MSPS)
TOTAL POWER (mW)
CURRE
NT (mA)
10
20
30
40
50
60
70
80
90
300
325
350
375
400
425
0
20
40
60
80
100
120
140
100
03583-B-035
ANALOG CURRENT
TOTAL POWER
DIGITAL CURRENT
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in
was
taken with the same operating conditions as the Typical Per-
formance Characteristics, and with a 5 pF load on each output
driver.
By asserting the PDWN pin high, the AD9245 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During standby,
the output drivers are placed in a high impedance state.
Reasserting the PDWN pin low returns the AD9245 to its
normal operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 F and 10 F decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
DIGITAL OUTPUTS
The AD9245 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to pro-
vide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads or
large fanouts may require external buffers or latches.
As detailed in
, the data format can be selected for either
offset binary or twos complement.
Table 9
Rev. B | Page 16 of 28
AD9245
TIMING
The AD9245 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (t
PD
) after the rising edge of the clock signal. Refer to
for a detailed timing diagram.
Figure 2
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9245. These transients can degrade the converter's dynamic
performance.
The lowest typical conversion rate of the AD9245 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9245. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9245 using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are summarized
and described
in the following sections.
Table 8
Table 8
Table 8. Reference Configuration Summary
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap (com-
mon-mode voltage).
INTERNAL REFERENCE CONNECTION
A comparator within the AD9245 detects the potential at the
SENSE pin and configures the reference into one of four
possible states, which are summarized in
. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see
), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in
, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as follows:
Figure 33
Figure 33. Internal Reference Configuration
Figure 35
+
=
R1
R2
VREF
1
5
.
0
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
03583-B-017
10
F
+
0.1
F
VREF
SENSE
0.5V
AD9245
VIN
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
+
If the internal reference of the AD9245 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 34
depicts how the internal reference voltage is affected by loading.
LOAD (mA)
E
RROR (%)
0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
03583-B-019
0
0.25
0.20
0.15
0.10
0.05
0.5V ERROR (%)
1.0V ERROR (%)
Figure 34. VREF Accuracy vs. Load
Selected Mode
SENSE Voltage
Internal Switch
Position
Resulting VREF (V)
Resulting Differential
Span (V p-p)
External Reference
AVDD
N/A
N/A
2 External Reference
Internal Fixed Reference
VREF
SENSE
0.5
1.0
Programmable Reference
0.2 V to VREF
SENSE
+
R1
R2
1
5
.
0
(See Figure 35)
2 VREF
Internal Fixed Reference
AGND to 0.2 V
Internal Divider
1.0
2.0
Rev. B | Page 17 of 28
AD9245
03583-B-018
10
F
+
0.1
F
VREF
SENSE
R2
R1
0.5V
AD9245
VIN
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 35. Programmable Reference Configuration
EXTERNAL REFERENCE OPERATION
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. F
shows the typi-
cal drift characteristics of the internal reference in both 1.0 V
and 0.5 V modes.
igure 36
Figure 36. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 k load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.
TEMPERATURE (C)
VR
EF ER
R
O
R
(
%
)
40
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
80
70
60
50
40
30
20
10
0
10
20
30
03583-B-040
VREF = 0.5V
VREF = 1.0V
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9245 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined in
.
Table 9
Table 9. Mode Selection
MODE Voltage
Data Format
Duty Cycle
Stabilizer
AVDD Twos
Complement
Disabled
2/3 AVDD
Twos Complement
Enabled
1/3 AVDD
Offset Binary
Enabled
AGND (Default)
Offset Binary
Disabled
EVALUATION BOARD
The AD9245 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.
It is critical that signal sources with very low phase noise (<1 ps
rms jitter) be used to realize the ultimate performance of the
converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
The AD9245 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input configu-
ration can be selected by proper connection of various jumpers
(refer to the schematics).
An alternative differential analog input path using an AD8351
op amp is included in the layout, but is not populated in pro-
duction. Designers interested in evaluating the op amp with the
ADC should remove C15, R12, and R3, and populate the op
amp circuit. The passive network between the AD8351 outputs
and the AD9245 allows the user to optimize the frequency
response of the op amp for the application.
Rev. B | Page 18 of 28
AD9245
03583-B-050
123
45
6
P1
3
P1
4
X
F
RI
N1
OPTI
ONAL XFR
T2
FT C1
113
NC
CT
1
T 1
ADT1
1WT
6
2
34
5
1
2
3
4
5
R S
I
NGLE
E
NDE
D
R18
25
R3,
R17,
R18
ONL
Y
ONE SHOULD BE
ON BO
ARD A
T
A
T
I
M
E
EXTR
EF
1
V
MA
X E1
R1
10k
R9
10k
0.
1
F
C12
C9
0.
10
F
GND
G
ND
GND
GND
GND
AV
DD
C29
10
F
0.
1
F
C11
C7
0.
1
F
GND
GND
AV
DD
P7
A
B
C
D
P9
P8
P1
1
P1
0
E
C13
0.
10
F
C22
10
F
P6
P1
P3
P4
1
2
3
4
GND
GND
C8
0.
1
F
P5
2
MOD
E
25
26
27
28
29
30
31
32
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
RE
FB
R
E
F
T
A
V
D
D
A
G
N
D
V
I
N
+
A
G
N
D
A
V
D
D
V
I
N
AD9245
U4
VREF
SENSE
MODE
D13
OTR
D12
D11
D10
D
V
D
D
D
G
N
D
D
9
D
7
D
8
D
6
D
5
D
4
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
DNC
CLK
DNC
D0
PDW
N
D1
D2
D3
(
L
S
B
)
D
R
V
D
D
G
N
D
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
D
R
X
D
1
3
X
D
1
2
X
D
1
0
X
D
1
1
X
D
9
X
D
8
X
D
7
X
D
6
X
D
5
X
D
4
X
D
2
X
D
3
X
D
1
X
D
0
X
(
M
S
B
)
O
V
E
R
R
A
N
G
E
B
I
T
AVD
D
GND
DRV
DD
VDL
VAMP
GND
P2
G
N
D
H
1
M
T
H
O
L
E
6
H
2
M
T
H
O
L
E
6
H
3
M
T
H
O
L
E
6
H
4
M
T
H
O
L
E
6
3.0V
2.5V
2.5V
5.0V
R
P
2
2
2
0
R
P
1
2
2
0
S
E
N
S
E
P
I
N
S
O
L
D
E
R
A
B
L
E
J
U
M
P
E
R
:
E
T
O
A
:
E
X
T
E
R
N
A
L
V
O
L
T
A
G
E
D
I
V
I
D
E
R
E
T
O
B
:
I
N
T
E
R
N
A
L
1
V
R
E
F
E
R
E
N
C
E
(
D
E
F
A
U
L
T
)
E
T
O
C
:
E
X
T
E
R
N
A
L
R
E
F
E
R
E
N
C
E
E
T
O
D
:
I
N
T
E
R
N
A
L
0
.
5
V
R
E
F
E
R
E
N
C
E
M
O
D
E
P
I
N
S
O
L
D
E
R
A
B
L
E
J
U
M
P
E
R
:
5
T
O
1
:
T
W
O
S
C
O
M
P
L
E
M
E
N
T
/
D
C
S
O
F
F
5
T
O
2
:
T
W
O
S
C
O
M
P
L
E
M
E
N
T
/
D
C
S
O
N
5
T
O
3
:
O
F
F
S
E
T
B
I
N
A
R
Y
/
D
C
S
O
N
5
T
O
4
:
O
F
F
S
E
T
B
I
N
A
R
Y
/
D
C
S
O
F
F
G
N
D
R
8
1
k
C
L
K
A
V
D
D
G
N
D
R
2
5
1
k
R
1
3
1
k
A
V
D
D
R
1
5
3
3
G
N
D
G
N
D
C
2
3
1
0
p
F
G
N
D
C
1
9
O
R
L
1
F
O
R
F
I
L
T
E
R
G
N
D
A
V
D
D
R
4
3
3
R
3
6
1
k
R
2
6
1
k
G
N
D
A
V
D
D
A
V
D
D
G
N
D
G
N
D
V
I
N
+
V
I
N
1
5
p
F
C
2
1
1
0
p
F
R
2
X
X
R
1
0
3
6
R
1
2
0
A
M
P
I
N
X
OU
T
G
N
D
X
OU
T
B
R
3
0
R
1
1
3
6
C
5
0
.
1
F
C
2
6
1
0
p
F
E
4
5
C
1
6
0
.
1
F
R
4
2
0
C
6
0
.
1
F
G
N
D
G
N
D
A
M
P
A
M
P
I
N
B
C
1
5
0
.
1
F
L
1
1
0
n
H
G
N
D
P
R
I
S
E
C
P
R
I
S
E
C
G
N
D
C
1
8
0
.
1
0
F
X
F
R
I
N
X
OU
T
B
C
T
X
OU
T
J
1
R
5
1
k
R
7
1
k
R
6
1
k
Figure 37. LFCSP Evaluation Board Schematic--Analog Inputs and DUT
Rev. B | Page 19 of 28
AD9245
03583-B
-
051
DRX
D
13X
GND
D2
X
D1
X
GND
D0
X
D
11X
D
12X
DR
V
D
D
D
10X
D9
X
GND
D8
X
D7
X
D5
X
D6
X
GND
D4
X
D3
X
DRV
DD
2C
LK
2D
B
2D
7
GND
2D
6
2D
5
1D
2
1D
1
1C
LK
2D
4
V
CC
V
CC
2D
3
GND
2D
2
2D
1
1D
7
1D
6
1D
5
1D
8
GND
1D
4
1D
3
GND
2OE
2QB
2Q7
2Q6
2Q5
1Q2
1Q1
1OE
2Q4
2Q3
GND
GND
2Q2
2Q1
1Q8
1Q7
1Q6
1Q5
G
N
D
V
CC
V
CC
1
Q
4
1
Q
3
G
N
D
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
I
N
O
U
T
C
L
K
A
T
/
D
A
C
1
U
1
7
4
L
V
T
H
1
6
2
3
7
4
C
L
K
L
A
T
/
D
A
C
G
N
D
G
N
D
D
R
V
D
D
G
N
D
G
N
D
D
R
V
D
D
G
N
D
G
N
D
D
R
Y
M
S
B
L
S
B
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
3
8
4
0
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
3
8
4
0
1
3
5
7
9
1
1
1
3
1
5
1
7
1
9
2
1
2
3
2
5
2
7
2
9
3
1
3
3
3
5
3
7
3
9
1
3
5
7
9
1
1
1
3
1
5
1
7
1
9
2
1
2
3
2
5
2
7
2
9
3
1
3
3
3
5
3
7
3
9
G
N
D
D
R
G
N
D
M
S
B
D
R
Y
G
N
D
A
M
P
I
N
A
M
P
I
N
B
G
N
D
V
A
M
P
G
N
D
G
N
D
G
N
D
G
N
D
V
A
M
P
G
N
D
V
A
M
P
G
N
D
G
N
D
H
E
A
D
E
R
4
0
C
2
7
0
.
1
F
C
4
5
0
.
1
F
C
2
8
0
.
1
F
C
3
5
0
.
1
0
F
C
2
4
1
0
F
C
1
7
0
.
1
F
R
1
6
0
R
3
9
1
k
R
1
4
2
5
R
4
0
1
0
k
P
W
D
N
1
R
G
P
1
2
I
N
H
I
3
I
N
L
O
4
R
P
G
2
5
R
4
1
1
0
k
R
3
5
2
5
R
3
3
2
5
R
3
4
1
.
2
k
R
1
9
5
0
A
M
P
I
N
A
M
P
R
1
7
0
R
3
8
1
k
U3
AD8351
P
O
W
E
R
D
O
W
N
U
S
E
R
4
0
O
R
R
4
1
C
4
4
0
.
1
F
G
N
D
G
N
D
C
O
M
M
6
7
8
9
1
0
O
P
L
O
O
P
H
I
V
P
O
S
V
O
C
M
Figure 38. LFCSP Evaluation Board Schematic--Digital Path
Rev. B | Page 20 of 28
AD9245
03583-B-052
C10
22
F
C4
10
F
C3
10
F
C25
10
F
C32
0.
001
F
C33
0.
1
F
C14
0.
001
F
VD
L
D
R
VD
D
A
VD
D
GND
GND
AV
D
D
DUT BY
P
A
S
S
I
N
G
CLOCK TI
M
I
NG
ADJUS
TM
E
N
TS
FOR A B
U
FFE
RE
D E
NCODE
US
E
R28
FOR A DI
RE
CT E
NCODE
US
E
R27
ANALOG BY
P
A
S
S
I
N
G
D
I
G
I
T
AL BY
P
A
S
S
I
NG
LA
TCH BY
P
A
S
S
I
N
G
GND
DR
V
D
D
C41
0.
1
F
C2
22
F
C30
0.
001
F
C31
0.
1
F
C46
10
F
C34
0.
1
F
C36
0.
1
F
C38
0.
001
F
C1
0.
1
F
C47
0.
1
F
C48
0.
001
F
C49
0.
001
F
C20
10
F
C37
0.
1
F
C40
0.
001
F
GND
GND
VA
MP
VD
L
C39
0.
001
F
E
NCX
CLK
EN
C
E
NCODE
R27
0
R32
1k
R23
0
R37
25
R22 0
R28
0
E5
0
E5
1
EN
C
VD
L
VD
L
VD
L
E5
2
E
5
3
E3
1
E
3
5
E4
3
E
4
4
GND
GND
GN
D
PWR
GND
CLKLAT/
DAC
VD
L
GND
VD
L
GND
C43
0.
1
F
R31
1k
R20
1k
R21
1k
R24
1k
R30
1k
R29
50
GND
J2
GND
VD
L
GND
1
1Y
U5
4Y
2Y
3Y
2
4
5
9
10
3
6
7
8
11
14
12
13
74V
CX
86
E
NCX
1
B
1
A
2
B
2
A
3
B
3
A
4
B
4
A
DR
S
CHE
M
A
TI
C S
H
OWS
TWO
GATE DELAY SETUP.
FOR ONE
DE
LAY
,
RE
M
O
V
E
R22 AND R37 AND
ATTACH Rx (Rx = 0
).
Rx DNP
LA
TCH BY
P
A
S
S
I
N
G
Figure 39. LFCSP Evaluation Board Schematic--Clock Input
Rev. B | Page 21 of 28
AD9245
03583-B-053
Figure 40. LFCSP Evaluation Board Layout, Primary Side
03583-B-054
Figure 41. LFCSP Evaluation Board Layout, Secondary Side
03583-B-055
Figure 42. LFCSP Evaluation Board Layout, Ground Plane
03583-B-056
Figure 43. LFCSP Evaluation Board Layout, Power Plane
Rev. B | Page 22 of 28
AD9245
03583-B-057
Figure 44. LFCSP Evaluation Board Layout, Primary Silkscreen
03583-B-058
Figure 45. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. B | Page 23 of 28
AD9245
Table 10. LFCSP Evaluation Board Bill of Materials
Item
Qty. Omit
1
Reference Designator
Device
Package Value
Recommended
Vendor/Part Number
Supplied
by ADI
18
C1, C5, C7, C8, C9, C11, C12,
C13, C15, C16, C31, C33, C34,
C36, C37, C41, C43, C47
1
8
C6, C18, C27, C17,
C28, C35, C45, C44
Chip Capacitor
0603
0.1 F
8
C2, C3, C4, C10, C20, C22,
C25, C29
2
2 C46,
C24
Tantalum Capacitor
TAJD
10 F
3 8
C14, C30, C32, C38,
C39, C40, C48, C49
Chip Capacitor
0603
0.001 F
4
3
C19, C21, C23
Chip Capacitor
0603
10 pF
5
1
C26
Chip Capacitor
0603
10 pF
9
E31, E35, E43, E44, E50, E51,
E52, E53
6
2 E1,
E45
Header
EHOLE
Jumper Blocks
7
2
J1, J2
SMA Connector/50
SMA
8 1 L1
Inductor
0603 10
nH
Coilcraft/0603CS-
10NXGBU
9
1
P2
Terminal Block
TB6
Wieland/25.602.2653.0,
z5-530-0625-0
10
1
P12
Header Dual 20-Pin RT Angle HEADER40
Digi-Key S2131-20-ND
5
R3, R12, R23, R28, Rx
11
6
R16, R17, R22, R27, R42, R37
Chip Resistor
0603
0
12
2
R4, R15
Chip Resistor
0603
33
13 14
R5, R6, R7, R8, R13, R20, R21,
R24, R25, R26, R30, R31, R32,
R36
Chip Resistor
0603
1 k
14
2
R10, R11
Chip Resistor
0603
36
1
R29
15
1 R19
Chip Resistor
0603
50
16
2
RP1, RP2
Resistor Pack
R_742
220
Digi-Key
CTS/742C163220JTR
17
1
T1
ADT1-1WT
AWT1-1T
Mini-Circuits
18
1
U1
74LVTH162374 CMOS Register TSSOP-48
19
1
U4
AD9245BCP ADC (DUT)
CSP-32
Analog Devices, Inc.
X
20
1
U5
74VCX86M
SOIC-14
Fairchild
21
1
PCB
AD92XXBCP/PCB
PCB
Analog Devices, Inc.
X
22
1
U3
AD8351 Op Amp
MSOP-8
Analog Devices, Inc.
X
23
1
T2
MACOM Transformer
ETC1-1-13 1-1 TX
MACOM/ETC1-1-13
24
5
R1, R2, R9, R38, R39
Chip Resistor
0603
SELECT
25
3
R14, R18, R35
Chip Resistor
0603
25
26
2
R40, R41
Chip Resistor
0603
10 k
27
1
R34
Chip Resistor
1.2 k
28
1
R33
Chip Resistor
100
Total 82
34
1
These items are included in the PCB design, but are omitted at assembly.
Rev. B | Page 24 of 28
AD9245
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12 MAX
1.00
0.85
0.80
SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
BOTTOM
VIEW
0.50
0.40
0.30
3.50 REF
0.50
BSC
3.25
3.10 SQ
2.95
0.60 MAX
0.60 MAX
0.25 MIN
TOP
VIEW
PIN 1
INDICATOR
PIN 1
INDICATOR
5.00
BSC SQ
4.75
BSC SQ
Figure 46. 32-Lead Frame Chip Scale Package [LFCSP]
(CP-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
AD9245 Products
Temperature Range
Package Description
Package Outline
AD9245BCP-80
1
40C to +85C
Lead Frame Chip Scale Package (LFCSP)
CP-32-1
AD9245BCPRL780
1
40C to +85C
Lead Frame Chip Scale Package (LFCSP)
CP-32-1
AD9245BCPZ-80
1,
2
40C to +85C
Lead Frame Chip Scale Package (LFCSP)
CP-32-1
AD9245BCPZRL7-80
1,
2
40C to +85C
Lead Frame Chip Scale Package (LFCSP)
CP-32-1
AD9245BCP-80EB
1
Evaluation
Board
1
It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maxi-
mum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.
2
Z = Lead Free.
Rev. B | Page 25 of 28
AD9245
NOTES
Rev. B | Page 26 of 28
AD9245
NOTES
Rev. B | Page 27 of 28
AD9245
NOTES
2003 Analog Devices, Inc. All rights reserved. Trademarks and
regis-
tered trademarks are the property of their respective owners.
C03583-0-10/03(B)
Rev. B | Page 28 of 28
Document Outline
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