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16-Bit, 200 MSPS/500 MSPS TxDAC+

with

2×/4×/8× Interpolation and Signal Processing

AD9786

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

16-bit resolution, 200 MSPS input data rate
IMD 90 dBc @10 MHz
Noise spectral density (NSD) -164 dBm/Hz @ 10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.3 LSB
INL = ±0.6 LSB
Selectable 2×/4×/8× interpolation filters
Selectable f

DAC

/2, f

DAC

/4, f

DAC

/8 modulation modes

Single or dual channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
3.3 V compatible digital interface
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package

APPLICATIONS

Base stations: Multicarrier WCDMA, GSM/EDGE, TD-SCDMA,
IS136, TETRA
Instrumentation: RF Signal Generators, Arbitrary Waveform
Generators
HDTV Transmitters
Broadband Wireless Systems
Digital Radio Links
Satellite Systems

PRODUCT DESCRIPTION

The AD9786 is a 16-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for com-
munications applications. It offers state-of-the-art distortion
and noise performance. The AD9786 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.

The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or
differential mode. Internal dividers generate the required data
rate interface clocks.

The AD9786 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9786 is
manufactured on an advanced low cost 0.25 µm CMOS process.

FUNCTIONAL BLOCK DIAGRAM

16-BIT DAC

NCE

CIRCUITS

CALIBRATION

SPI

ZERO

STUFF

HILBERT

()/

I
m

()

2×

LATCH

DATA

SSEM

DATA P

NCHRONIZE

DAC

×1

CLOCK DISTRIBUTION AND CONTROL

CLK+
CLK

DATACLK

P2B[15:0]

P1B[15:0]

FSADJ

REFIO

OUTA

OUTB

SDIO
SDO
CSB
SCLK
RESET

03152-0-001

2×

LATCH

Figure 1.

AD9786

Rev. 0 | Page 2 of 60

TABLE OF CONTENTS

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Dynamic Specifications ............................................................... 5

Digital Specifications ................................................................... 6

Absolute Maximum Ratings ....................................................... 6

Thermal Characteristics .............................................................. 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Clock .............................................................................................. 8

Analog............................................................................................ 9

Data ................................................................................................ 9

Serial Interface ............................................................................ 10

Definition of Specifications........................................................... 11

Typical Performance Characteristics ........................................... 13

Serial Control Interface.................................................................. 19

General Operation of the Serial Interface ............................... 19

Serial Interface Port Pin Descriptions ..................................... 19

MSB/LSB Transfers..................................................................... 20

Notes on Serial Port Operation ................................................ 20

Mode Control (via SERIAL Port)................................................. 21

Digital Filter Specifications ........................................................... 25

Digital Interpolation Filter Coefficients.................................. 25

AD9786 Clock/Data Timing..................................................... 26

Real and Complex Signals......................................................... 33

Modulation Modes..................................................................... 34

Power Dissipation ...................................................................... 39

Hilbert Transform Implementation......................................... 41

Operating the AD9786 Rev F Evaluation Board ........................ 45

Power Supplies............................................................................ 45

PECL Clock Driver .................................................................... 45

Data Inputs.................................................................................. 46

Serial Port .................................................................................... 46

Analog Output ............................................................................ 47

Outline Dimensions ....................................................................... 60

Ordering Guide .......................................................................... 61

REVISION HISTORY

7/04--Revision 0: Initial Version

AD9786

Rev. 0 | Page 3 of 60

PRODUCT HIGHLIGHTS

The AD9786 is a 16-bit high speed interpolating
TxDAC+.

2×/4×/8× user selectable interpolating filter eases data
rate and output signal reconstruction filter requirements.

200 MSPS input data rate.

Ultra high speed 500 MSPS DAC conversion rate.

Flexible clock with single-ended or differential input:
CMOS, 1 V p-p sine wave, and LVPECL capability.

Complete CMOS DAC function operates from a 3.1 V to
3.5 V single analog (AVDD) supply, 2.5 V (DVDD)

digital supply, and a 2.5 to 3.3V DRVDD supply. The
DAC full-scale current can be reduced for lower power
operation, and a sleep mode is provided for low power
idle periods.

On-chip voltage reference: The AD9786 includes a
1.20 V temperature-compensated band gap voltage
reference.

8. Multichip synchronization: Multiple AD9786 DACs can

be synchronized to a single master AD9786 to ease
timing design requirements and optimize image reject
transmit performance.

AD9786

Rev. 0 | Page 4 of 60

SPECIFICATIONS

DC SPECIFICATIONS

MIN

to T

MAX

, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, I

OUTFS

= 20 mA, unless otherwise noted.

Table 1.

Parameter Min

Typ

Max

Unit

RESOLUTION

Bits

DC Accuracy

Integral Nonlinearity

±0.6

LSB

Differential Nonlinearity

±0.3

LSB

ANALOG OUTPUT

Offset Error

±0.015

±0.0175

% of FSR

Gain Error (with Internal Reference)

±1.5

% of FSR

Full-Scale Output Current

Output Compliance Range

1.0

+1.0

Output Resistance

REFERENCE OUTPUT

Reference Voltage

1.15

1.23

1.30

Reference Output Current

µA

REFERENCE INPUT

Input Compliance Range

0.1

1.25

Reference Input Resistance (Ext Reference Mode)

Small Signal Bandwith

200

kHz

TEMPERATURE COEFFICIENTS

Unipolar Offset Drift

ppm of FSR/°C

Gain Drift (with Internal Reference)

±4

ppm of FSR/°C

Reference Voltage Drift

±30

ppm/°C

POWER SUPPLY

AVDD1, AVDD2

Voltage Range

3.1

3.3

3.5

Analog Supply Current (I

AVDD1

+ I

AVDD2

)

AVDD1

+ I

AVDD2

in SLEEP Mode

ACVDD, ADVDD

Voltage Range

2.35

2.5

2.65

Analog Supply Current (I

ACVDD

+ I

ADVDD

)

2.5

CLKVDD

Voltage Range

2.35

2.5

2.65

Clock Supply Current (I

CLKVDD

)

DVDD

Voltage Range

2.35

2.5

2.65

Digital Supply Current (I

DVDD

)

52.5

DRVDD

Voltage Range

2.35

2.5/3.3

3.5

Digital Supply Current (I

DRVDD

)

5.3

µA

Nominal Power Dissipation

1.25

OPERATING RANGE

+85

°C

Measured at IOUTA driving a virtual ground.

Nominal full-scale current, I

OUTFS

, is 32× the I

REF

current.

Use an external amplifier to drive any external load.

Measured under the following conditions: f

DATA

= 125 MSPS, f

DAC

= 500 MSPS, 4× interpolation, f

DAC

/4 modulation, Hilbert Off.

AD9786

Rev. 0 | Page 5 of 60

DYNAMIC SPECIFICATIONS

MIN

to T

MAX

, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, I

OUTFS

= 20 mA, differential transformer

coupled output, 50 doubly terminated, unless otherwise noted.

Table 2.

Parameter

Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f

DAC

) 500

MSPS

Output Settling Time (t

) (to 0.025%)

Output Propagation Delay

)

Output Rise Time (10% to 90% of Full Scale)

Output Fall Time (90% to 10% of Full Scale)

AC LINEARITY-BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

OUT

= 0 dBFS)

DATA

= 100 MSPS; f

OUT

= 5 MHz, 4×, 2× interpolation

dBc

DATA

= 200 MSPS; f

OUT

= 10 MHz

dBc

DATA

= 200 MSPS; f

OUT

= 25 MHz

dBc

DATA

= 200 MSPS; f

OUT

= 50 MHz

dBc

Two-Tone Intermodulation (IMD) to Nyquist (f

OUT1

= f

OUT2

= 6 dBFS)

DATA

= 200 MSPS; f

OUT1

= 5 MHz; f

OUT2

= 6 MHz

dBc

DATA

= 200 MSPS; f

OUT1

= 15 MHz; f

OUT2

= 16 MHz

dBc

DATA

= 200 MSPS; f

OUT1

= 25 MHz; f

OUT2

= 26 MHz

dBc

DATA

= 200 MSPS; f

OUT1

= 45 MHz; f

OUT2

= 46 MHz

dBc

DATA

= 200 MSPS; f

OUT1

= 65 MHz; f

OUT2

= 66 MHz

dBc

DATA

= 200 MSPS; f

OUT1

= 85 MHz; f

OUT2

= 86 MHz

dBc

Noise Power Spectral Density (NPSD)

DATA

= 156 MSPS; f

OUT

= 10 MHz; 0 dBFS, 8 tones, separation = 500 kHz

-164

dBm/Hz

DATA

= 156 MSPS; f

OUT

= 50 MHz; 0 dBFS, 8 tones, separation = 500 kHz

-161

dBm/Hz

Adjacent Channel Power Ratio (ACLR)

WCDMA ACLR with 3.84 MHz BW, single carrier

IF = 21 MHz, f

DATA

= 122.88 MSPS, 4× interpolation

IF = 224.76 MHz, f

DATA

= 122.88 MSPS, 4× interpolation, high-pass interpolation filter mode

Propagation delay is delay from CLK input to DAC update.

Measured doubly terminated into 50 load.

AD9786

Rev. 0 | Page 7 of 60

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

With Respect to

Min

Max Unit

AVDD1, AVDD2, DRVDD
ACVDD, ADVDD, CLKGND, DVDD
AGND1, AGND2, ACGND, ADGND, CLKGND,
DGND
REFIO, FSADJ
I

OUTA

, I

OUTB

P1B15-P1B0, P2B15-P2B0
DATACLK
CLK+, CLK-, RESET
CSB, SCLK, SDIO, SDO
Junction Temperature
Storage Temperature
Lead temperature (10 sec)

AGND1, AGND2, ACGND, ADGND, CLKGND, DGND
AGND1, AGND2, ACGND, ADGND, CLKGND, DGND
AGND1, AGND2, ACGND, ADGND, CLKGND, DGND

AGND1

AGND1
DGND
DGND
CLKGND
DGND

-0.3
-0.3
-0.3

-0.3
-1.0
-0.3
-0.3
-0.3
-0.3
-65

+3.6
+2.8
+0.3

AVDD1 + 0.3
AVDD1 + 0.3
DVDD + 0.3
DRVDD + 0.3
CLKVDD + 0.3
DVDD + 0.3
+125
150
300

V
V
V

V
V
V
V
V
V
°C
°C

°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

80-Lead Thermally Enhanced

TQFP Package

= 23.5° C/W (with thermal pad soldered to PCB)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

AD9786

Rev. 0 | Page 8 of 60

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80 79 78 77 76

71 70 69 68 67 66 65

75 74 73 72

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN 1
IDENTIFIER

DNC = DO NOT CONNECT

DNC

ADV

ADGND

ACV

ACGND

DD2

AGND2

DD1

AGND1

IOUTA

IOUTB

AGND1

DD1

AGND2

DD2

ACGND

ACV

ADGND

ADV

DNC

CLKVDD

DNG

CLKVDD

CLKGND

CLK+
CLK

CLKGND

DGND

DVDD

P1B15
P1B14
P1B13
P1B12

P1B11

P1B10

DGND

DVDD

P1B9
P1B8
P1B7

FSADJ
REFIO
RESET
CSB
SCLK
SDIO
SDO
DGND
DVDD
P2B0
P2B1
P2B2
P2B3
P2B4
P2B5
DGND

P1B

DGND

P1B

DRV

IQSEL/P2B15

ONE

RTCLOCK/P

P2B

DGND

DATACLK

AD9786

TOP VIEW

(Not to Scale)

DVDD
P2B6
P2B7
P2B8

P2B

03152-0-002

Figure 2. Pin Configuration

CLOCK

Table 5. Clock Pin Function Descriptions

Pin
No.

Name Direction

Description

5, 6

CLK+, CLK

Differential Clock Input.

DNC

Do Not Connect.

DCLKEXT
02h[3]

Mode

Pin configured for input of channel data rate or synchronizer clock.
Internal clock synchronizer may be turned on or off with DCLKCRC
(02h[2]).

31 DATACLK

I/O

Pin configured for output of channel data rate or synchronizer
clock.

1, 3

CLKVDD

Clock Domain 2.5 V.

4, 7

CLKGND

Clock Domain 0 V.

AD9786

Rev. 0 | Page 9 of 60

ANALOG

Table 6. Analog Pin Function Descriptions

Pin No.

Name

Direction

Description

59 REFIO

Reference.

60 FSADJ

Full-Scale

Adjust.

70, 71

IOUTB, IOUTA

Differential DAC Output Currents.

DNC

Do Not Connect.

62, 79

ADVDD

Analog Domain Digital Content 2.5 V.

63, 78

ADGND

Analog Domain Digital Content 0 V.

64, 77

ACVDD

Analog Domain Clock Content 2.5 V.

65, 76

ACGND

Analog Domain Clock Content 0 V.

66, 75

AVDD2

Analog Domain Clock Switching 3.3 V.

67, 74

AGND2

Analog Domain Switching 0 V.

68, 73

AVDD1

Analog Domain Quiet 3.3 V.

69, 72

AGND1

Analog Domain Quiet 0 V.

DNC

Do Not Connect.

DATA

Table 7. Data Pin Function Descriptions

Pin No.

Name

Direction

Description

Input Data Port One.

ONEPORT
02h[6] Mode

Latched data routed for I channel processing.

1015, 1824,
2729

P1B15P1B0 I

Latched data demultiplexed by IQSEL and routed for interleaved
I/Q processing.

ONEPORT
02h[6]

IQPOL
02h[1]

IQSEL/
P2B15

Mode (IQPOL = 0)

0 X

Latched data routed to Q channel Bit 15 (MSB)
processing.

1 0

Latched data on Data Port One routed to Q
channel processing.

1 0

Latched data on Data Port One routed to I
channel processing.

1 1

Latched data on Data Port One routed to I
channel processing.

32 IQSEL/P2B15

1 1

Latched data on Data Port One routed to Q
channel processing.

ONEPORT
02h[6]

Latched data routed for Q channel Bit 14 processing.

33 ONEPORTCLK/P2B14

I/O

Pin configured for output of clock at twice the channel data route.

34, 37-43,
4651

P2B13-P2B0

Input Data Port Two Bits 130.

DRVDD

Digital Output Pin Supply, 2.5 V or 3.3 V.

9, 17, 26,
36, 44, 52

DVDD

Digital Domain 2.5 V.

8, 16, 25,
35, 45, 53

DGND

Digital Domain 0 V.

AD9786

Rev. 0 | Page 11 of 60

DEFINITION OF SPECIFICATIONS

Linearity Error (Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normal-
ized to full scale, associated with a 1 LSB change in digital
input code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I

OUTA

, 0 mA output is expected when the

inputs are all 0s. For I

OUTB

, 0 mA output is expected when all

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).

Signal-to-Noise Ratio (SNR)

S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc. The
value for SNR is expressed in decibels.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of
f

DATA

(interpolation rate), a digital filter can be constructed

which has a sharp transition band near f

DATA

/2. Images that

would typically appear around f

DAC

(output data rate) can be

greatly suppressed.

Pass Band

Frequency band in which any input applied therein passes
unattenuated to the DAC output.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.

Group Delay

Number of input clocks between an impulse applied at the
device input and peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range

Impulse Response

Response of the device to an impulse applied to the input.

Adjacent Channel Leakage Ratio (or ACLR)

A ratio in dBc between the measured power within a channel
relative to its adjacent channel.

AD9786

Rev. 0 | Page 12 of 60

Complex Modulation

The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = e

jwt

coswt + jsinwt) and realizing real and imaginary components
on the modulator output.

Hilbert Transform

A function with unity gain over all frequencies, but with a phase
shift of 90 degrees for negative frequencies, and a phase shift of
90 degrees for positive frequencies. Although this function can
not be implemented ideally, it can be approximated with a short
FIR filter with enough accuracy to be very useful in single
sideband radio architectures.

Complex Image Rejection

In a traditional two part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex
modulator in series with the first complex modulator, either the
upper or lower frequency image near the second IF can be
rejected.

AD9786

Rev. 0 | Page 13 of 60

TYPICAL PERFORMANCE CHARACTERISTICS

MIN

to T

MAX

, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, I

OUTFS

= 20 mA, differential transformer

coupled output, 50 doubly terminated, unless otherwise noted.

03152-P

r
D-035

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 3. SFDR vs. Frequency, F

DATA

= 200 MSPS, 1× Interpolation

03152-P

r
D-038

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 4. SFDR vs. Frequency, F

DATA

= 100 MSPS, 4× Interpolation

03152-P

r
D-040

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 5. SFDR vs. Frequency, F

DATA

= 50 MSPS, 8× Interpolation

03152-P

r
D-037

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 6. SFDR vs. Frequency, F

DATA

= 200 MSPS, 2× Interpolation

03152-P

r
D-039

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 7. SFDR vs. Frequency, F

DATA

= 125 MSPS, 4× Interpolation

03152-P

r
D-041

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 8. SFDR vs. Frequency, F

DATA

= 62.5 MSPS, 8× Interpolation

AD9786

Rev. 0 | Page 14 of 60

03152-P

r
D-045

OUT

(MHz)

200

120

140

160

180

100

IMD

(
dBc)

100

0dBFS

6dBFS

3dBFS

Figure 9. Out of Band SFDR, F

DATA

= 200 MSPS, 2× Interpolation

03152-P

r
D-047

OUT

(MHz)

260

200 220 240

120 140 160 180

80 100

IMD

(
dBc)

100

0dBFS

6dBFS

3dBFS

Figure 10. Out of Band SFDR, F

DATA

= 125 MSPS, 4× Interpolation

03152-P

r
D-049

OUT

(MHz)

260

120 140 160 180 200 220 240

80 100

IMD

(
dBc)

100

6dBFS

0dBFS

3dBFS

Figure 11. Out of Band SFDR, F

DATA

= 62.5 MSPS, 8× Interpolation

03152-P

r
D-046

OUT

(MHz)

200

120

140

160

180

100

IMD

(
dBc)

100

0dBFS

6dBFS

3dBFS

Figure 12. Out of Band SFDR, F

DATA

= 100 MSPS, 4× Interpolation

03152-P

r
D-040

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 13. Out of Band SFDR, F

DATA

= 50 MSPS, 8× Interpolation

03152-P

r
D-039

FREQUENCY (MHz)

DR (dBc

)

120

100

0dBFS

6dBFS

3dBFS

Figure 14. Third Order IMD vs. Frequency, F

DATA

= 160 MSPS, 1× Interpolation

AD9786

Rev. 0 | Page 15 of 60

03152-P

r
D-044

OUT

(MHz)

160

120

140

100

IMD

(
dBc)

100

6dBFS

0dBFS

3dBFS

Figure 15. Third Order IMD vs. Frequency, F

DATA

= 160 MSPS, 2× Interpolation

03152-P

rD-045

OUT

(MHz)

200

120

140

160

180

100

IMD

(
dBc)

100

0dBFS

6dBFS

3dBFS

Figure 16. Third Order IMD vs. Frequency, F

DATA

= 200 MSPS, 2× Interpolation

03152-P

r
D-047

OUT

(MHz)

260

200 220 240

120 140 160 180

80 100

IMD

(
dBc)

100

0dBFS

6dBFS

3dBFS

Figure 17. Third Order IMD vs. Frequency, F

DATA

= 125 MSPS, 4× Interpolation

03152-P

r
D-043

OUT

(MHz)

100

IMD

(
dBc)

100

6dBFS

0dBFS

3dBFS

Figure 18. Third Order IMD vs. Frequency, F

DATA

= 200 MSPS,1x Interpolation

03152-P

r
D-046

OUT

(MHz)

200

120

140

160

180

100

IMD

(
dBc)

100

0dBFS

6dBFS

3dBFS

Figure 19. Third Order IMD vs. Frequency, F

DATA

= 100 MSPS, 4× Interpolation

03152-P

r
D-048

OUT

(MHz)

200

120

140

160

180

100

IMD

(
dBc)

100

0dBFS

6dBFS

3dBFS

Figure 20. Third Order IMD vs. Frequency, F

DATA

= 50 MSPS, 8× Interpolation

AD9786

Rev. 0 | Page 16 of 60

03152-P

r
D-049

OUT

(MHz)

260

120 140 160 180 200 220 240

80 100

IMD

(
dBc)

100

6dBFS

0dBFS

3dBFS

Figure 21. Third Order IMD vs. Frequency, F

DATA

= 62.5 MSPS, 8× Interpolation

03152-0-046

CODE

65536

8192

16384 24576

49152 57344

32768 40960

INL

(
LSBs)

0.6

0.2

0.4

0.2

0.4

Figure 22. Typical INL

03152-P

r
D-054

ANALOG OUTPUT FREQUENCY (MHz)

160

120

140

100

OISE SPEC

ITY

(
dB

m/H

z
)

180

140

150

145

155

160

165

170

175

DATA

= 156MSPS, 1× INTERPOLATION

DATA

= 156MSPS, 2× INTERPOLATION

Figure 23. Noise Spectral Density vs. Analog

Input Frequency, F

DATA

= 156 MSPS, Interpolation = 1x

03152-0-047

CODE

65536

8192

16384 24576

49152 57344

32768 40960

DNL

(LS

)

0.4

0.3

0.2

0.1

0.2

0.3

Figure 24. Typical DNL

03152-P

r
D-053

ANALOG OUTPUT FREQUENCY (MHz)

OISE SPEC

ITY

(
dB

m/H

z
)

180

140

150

145

155

160

165

170

175

DATA

= 78MSPS, 1× INTERPOLATION

DATA

= 78MSPS, 2× INTERPOLATION

Figure 25. Noise Spectral Density vs. Analog

Input Frequency, F

DATA

= 78 MSPS, Interpolation = 1x

03152-P

r
D-054

ANALOG OUTPUT FREQUENCY (MHz)

160

120

140

100

OISE SPEC

ITY

(
dB

m/H

z
)

180

140

150

145

155

160

165

170

175

DATA

= 156MSPS, 1× INTERPOLATION

DATA

= 156MSPS, 2× INTERPOLATION

Figure 26. Noise Spectral Density vs. Analog Input Frequency, F

DATA

= 78 MSPS

Interpolation = 2x

AD9786

Rev. 0 | Page 17 of 60

03152-P

r
D-054

ANALOG OUTPUT FREQUENCY (MHz)

160

120

140

100

OISE SPEC

ITY

(
dB

m/H

z
)

180

140

150

145

155

160

165

170

175

DATA

= 156MSPS, 1× INTERPOLATION

DATA

= 156MSPS, 2× INTERPOLATION

Figure 27. Noise Spectral Density vs. Analog Input Frequency,

DATA

= 156 MSPS Interpolation = 2x

03152-P

r
D-055

OUT

(MHz)

150

100

125

ACLR

(
dBc

)

90

60

65

70

75

80

85

6dBFS

0dBFS

3dBFS

Figure 28. ACLR for First Adjacent Band vs. Frequency,

DATA

= 61.44 MSPS, 4× Interpolation

03152-P

r
D-056

OUT

(MHz)

200

100

120

140

160

180

ACLR

(
dBc

)

90

60

65

70

75

80

85

3dBFS

0dBFS

6dBFS

Figure 29. ACLR for First Adjacent Band vs. Frequency,

DATA

= 76.8 MSPS, 4× Interpolation

03152-P

r
D-059

10

20

30

40

50

60

70

80

90

100

110

START 100 kHz

STOP 200 MHz

19.9 MHz/

1MA

1AVG

Figure 30. Two Tones around 23 MHz, F

DATA

= 200 MSPS, 2× Interpolation,

Low-Pass Digital Filter Mode

03152-P

r
D-060

10

20

30

40

50

60

70

80

90

100

110

START 100 kHz

STOP 200 MHz

19.9 MHz/

1MA

1AVG

Figure 31. Two Tones around 177 MHz, F

DATA

= 200 MSPS, 2× Interpolation,

High-Pass Digital Filter Mode

03152-0-031

SPAN 43.84MHz

SWEEP 142.2ms (601 pts)

VBW 300kHz

CENTER 51.44MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER
17.41dBm/
3.84MHz

FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz
20.000MHz

REF BW
3.840MHz
3.840MHz
3.840MHz
3.840MHz

dBc
0.15
74.24
75.73
75.67

dBm
17.26
91.65
93.14
93.08

LOWER

dBc
74.63
75.67
76.38
75.75

dBm
92.05
93.08
93.79
93.17

UPPER

REF 29.82dBm
*AVG
Log
10dB/

PAVG
22
W1 S2

*ATTEN 6dB

AVERAGE
103

Figure 32. ACLR for Two WCDMA Carriers at 51.44 MHz, F

DATA

= 61.44 MSPS,

4× Interpolation

AD9786

Rev. 0 | Page 18 of 60

03152-0-028

SPAN 33.84MHz

SWEEP 109.8ms (601 pts)

VBW 300kHz

CENTER 20.00MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER
10.38dBm/
3.84 MHz

FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz

REF BW
3.840MHz
3.840MHz
3.840MHz

dBc
79.00
80.78
79.71

dBm
89.38
91.16
90.09

LOWER

dBc
79.63
81.77
81.45

dBm
90.01
92.15
91.83

UPPER

REF 22.76dBm
*AVG
Log
10dB/

PAVG
22
W1 S2

*ATTEN 8dB

AC-COUPLED

AVERAGE
22

Figure 33. ACLR for Single WCDMA Carrier at 20 MHz, F

DATA

= 61.44 MSPS,

4× Interpolation

03152-0-030

SPAN 33.84MHz

SWEEP 109.8ms (601 pts)

VBW 300kHz

CENTER 142.88MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER
15.30dBm/
3.84MHz

FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz

REF BW
3.840MHz
3.840MHz
3.840MHz

dBc
72.33
72.41
72.67

dBm
87.64
87.71
87.97

LOWER

dBc
72.13
73.02
73.50

dBm
87.43
88.32
88.88

UPPER

REF 28.2dBm
*AVG
Log
10dB/

PAVG
22
W1 S2

*ATTEN 6dB

AVERAGE
22

Figure 34. ACLR for Single WCDMA Carrier at 142.88 MHz, F

DATA

= 61.44 MSPS,

4× Interpolation

03152-0-032

SPAN 53.84MHz

SWEEP 174.6ms (601 pts)

VBW 300kHz

CENTER 46.40MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER
20.32dBm/
3.84MHz

FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz
20.000MHz
25.000MHz

REF BW
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz

dBc
0.22
0.60
72.68
72.74
73.05

dBm
20.11
20.92
93.00
93.06
93.37

LOWER

dBc
0.16
72.05
72.85
72.55
72.02

dBm
20.48
92.37
93.18
92.88
92.35

UPPER

REF 33.3dBm
*AVG
Log
10dB/

PAVG
104
W1 S2

*ATTEN 6dB

AVERAGE
104

AC-COUPLED

Figure 35. ACLR for Four-Carrier WCDMA Signal Near 50 MHz, F

DATA

61.44 MSPS, 4× Interpolation

AD9786

Rev. 0 | Page 19 of 60

SERIAL CONTROL INTERFACE

AD9786 SPI
PORT INTERFACE

SDO (PIN 54)

SDIO (PIN 55)

SCLK (PIN 56)

CSB (PIN 57)

03152-0-048

Figure 36. AD9786 SPI Port Interface

The AD9786 serial port is a flexible, synchronous serial
communications port, allowing easy interface to many industry-
standard microcontrollers and microprocessors. The serial I/O
is compatible with most synchronous transfer formats,

including both the Motorola SPI

and Intel

SSR protocols. The

interface allows read/write access to all registers that configure
the AD9786. Single or multiple byte transfers are supported, as
well as MSB first or LSB first transfer formats. The AD9786's
serial interface port can be configured as a single pin I/O
(SDIO) or two unidirectional pins for in/out (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the
AD9786. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9786, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9786 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD9786.

A logic high on the CS pin, followed by a logic low, will reset the
SPI port timing to the initial state of the instruction cycle. This
is true regardless of the present state of the internal registers or
the other signal levels present at the inputs to the SPI port. If the
SPI port is in the midst of an instruction cycle or a data transfer
cycle, none of the present data will be written.

The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9786 and the system controller. Phase 2 of the
communication cycle is a transfer of 1, 2, 3, or 4 data bytes as
determined by the instruction byte. Using one multibyte
transfer is the preferred method. Single byte data transfers are
useful to reduce CPU overhead when register access requires
one byte only. Registers change immediately upon writing to the
last bit of each transfer byte.

Instruction Byte

The instruction byte contains the following information:

Table 9.

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer will occur after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation. N1, N0, Bits 6 and 5 of the instruction byte,
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in Table 10.

Table 10.

MSB

LSB

I6 I5 I4 I3 I2 I1 I0

R/W N1 N0 A4 A3 A2 A1 A0

A4, A3, A2, A1, A0

, Bits 4, 3, 2, 1, 0 of the instruction byte,

determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers,
this address is the starting byte address. The remaining register
addresses are generated by the AD9786.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK--Serial Clock

. The serial clock pin is used to

synchronize data to and from the AD9786 and to run the
internal state machines. SCLK's maximum frequency is 20 MHz.
All data input to the AD9786 is registered on the rising edge of
SCLK. All data is driven out of the AD9786 on the falling edge
of SCLK.

CSB--Chip Select

. Active low input starts and gates a

communication cycle. It allows more than one device to be used
on the same serial communications lines. The SDO and SDIO
pins will go to a high impedance state when this input is high.
Chip select should stay low during the entire communication
cycle.

SDIO--Serial Data I/O

. Data is always written into the

AD9786 on this pin. However, this pin can be used as a
bidirectional data line. The configuration of this pin is
controlled by Bit 7 of register address 00h. The default is
Logic 0, which configures the SDIO pin as unidirectional.

SDO--Serial Data Out

. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the
case where the AD9786 operates in a single bidirectional I/O
mode, this pin does not output data and is set to a high
impedance state.

AD9786

Rev. 0 | Page 20 of 60

MSB/LSB TRANSFERS

The AD9786 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by register address DATADIR
(00h[6]). The default is MSB first. When this bit is set active
high, the AD9786 serial port is in LSB first format. That is, if the
AD9786 is in LSB first mode, the instruction byte must be
written from least significant bit to most significant bit.
Multibyte data transfers in MSB format can be completed by
writing an instruction byte that includes the register address of
the most significant byte. In MSB first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB first mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.

The AD9786 serial port controller address will increment from
1Fh to 00h for multibyte I/O operations if the MSB first mode is
active. The serial port controller address will decrement from
00h to 1Fh for multibyte I/O operations if the LSB first mode
is active.

NOTES ON SERIAL PORT OPERATION

The AD9786 serial port configuration bits reside in Bits 6 and 7
of register address 00h. It is important to note that the
configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register
may occur during the middle of communication cycle. Care
must be taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.

The same considerations apply to setting the software reset,
SWRST (00h[5]) bit. All other registers are set to their default
values, but the software reset does not affect the bits in Register
Address 00h and 04h.

It is recommended to use only single byte transfers when
changing serial port configurations or initiating a soft-
ware reset.

R/W N0 N1 A0 A1

A2 A3 A4 D7 D6

D7 D6

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

03152-0-004

Figure 37. Serial Register Interface Timing MSB First

A0 A1 A2 A3 A4

N1 N0 R/W D0

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

03152-0-005

Figure 38. Serial Register Interface Timing LSB First

INSTRUCTION BIT 6

INSTRUCTION BIT 7

CSB

SCLK

SDIO

PWH

PWL

SCLK

03152-P

r
D-006

Figure 39. Timing Diagram for Register Write

DATA BIT n1

DATA BIT n

CSB

SCLK

SDIO

SDO

03152-P

r
D-007

Figure 40. Timing Diagram for Register Read

AD9786

Rev. 0 | Page 21 of 60

MODE CONTROL (VIA SERIAL PORT)

Table 11.

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

COMMS 00

SDIODIR DATADIR SWRST

SLEEP

PDN

EXREF

FILTER

INTERP[1]

INTERP[0]

ZSTUFF

HPFX8

HPFX4

HPFX2

DATA 02

DATAFMT

ONEPORT

DCLKSTR

DCLKPOL DCLKEXT DCLKCRC IQPOL CRAYDIN

MODULATE 03 CHANNEL

HILBERT

MODDUAL

SIDEBAND

MOD[1]

MOD[0]

RESERVED

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

DCLKCRC 05

DATADJ[3] DATADJ[2] DATADJ[1] DATADJ[0] MODSYNC MODADJ[2] MODADJ[1]

MODADJ[0]

Reserved

CALMEMCK 0E

CALMEM[1] CALMEN[0]

CALCKDIV[2]

MEMRDWR 0F CALSTAT

CALEN

XFERSTAT

XFEREN

SMEMWR

SMEMRD

FMEMRD

UNCAL

MEMADDR 10 MEMADDR[7] MEMADDR[6] MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]

MEMDATA 11

MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]

DCRCSTAT

DCRCSTAT[2] DCRCSTAT[1] DCRCSTAT[0]

Table 12.

COMMS(00) Bit

Direction

Default

Description

SDIODIR

0: SDIO pin configured for input only during data transfer
1: SDIO configured for input or output during data transfer

DATADIR

0: Serial data uses MSB first format
1: Serial data uses LSB first format

SWRST

1: Default all serial register bits, except addresses 00h and 04h

SLEEP

1: DAC output current off

PDN

1: All analog and digital circuitry, except serial interface, off

EXREF

0: Internal band gap reference
1: External reference

Table 13.

FILTER(01) Bit

Direction

Default

Description

INTERP[1:0]

[7:6]

00: No interpolation
01: Interpolation 2×
10: Interpolation 4×
11: Interpolation 8×

ZSTUFF

1: Zero Stuffing on

HPFX8

0: ×8 interpolation filter configured for low pass
1: ×8 interpolation filter configured for high pass

HPFX4

0: ×4 interpolation filter configured for low pass
1: ×4 interpolation filter configured for high pass

HPFX2

0: ×2 interpolation filter configured for low pass
1: ×2 interpolation filter configured for high pass

AD9786

Rev. 0 | Page 22 of 60

Table 14.

DATA(02)

Bit

Direction

Default

Description

DATAFMT

0: Twos complement data format
1: Unsigned binary input data format

ONEPORT

0: I and Q input data onto ports one and two, respectively
1: I and Q input data interleaved onto port one

DCLKSTR

0: DATACLK pin 12 mA drive strength
1: DATACLK pin 24 mA drive strength

DCLKPOL

0: Input data latched on DATACLK rising edge
1: Input data latched on DATACLK falling edge

DCLKEXT

0: DATACLK pin inputs channel data rate or modulator synchronizer clock
1: DATACLK pin outputs channel data rate or modulator synchronizer clock

DCLKCRC

0: With DATACLK pin as input, DATACLK clock recovery off
1: With DATACLK pin as input, DATACLK clock recovery on

IQPOL 1

I 0

0: In one port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data
into Q channel
1: In one port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data
into Q channel

GRAYDIN

0: Gray decoder off
1: Gray decoder on

Table 15.

MODULATE(03) Bit Direction Default Description

MODDUAL
03h [5]

CHANNEL
03h[7]

I channel processing routed to DAC

Q channel processing routed to DAC

1 0 Modulator

real

output routed to DAC

CHANNEL 7

I 0

1 1 Modulator

imaginary

output routed to DAC

HILBERT

1: With MODDUAL on, Hilbert transform on

MODDUAL

0: Modulator uses a single channel
1: Modulator uses both I and Q channels

SIDEBAND

0: With MODDUAL on, lower sideband rejected
1: With MODDUAL on, upper sideband rejected

MOD[1:0]

[3:2]

00: No modulation
01: f

/2 modulation

10: f

/4 modulation

11: f

/8 modulation

AD9786

Rev. 0 | Page 23 of 60

Table 16.

DCLKCRC(05) Bit

Direction

Default

Description

DATADJ[3:0] [7:4]

I 0000

DATACLK

offset.

Twos complement representation

0111: +7
:
0000: 0
:
1000: -8

MODSYNC

0: Channel data rate clock synchronizer mode
1: State machine clock synchronizer mode

/8 f

/4 f

000 1

001 1/2

010 0

011 1/2

100 1

101 1/2

110 0

MODADJ[2:0] [2:0]

I 000

111 1/2

Modulator coefficient offset

Table 17.

VERSION(0D) Bit

Direction

Default

Description

VERSION[3:0]

[3:0]

Hardware version identifier

Table 18.

CALMEMCK(OE) Bit

Direction

Default

Description

CALMEM [5:4]

Calibration

memory

00: Uncalibrated
01: Self calibration
10: Factory calibration
11: User input

CALCKDIV[2:0] [2:0]

Calibration

clock

divide ratio from channel data rate

000: /32
001: /64
:
110: /2048
111: /4096

Table 19.

MEMRDWR(OF) Bit

Direction

Default

Description

CALSTAT

0: Self calibration cycle not complete
1: Self calibration cycle complete

CALEN

1: Self calibration in progress

XFERSTAT

0: Factory memory transfer not complete
1: Factory memory transfer complete

XFEREN

1: Factory memory transfer in progress

SMEMWR

1: Write static memory data from external port

SMEMRD

1: Read static memory to external port

FMEMRD

1: Read factory memory data to external port

UNCAL

1: Use uncalibrated

AD9786

Rev. 0 | Page 25 of 60

DIGITAL FILTER SPECIFICATIONS

DIGITAL INTERPOLATION FILTER COEFFICIENTS

Table 23. Stage 1 Interpolation Filter Coefficients

Lower Coefficient

Upper Coefficient

Integer Value

H(1) H(43)

H(2) H(42)

H(3) H(41)

H(4) H(40)

H(5) H(39)

H(6) H(38)

H(7) H(37)

131

H(8) H(36)

H(9) H(35)

239

H(10) H(34) 0
H(11) H(33) 407
H(12) H(32) 0
H(13) H(31) 665
H(14) H(30) 0
H(15) H(29) 1070
H(16) H(28) 0
H(17) H(27) 1764
H(18) H(26) 0
H(19) H(25) 3273
H(20) H(24) 0
H(21) H(23) 10358
H(22)

16384

Table 24. Stage 2 Interpolation Filter Coefficients

Lower Coefficient

Upper Coefficient

Integer Value

H(1) H(19)

H(2) H(18)

H(3) H(17)

120

H(4) H(16)

H(5) H(15)

436

H(6) H(14)

H(7) H(13)

1284

H(8) H(12)

H(9) H(11)

5045

H(10)

8192

Table 25. Stage 3 Interpolation Filter Coefficients

Lower Coefficient

Upper Coefficient

Integer Value

H(1) H(11)

H(2) H(10)

H(3) H(9) 53
H(4) H(8) 0
H(5) H(7) 302
H(6)

512

03152-P

r
D-008

0.5

0.5 0.4 0.3 0.2 0.1

0.1

0.2

0.3

0.4

140

20

40

60

80

100

120

Figure 41. ×2 Interpolation Filter Response

03152-P

r
D-009

0.5

0.5 0.4 0.3 0.2 0.1

0.1

0.2

0.3

0.4

140

20

40

60

80

100

120

Figure 42. ×4 Interpolation Filter Response

03152-P

r
D-010

0.5

0.5 0.4 0.3 0.2 0.1

0.1

0.2

0.3

0.4

140

20

40

60

80

100

120

Figure 43. ×8 Interpolation Filter Response

AD9786

Rev. 0 | Page 26 of 60

AD9786 CLOCK/DATA TIMING

Table 26. Data Port Synchronization

DCLKEXT
02h, Bit 3

MODSYNC
05h, Bit 3

DCLKCRC
02h, Bit 2

Mode

Function

1 0 X DATACLK

Master

Channel data rate clock output

1 1 X Modulator

Master

Modulator synchronization DATACLK output

External Sync Mode

DATACLK inactive, DACCLK synchronous with external data

DATACLK Slave

DATACLK input, data rate clock, Data Recovery On

Low Setup/Hold

DATACLK input, input data synchronous with DATACLK

Modulator Slave

Input modulator synchronizer DATACLK input

Two-Port Data Input Mode, DATACLK Master

With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same
frequency. Note that DACCLK refers to the differential clock
inputs applied at Pins 5 and 6. As Figure 44 and Figure 45 show,
there is a constant delay between the edges of DACCLK and
DATACLK.

The DCLKPOL bit (Reg 02 Bit 4) allows the data to be latched
into the AD9786 on either the rising or falling edge of
DACCLK. With DCLKPOL = 0, the data is latched in on the
falling edge of DACCLK, as shown in Figure 44. With
DCLKPOL = 1, as shown in Figure 45, data is latched in on the
rising edge of DACCLK. The setup and hold times are always
with respect to the latching edge of DACCLK.

03152-0-040

DACCLK

DATACLK

OUT

DATA

= 6ns TYP

= 2.9ns MIN

= 0.5ns MIN

Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0

03152-0-045

= 300ps TYP

= 2.9ns TYP

DACCLK

DATA

Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1

AD9786

Rev. 0 | Page 27 of 60

With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the
digital inputs of the AD9786 on every other rising edge of
DACCLK, as shown in Figure 47 and Figure 48. With
DCLKPOL = 0, as shown in Figure 47, the latching edge of
DACCLK is the rising edge that occurs just before the falling
edge of DATACLK. With DCLKPOL = 1, as in Figure 48, the
latching edge of DACCLK is the rising edge of DACCLK that
occurs just before the rising edge of DATACLK. The setup
and hold time values are identical to those in Figure 44 and
Figure 45.

Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 46 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.

With the interpolation set to 4× or 8×, the DACCLK input runs
at 4× or 8× the speed of the DATACLK output. The data is
latched in on a rising edge of DACCLK, similar to the 2×
interpolation mode. However, the latching edge is every fourth
edge in 4× interpolation mode and every eighth edge in the 8×

interpolation mode. Similar to operation in the 2× interpolation
mode, with DCLKPOL = 0, the latching edge of DACCLK is the
rising edge that occurs just before the falling edge of
DATACLK. With DCLKPOL = 1, the latching edge of DACCLK
is the rising edge that occurs just before the rising edge of
DATACLK. The setup and hold time values are identical to
those in 1× and 2× interpolation.

03152-P

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D-068

Figure 46.

= 5ns TYP

= 0.5ns MIN

= 2.9ns MIN

DACCLK

DATACLK

OUT

DATA

03152-0-020

Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0

03152-0-022

= 6ns TYP

= 2.9ns MIN

= 0.5ns MIN

DACCLK

DATACLK

OUT

DATA

Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1

AD9786

Rev. 0 | Page 28 of 60

AD9786 DATACLK Slave Mode, Data Recovery On

DATACLK (Pin 31) can be used as an input in order to
synchronize multiple AD9786s. A clock generated by an
AD9786 operating in master mode, or a clock from an external
source, can be used to drive DATACLK.

In this mode, there are two clocks required to be applied to the
AD9786. A clock running at the DAC sample rate, referred to as
DACCLK, must be applied to the differential inputs (Pins 5 and
6) of the AD9786. As described above, a clock at the input
sample rate must also be applied to Pin 31 (DATACLK). An
internal DLL synchronizes the two applied clocks. The timing
relationships between the input data, DATACLK, and DACCLK
are given in Figure 49 and Figure 50.

Note that DCLKPOL (Reg 02h, Bit 4) can be used to select the
edge of DACCLK upon which the input data is latched.

There is a defined setup and hold window with respect to input
data and the latching edge of DACCLK. There is also a required
timing relationship between DATACLK and DACCLK. This is
referred to in Figure 49 and Figure 50 as t

and t

(setup and

hold for transition). As an example, with DCLKPOL set to
logic 0, the input data will latch on the first rising edge of
DACCLK which occurs greater than 1.5 ns before the falling
edge of DATACLK. DACCLK should not be given a rising edge
in the window of 500 ps to 1.5 ns before the latching edge
(falling when DCLKPOL = 0, rising when DCLKPOL = 1) of
DATACLK. Failure to account for this timing relationship may
result in corrupt data.

There are three status bits available for read which allow the
user to verify DLL lock. These are Bits 0, 1, and 2 (DCRCSTAT)
in Reg 12h.

03152-0-023

DACCLK

DATACLK

DATA

= 1.5ns MIN

= 0.0ns MIN

= 500ps MIN

= 3.2ns MIN

Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0

03152-0-042

DACCLK

DATACLK

DATA

= 2.0ns MIN

= 0.0ns MIN

= 1.0ns MIN

= 3.2ns MIN

Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1

AD9786

Rev. 0 | Page 29 of 60

AD9786 Low Setup/Hold Mode (DATACLK input, data
recovery off)

Some applications may require that digital input data be
synchronized with the DATACLK input, rather than DACCLK.
For these applications, the AD9786 can be programmed for Low
Setup/Hold Mode by entering the values in Table 26 into the
SPI registers. With data recovery off and the MODSYNC bit set
to logic 1, the AD9786 will latch data in on the rising or falling
edge of DATACLK input, depending on the state of DCLKPOL.

The timing is similar to the slave mode with data recovery on.
There is still a required timing relationship between DACCLK
and DATACLK in, as shown in Figure 51 and Figure 52. As
these show, the digital input data is latched in on the
DATACLK edge, rather than DACCLK. One advantage of this
mode is that the setup and hold numbers for the input data with
respect to DATACLK are much smaller than the similar specs in
the slave/clock recovery mode.

Note that in this mode, the DATAADJ bits have no effect.

03152-0-043

= 0.0ns MIN

= 1.1ns MIN

= 2.8ns MIN

DACCLK

DATACLK

DATA

= 3.0ns MIN

Figure 51. Low Setup and Hold Mode Timing, 2× Interpolation, DCLKPOL = 0

03152-0-044

DACCLK

DATACLK

DATA

= 1.8ns MIN

= 3.1ns MIN

= 1.0ns MIN

= 2.0ns MIN

Figure 52. Low Setup and Hold Mode Timing, 2× Interpolation, DCLKPOL = 1

AD9786

Rev. 0 | Page 30 of 60

AD9786 External Sync Mode

There is one additional timing mode in which the AD9786 may
be used. In the External Sync Mode, the DATACLK is
programmed as an input, but is not used. Applying a DATACLK
input while in this mode will have no effect. The digital input
data is synchronized solely to the DACCLK input. With 1×
interpolation, this means that the data input will be latched on
every rising edge of DACCLK. The challenge is that the user has
no way of knowing exactly which edge is the latching edge
when the interpolating filters are in use. In 2×, 4×, and 8×
interpolation modes, the latching edge of DACCLK will be
either every 2

, 4

, or 8

edge, respectively.

With the 2 ns keep out window, as shown in Figure 53, there is
a strong possibility of violating setup and hold times, especially
at high speeds. It is recommended that users sense the DAC
output noise floor for setup and hold violations. If setup and
hold is violated, DCLKPOL can be switched. The effect of
switching the state of DCLKPOL is that the latching edge will
be moved by one, two, or four DACCLK cycles if the AD9786 is
in 2×, 4×, or 8× interpolation modes, respectively.

Note that in this mode, the DATAADJ bits have no effect.

03152-0-045

= 300ps TYP

= 2.9ns TYP

DACCLK

DATA

Figure 53. External Sync Mode with 2

Interpolation

DATAADJUST Synchronization

When designing the digital interface for high speed DACs, care
must be taken to ensure that the DAC input data meets setup
and hold requirements. Often, compensation must be used in
the clock delay path to the digital engine driving the DAC. The
AD9786 has the on-chip capability to vary the latching edge of
DACCLK. With the interpolation function enabled, this allows
the user the choice of multiple edges upon which to latch the
data. For instance, if the AD9786 is using 8× interpolation, the
user may latch from one of eight edges before the rising edge of
DATACLK, or seven edges after this rising edge. The specific
edge upon which data is latched is controlled by SPI Register
05h, Bits 7:4. Table 27 shows the relationship of the latching
edge of DACCLK and DATACLK with the various settings of
the DATAADJ bits.

Table 27. DATAADJ Values for Latching Edge Sync

SPI Reg 05h

Bit 7

Bit 6

Bit 5

Bit 4

Latching Edge wrt DATACLK

0 0 0 0 0
0 0 0 1 +1
0 0 1 0 +2
0 0 1 1 +3
0 1 0 0 +4
0 1 0 1 +5
0 1 1 0 +6
0 1 1 1 +7
1 0 0 0 8
1 0 0 1 7
1 0 1 0 6
1 0 1 1 5
1 1 0 0 4
1 1 0 1 3
1 1 1 0 2
1 1 1 1 1

AD9786

Rev. 0 | Page 31 of 60

Note that the data in Figure 44 to Figure 53 was taken with the
DATAADJ default of 0000. With DCLKPOL = 0, the latching
edge of DACCLK is just previous to the rising edge of
DATACLK; with DCLKPOL = 1, the latching edge of DACCLK
is just previous to the falling edge of DATACLK. Table 27
describes the values available for 8× interpolation which gives a
choice of 16 edges to sync data. With 4× interpolation, there will
be a choice of 8 edges, and the relevant values from Table 27 will
be 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These
options will allow latching edge placement from +3 cycles to
4 cycles. In 2× interpolation, 4 edges will be available, and the
relevant values from Table 27 will be 0000, 0100, 1000, and 1100.
The choices for DATAADJ are diminished to +1 cycle to
2 cycles.

Figure 54, Figure 55, and Figure 56 show the alignment for the
latching edge of DACCLK with 4× interpolation and different
settings for DATAADJ. In Figure 54, the AD9786 is in
DATACLK Master Mode. DATAADJ is set to 0000, with
DCLKPOL set to 0 so that the latching edge of DACCLK is
immediately before the rising edge of DATACLK. The data
transitions shown in Figure 54 are synchronous with the
DACCLK, so that DACCLK and input data are constant with
respect to each other. The only visible change when DATAADJ
is altered is that DATACLK moves, indicating the latching edge
has moved as well. Note that in DATACLK Master Mode, when
DATAADJ is altered, the latching edge with respect to
DATACLK remains the same.

03152-0-006

RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK

DATA TRANSITION

DACCLK
LATCHING EDGE

Figure 54. DATAADJ = 0000

Figure 55 shows the same conditions, but with DATAADJ set to
1111. This moves DATACLK to the left in the plot, indicating
that it occurs one DACCLK cycle before it did in Figure 54. As
explained previously, the latching edge of DACCLK also moves
one cycle back in time.

03152-P

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RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK

DATA TRANSITION

DACCLK

LATCHING EDGE

Figure 55. DATAADJ = 1111

Figure 56 shows the same conditions, with DATAADJ set to
0001, thus moving DATACLK to the right in the plot. This
indicates that it occurs one DACCLK cycle after it did in
Figure 54. In this case, the latching edge of DACCLK moves
forward in time one cycle.

03152-P

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RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK

DATA TRANSITION

DACCLK

LATCHING EDGE

Figure 56. DATAADJ = 0001

AD9786

Rev. 0 | Page 32 of 60

Interpolation Modes

Table 28. Interpolation Modes

INTERP[1] INTERP[0] Mode

0 0 No

Interpolation

0 1 ×2

Interpolation

1 0 ×4

Interpolation

1 1 ×8

Interpolation

Interpolation is the process of increasing the number of points
in a time domain waveform by approximating points between
the input data points, on a uniform time grid. This produces a
higher output data rate. Applied to an interpolation DAC, a
digital interpolation filter is used to approximate the inter-
polated points, having an output data rate increased by the
interpolation factor. Interpolation filter responses are achieved
by cascading individual digital filter banks, whose filter
coefficients are given in Table 23, Table 24, and Table 25. Filter
responses are shown in Figure 57, which shows the interpola-
tion filters of the AD9786 under different interpolation rates,
normalized to the input data rate, f

SIN

The digital filter's frequency domain response exhibits
symmetry about half the output data rate and dc. It will cause
images of the input data to be shaped by the interpolation
filter's frequency response. This has the advantage of causing
input data images, which fall in the stop band of the digital filter
to be rejected by the stop-band attenuation of the interpolation
filter; input data images falling in the interpolation filter's pass
band will be passed. In band-limited applications, the images at
the output of the DAC must be limited by an analog reconstruc-
tion filter. The complexity of the analog reconstruction filter is
determined by the proximity of the closest image to the
required signal band. Higher interpolation rates yield larger
stop-band regions, suppressing more input images and resulting
in a much relaxed analog reconstruction filter.

A DAC shapes its output with a sinc function, having a null at
the sampling frequency of the DAC. The higher the DAC sam-
pling rate compared to the input signal bandwidth, the less the
DAC sinc function will shape the output. The higher the
interpolation rate, the more input data images fall in the
interpolation filter stop band and are rejected; the bandwidth
between passed images is larger with higher interpolation
factors. The sinc function shaping is also reduced with a higher
interpolation factor.

Table 29. Sinc Shaping at Band Edge of Interpolation Filters

Mode

Sinc Shaping
at 0.43f

SIN

(dB)

Bandwidth to First Image

No Interpolation

2.8241

SIN

×2 Interpolation

0.6708

SIN

×4 Interpolation

0.1657

SIN

×8 Interpolation

0.0413

SIN

AD9786

Rev. 0 | Page 33 of 60

150

100

50

150

100

50

150

100

50

150

100

50

NO INTERPOLATION

×4 INTERPOLATION

×2 INTERPOLATION

×8 INTERPOLATION

SINC RESPONSE

SIN

INTERP[1] = 1
INTERP[0] = 1

INTERP[1] = 1
INTERP[0] = 0

INTERP[1] = 0
INTERP[0] = 1

INTERP[1] = 0
INTERP[0] = 0

03152-P

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Figure 57. Interpolation Modes

REAL AND COMPLEX SIGNALS

A complex signal contains both magnitude and phase
information. Given two signals at the same frequency, if a point
in time can be taken such that the signal leading in phase is
cosinusoidal and the lagging signal is sinusoidal, then
information pertaining to the magnitude and phase of a
combination of the two signals can be derived; the combination
of the two signals can be considered a complex signal. The
cosine and sine can be represented as a series of exponentials;
recalling that a multiplication by j is a counterclockwise rotation
about the Re/Im plane, the phasor representation of a complex
signal, with frequency f, can be shown in Figure 58.

A/2

FREQUENCY

C = Ae

= Acos(2

ft) + jAsin(2

ft)

Acos(2

ft) = A

[

+j2

+ e

j2

]

+j2

+ e

j2

Asin(2

ft) = A

[

+j2

+ e

j2

]

+j2

+ e

j2

03152-P

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Figure 58. Complex Phasor Representation

The cosine term represents a signal on the real plane with
mirror symmetry about dc; this is referred to as the real, in-
phase or I component of a complex signal. The sine term
represents a signal on the imaginary plane with mirror
asymmetry about dc; this term is referred to as the imaginary,
quadrature or Q complex signal component.

The AD9786 has two channels of interpolation filters, allowing
both I and Q components to be shaped by the same filter
transfer function. The interpolation filters' frequency response
is a real transfer function. Two DACs are required to represent a
complex signal. A single DAC can only synthesize a real signal.
When a DAC synthesizes a real signal, negative frequency
components fold onto the positive frequency axis. If the input to
the DAC is mirror symmetrical about dc, the folded negative
frequency components fold directly onto the positive frequency
components in phase producing constructive signal summation.
If the input to the DAC is not mirror symmetric about dc,
negative frequency components may not be in phase with
positive frequency components and will cause destructive signal
summation. Different applications may or may not benefit from
either type of signal summation.

AD9786

Rev. 0 | Page 34 of 60

MODULATION MODES

Table 30. Single Channel Modulation

MODDUAL CHANNEL MOD[1] MOD[0] Mode

I Channel, no modulation

I Channel, modulation by f

DAC

I Channel, modulation by f

DAC

I Channel, modulation by f

DAC

0 0 Q

Channel,

modulation

Q Channel, modulation by f

DAC

Q Channel, modulation by f

DAC

Q Channel, modulation by f

DAC

Either channel of the AD9786's interpolation filter channels can
be routed to the DAC and modulated. In single channel
operation the input data may be modulated by a real sinusoid;
the input data and the modulating sinusoid will contain both
positive and negative frequency components. A double side-
band output results when modulating two real signals. At the
DAC output the positive and negative frequency components
will add in phase resulting in constructive signal summation.

As the modulating sinusoidal frequency becomes a larger
fraction of the DAC update rate, f

DAC,

the more the sinc function

of the DAC shapes the modulated signal bandwidth, and the
closer the first image moves. As the AD9786 interpolation
filter's pass band represents a large portion of the input data's
Nyquist band, under certain modulation and interpolation
modes it is possible for modulated signal bands to touch or
overlap images if sufficient interpolation is not used.

Figure 59 shows the effects of f

DAC

/8 modulation when using

8× interpolation.

Figure 60 to Figure 62 show the effects of real modulation
under all interpolation modes. The sinc shaping at the corners
of the modulated signal band, and the bandwidth to the first
image for those cases whose pass bands do not touch or overlap,
are tabulated.

Table 31. Synthesis Bandwidth vs. Interpolation Modes

Interpolation

Modulation

None ×2 ×4 ×8

none f

SIN

DAC

/2 f

SIN

DAC

/4 Overlap Touching

SIN

DAC

/8 Overlap Overlap

Touching

SIN

Table 32. Modulated Pass-Band Edges Sinc Shaping
(Lower/Upper)

Interpolation

Modulation

None

×2 ×4 ×8

None 0 0 0 0

2.8241 0.6708 0.1657 0.0413

DAC

0.0701 1.1932 2.3248 3.0590

22.5378

9.1824 6.1190 4.9337

DAC

Overlap Touching

0.2921 0.5974

1.9096

1.3607

DAC

/8 Overlap

Overlap

Touching

0.0727

0.4614

AD9786

Rev. 0 | Page 35 of 60

DAC

DAC/8

DAC/4

DAC/8

DAC/2

DAC/8

DAC/4

DAC/8

DAC

FILTERED INTERPOLATION IMAGES

/8 MODULATION

DAC

DAC/8

DAC/4

DAC/8

DAC/2

DAC/8

DAC/4

DAC/8

DAC

03152-P

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Figure 59. Double Sideband Modulation

150

100

50

NO INTERPOLATION

×2 INTERPOLATION

SIN

×4 INTERPOLATION

SIN

×8 INTERPOLATION

SIN

INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

150

100

50

150

100

50

150

100

50

03152-P

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Figure 60. Real Modulation by f

DAC

/2 Under All Interpolation Modes

AD9786

Rev. 0 | Page 36 of 60

150

100

50

NO INTERPOLATION

×2 INTERPOLATION

SIN

×4 INTERPOLATION

×8 INTERPOLATION

INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

150

100

50

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

150

100

50

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

150

100

50

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

03215-P

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Figure 61. Real Modulation by f

DAC

/4 Under All Interpolation Modes

150

100

50

NO INTERPOLATION

×2 INTERPOLATION

SIN

×4 INTERPOLATION

SIN

×8 INTERPOLATION

SIN

INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

150

100

50

150

100

50

150

100

50

03152-P

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Figure 62. Real Modulation by f

DAC

/8 Under All Interpolation Modes

AD9786

Rev. 0 | Page 37 of 60

Table 33. Dual Channel Complex Modulation

MODSING REALIMAG MOD[1]

MOD[0]

Mode

Real output, no modulation

Real output, modulation by f

DAC

Real output, modulation f

DAC

Real output, modulation f

DAC

Image output, no modulation

Image output, modulation by f

DAC

Image output, modulation by f

DAC

Image output, modulation by f

DAC

In dual channel mode, the two channels may be modulated by
a complex signal, with either the real or imaginary modulation
result directed to the DAC. Assume initially, as in Figure 63,
that the complex modulating signal is defined for a positive
frequency only. This causes the output spectrum to be trans-
lated in frequency by the modulation factor only. No additional
sidebands are created as a result of the modulation process, and
therefore the bandwidth to the first image from the baseband
bandwidth is the same as the output of the interpolation filters.
Furthermore, pass bands will not overlap or touch. The sinc
shaping at the corners of the modulated signal band are
tabulated in Table 34. Figure 64, Figure 65, and Figure 66 show
the effects of complex modulation with varying interpolation
rates.

Table 34. Complex Modulated Pass-Band Edges Sinc Shaping
(Lower/Upper)

Interpolation

Modulation

None ×2 ×4 ×8

None 0 0 0 0
2.8241

0.6708

0.1657

0.0413

DAC

/2 0.0701

1.1932

2.3248

3.0590

22.5378

9.1824

6.1190

4.9337

DAC

/4 0.4680

0.0175

0.2921

0.5974

6.0630

3.3447

1.9096

1.3607

DAC

/8 1.3723

0.1160

0.0044

0.0727

4.9592

1.7195

0.7866

0.4614

DAC

FILTERED INTERPOLATION IMAGES

/8 MODULATION

NO NEGATIVE
SIDEBAND

DAC

03152-P

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Figure 63. Complex Modulation

AD9786

Rev. 0 | Page 38 of 60

03152-P

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150

100

50

×2INTERPOLATION

×4INTERPOLATION

×8INTERPOLATION

SIN

150

100

50

SIN

150

100

50

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

Figure 64. Complex Modulation by f

DAC

/2 Under All Interpolation Modes

150

100

50

×2 INTERPOLATION

×4 INTERPOLATION

×8 INTERPOLATION

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

150

100

50

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

150

100

50

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

03152-P

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Figure 65. Complex Modulation by f

DAC

/4 Under All Interpolation Modes

150

100

50

×2 INTERPOLATION

×4 INTERPOLATION

×8 INTERPOLATION

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 1

150

100

50

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 1

150

100

50

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 1

03152-P

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Figure 66. Complex Modulation by f

DAC

/8 Under All Interpolation Modes

AD9786

Rev. 0 | Page 39 of 60

POWER DISSIPATION

The AD9786 has seven power supply domains: two 3.3 V analog
domains (AVDD1 and AVDD2), two 2.5 V analog domains
(ADVDD and ACVDD), one 2.5 V clock domain (CLKVDD),
and two digital domains (DVDD, which runs from 2.5 V, and
DRVDD, which can run from 2.5 V or 3.3 V).

The current needed for the 3.3 V analog supplies, AVDD1 and
AVDD2, is consistent across speed and varying modes of the
AD9786. Nominally, the current for AVDD1 is 29 mA across
all speeds and modes, while the current for AVDD2 is 20 mA.

The current for the 2.5 V analog supplies and the digital
supplies varies depending on speed and mode of operation.
Figure 67, Figure 68, and Figure 69 show this variation. Note
that CLKVDD, ADVDD, and ACVDD vary with clock speed
and interpolation rate, but not with modulation rate.

03152-P

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DATA

(MSPS)

250

100

125

150

175

200

225

IDV

DD (mA)

425

325
300
275
250
225
200
175

400
375
350

150
125
100

75
50
25

1×

2×

2× fs/4

2× fs/8

4×

4× fs/4

4× fs/8

8×

8× fs/4

8× fs/8

Figure 67. DVDD Supply Current vs. Clock Speed, Interpolation, and

Modulation Rates

03152-P

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DATA

(MSPS)

250

100

125

150

175

200

225

IDV

DD (mA)

2×

1×

4×

8×

Figure 68. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates

03152-P

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DATA

(MSPS)

250

100

125

150

175

200

225

IDV

DD (mA)

2×

1×

4×

8×

Figure 69. ADVDD and ACVDD Supply Current vs. Clock Speed and

Interpolation Rates

AD9786

Rev. 0 | Page 40 of 60

FILTERED INTERPOLATION IMAGES

/8 MODULATION

/4 MODULATION

DAC

03152-P

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D-022

Figure 70. Complex Modulation with Negative Frequency Aliasing

Table 35. Dual Channel Complex Modulation with Hilbert

Hilbert Mode

Hilbert transform off

Hilbert transform on

When complex modulation is performed, the entire spectrum is
translated by the modulation factor. If the resulting modulated
spectrum is not mirror symmetric about dc, when the DAC
synthesizes the modulated signal, negative frequency compo-
nents will fall on the positive frequency axis and can cause
destructive summation of the signals, as shown in Figure 70. For
some applications, this can distort the modulated output signal.

A/2

X = Ae

(f + fm)t

Y = Ae

(f + fm)t 

Z = HILBERT(Y)

C = X Z

03152-P

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D-023

Figure 71. Negative Frequency Image Rejection

Referring to Figure 71, by performing a second complex
modulation with a modulating signal having a fixed /2 phase
difference, Figure (Y), relative to the original complex
modulation signal, Figure (X), taking the Hilbert transform of
the new resulting complex modulation, and subtracting it from

the original complex modulation output all negative frequency
components can be folded in phase to the positive frequency
axis before being synthesized by the DAC. When the DAC
synthesizes the modulated output there are no negative
frequency components to fold onto the positive frequency axis
out of phase; consequently no distortion is produced as a result
of the modulation process.

03152-P

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D-024

ALIASED NEGATIVE FREQUENCY INTERPOLATION IMAGES

0.5

0.5 0.4 0.3 0.2 0.1

0.1

0.2

0.3

0.4

dBFS

150

50

100

Figure 72. Negative Frequency Aliasing Distortion

Figure 72 shows this effect at the DAC output for a mirror
asymmetric signal about dc produced by complex modulation
without a Hilbert transform. The signal bandwidth was nar-
rowed to show the aliased negative frequency interpolation
images.

AD9786

Rev. 0 | Page 41 of 60

In contrast, Figure 73 shows the same waveform with the
Hilbert transform applied. Clearly, the aliased interpolation
images are not present.

03152-P

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D-025

0.5

0.5 0.4 0.3 0.2 0.1

0.1

0.2

0.3

0.4

dBFS

150

50

100

Figure 73. Effects of Hilbert Transform

If the output of the AD9786 is to be used with a quadrature
modulator, negative frequency images are cancelled without the
need of a Hilbert transform.

HILBERT TRANSFORM IMPLEMENTATION

The Hilbert transform on the AD9786 is implemented as a
19-coefficient FIR. The coefficients are given in Table 36.

Table 36.

Coefficient Integer

Value

H(1) 6
H(2) 0
H(3) 17
H(4) 0
H(5) 40
H(6) 0
H(7) 91
H(8) 0
H(9) 318
H(10) 0
H(11) 318
H(12) 0
H(13) 91
H(14) 0
H(15) 40
H(16) 0
H(17) 17
H(18) 0
H(19) 6

The transfer function of an ideal Hilbert transform has a +90°
phase shift for negative frequencies, and a 90° phase shift for
positive frequencies. Because of the discontinuities that occur at
0 Hz and at 0.5 × Sample Rate, any real implementation of the
Hilbert Transform trades off bandwidth versus ripple.

Figure 74 and Figure 75 show the gain of the Hilbert transform
versus frequency. Gain is essentially flat, with a pass-band ripple
of 0.1 dB over the frequency range 0.07 × Sample Rate to
0.43 × Sample Rate.

Figure 76 shows the phase response of the Hilbert transform
implemented in the AD9786. The phase response for positive
frequencies begins at 90° at 0 Hz, followed by a linear phase
response (pure time delay) equal to nine filter taps (nine
DACCLK cycles). For negative frequencies, the phase response
at 0 Hz is +90°, again followed by a linear phase delay of nine
filter taps. To compensate for the unwanted 9-cycle delay, an
equal delay of nine taps is used in the AD9786 digital signal
path opposite to the Hilbert transform. This delay block is
noted as t on the block diagram on the first page of this data
sheet.

03152-P

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D-074

1000

100

200

300

400

500

600

700

800

900

100

20

60

40

30

70

80

90

10

50

Figure 74. Hilbert Transform Gain

03152-P

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D-075

1000

100

200

300

400

500

600

700

800

900

1.0

0.4

0.8

0.2

0.6

0.8

0.6

0.2

Figure 75. Hilbert Transform Ripple

AD9786

Rev. 0 | Page 42 of 60

03152-P

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D-076

1200

100

200

400

600

800

1000

Figure 76. Phase Response of Hilbert Transform

Table 37. Dual Channel Complex Modulation Sideband
Selection

Sideband Mode

Lower IF sideband rejected

Upper IF sideband rejected

AD9786

Im()

Re()

03152-P

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D-026

Figure 77. AD9786 Driving Quadrature Modulator

The AD9786 can be configured to drive a quadrature modula-
tor representatively, as in Figure 77. Where two AD9786s are
used with one AD9786 producing the real output, the second
AD9786 produces the imaginary output. By configuring the
AD9786 as a complex modulator coupled to a quadrature
modulator, IF image rejection is possible. The quadrature
modulator acts as the real part of a complex modulation pro-
ducing a double sideband spectrum at the local oscillator (LO)
frequency, with mirror symmetry about dc.

A baseband double sideband signal modulated to IF increases
IF filter complexity and reduces power efficiency. If the base-
band signal is complex, a single sideband IF modulation can be
used, relaxing IF filter complexity and increasing power
efficiency.

The AD9786 has the ability to place the baseband single side-
band complex signal either above the IF frequency or below it.
Figure 78, Figure 79, and Figure 80 illustrate this.

03152-P

r
D-027

0.5

0.5 0.4 0.3 0.2 0.1

0.1

0.2

0.3

0.4

dBFS

150

50

100

Figure 78. Upper IF Sideband Rejected

03152-P

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D-028

0.5

0.5 0.4 0.3 0.2 0.1

0.1

0.2

0.3

0.4

dBFS

150

50

100

Figure 79. Lower IF Sideband Rejected

BASEBAND

SIDEBAND = 0

SIDEBAND = 1

03152-

r
D-

029

Figure 80. IF Quadrature Modulation of Real and Complex Baseband Signals

AD9786

Rev. 0 | Page 43 of 60

Master/Slave, Modulator/DATACLK Master Modes

In applications where two or more AD9786s are used to syn-
thesize several digital data paths, it may be necessary to ensure
that the digital inputs to each device are latched synchronously.
In complex data processing applications, digital modulator
phase alignment may be required between two AD9786s. In
order to allow data synchronization and phase alignment, only
one AD9786 should be configured as a master device, providing
a reference clock for another slave-configured AD9786.

With synchronization enabled, a reference clock signal is
generated on the DATACLK pin of the master. The DATACLK
pins on the slave devices act as inputs for the reference clock
generated by the master. The DATACLK pin on the master and
all slaves must be directly connected. All master and slave
devices must have the same clock source connected to their
respective CLK+/CLK pins.

When configured as a master, the reference clock generated may
take one of two forms. In modulator master mode, the reference
clock will be a square wave with a period equal to 16 cycles of
the DAC update clock. Internal to the AD9786 is a 16-state
finite state machine, running at the DAC update rate. This state
machine generates all internal and external synchronization
clocks and modulator phasings. The rising edge of the master
reference clock is time aligned to the internal state machine's
state zero. Slave devices use the master's reference clock to
synchronize their data latching and align their modulator's
phase by aligning their local state machine state zero to the
master.

The second master mode, DATACLK master mode, generates a
reference clock that is at the channel data rate. In this mode, the
slave devices align their internal channel data rate clock to the
master. If modulator phase alignment is needed, a concurrent
serial write to all slave devices is necessary. To achieve this, the
CSB pin on all slaves must be connected together and a group
serial write to the MODADJ register bits must be performed;
the modulator coefficient alignment is updated on the next
rising edge of the internal state machine following a successful
serial write, see Figure 81. Modulator master mode does not
need a concurrent serial write as slaves lock to the master phase
automatically.

In a slave device, the local channel data rate clock and the digital
modulator clock are created from the internal state machine.
The local channel data rate clock is used by the slave to latch
digital input data. At high data rates, the delay inherent in the
signal path from master to slave may cause the slave to lag the
master when acquiring synchronization. To account for this, an
integer number of the DAC update clock cycles may be
programmed into the slave device as an offset. The value in
DATADJ allows the local channel data rate clock in the slave
device to advance by up to eight cycles of the DAC clock or to
be delayed by up to seven cycles, see Figure 84.

The digital modulator coefficients are updated at the DAC clock
rate and decoded in sequential order from the state machine
according to Figure 83. The MODADJ bits can be used to align
a different coefficient to the finite state machine's zero state as
shown in Figure 84.

DAC

CLOCK

STATE

MACHINE

STATE MACHINE

CHANNEL DATA

CYCLE CLOCK

RATE CLOCK

MODULATOR

COEFFICIENT

MODADJ

000

10 11 12 13 14 15

03152-P

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D-030

Figure 81. Synchronous Serial Modulator Phase Alignment

AD9786

Rev. 0 | Page 45 of 60

OPERATING THE AD9786 REV F EVALUATION BOARD

This section helps the user get started with the AD9786
evaluation board. Because it is intended to provide starter
information to power up the board and verify correct operation,
a description of some of the more advanced modes of operation
has been omitted.

POWER SUPPLIES

The AD9786 Rev F Evaluation Board has five power supply
connectors, labeled AVDD1, AVDD2, (ACVDD, ADVDD),
CLKVDD, and DVDD. The AD9786 itself actually has seven
power supply domains. To reconcile the power supply domains
on the chip with the power supply connectors on the evaluation
board, use Table 38.

Additionally, the DRVDD power supply on the AD9786 is used
to supply power for the digital input bus. DRVDD can be run
from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper
selectable by JP1, just to the left of the chip on the evaluation
board. With the jumper set to the 3.3 V position, DRVDD chip
receives its power from VDD3IN. With the jumper set to the
2.5 V position, DRVDD receives its power from AVDIN.

PECL CLOCK DRIVER

The AD9786 system clock is driven from an external source via
connector S1. The AD9786 Evaluation Board includes an
OnSemiconductor MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CLKVDD power connector,
or 3.3 V from the VDD3IN power connector. This setting is
done via jumper, JP2, situated next to the CLKVDD power
connector, and by setting input bias resistors R23 and R4 on the
evaluation board. The factory default is for the PECL driver to
be powered from CLKVDD at 2.5 V (R23 = 90.9 , R4 =
115 ). To operate the PECL driver with a 3.3 V supply, R23
must be replaced with a 115 resistor and R4 must be replaced
with a 90.9 resistor, as well as changing the position of JP2.
The schematic of the PECL driver section of the evaluation
board is shown in Figure 85. A low jitter sine wave should be
used as the clock source. Care must be taken to make sure the
clock amplitude does not exceed the power supply rails for the
PECL driver.

03152-P

r
D-080

COND;5

CLKVDDS;8

C32

0.1

R23
115

R4
90.9

ACLKX

CLKVDDS

R5
50

R6
50

CLKVDDS

MC100EPT22

CLK+

CLK

Figure 85. PECL Driver on AD9786 Rev E Evaluation Board

Table 38.

Evaluation Board Label/
PS Domain on Chip

Nominal Power
Supply Voltage (V)

Description

DVDD 2.5

SPI

port

CLKVDD 2.5

Clock

circuitry

(ACVDD ADVDD)

2.5

Analog circuitry containing clock and digital interface circuitry

AVDD2

3.3

Switching analog circuitry

AVDD1

3.3

Analog output circuitry

AD9786

Rev. 0 | Page 46 of 60

DATA INPUTS

Digital data inputs to the AD9786 are accessed on the
evaluation board through connectors J1 and J2. These are 40 pin
right angle connectors that are intended to be used with
standard ribbon cable connectors. The input levels should be
either 3.3 V or 2.5 V CMOS, depending on the setting of the
DRVDD jumper JP1. The data format is selectable through
Register 02h, Bit 7 (DATAFMT). With this bit set to a default 0,
the AD9786 assumes that the input data is in twos complement
format. With this bit set to 1, data should be input in offset
binary format.

When the evaluation board is first powered up and the clock
and data are running, it is recommended that the proper
operating current is verified. Depress reset switch SW1 to
ensure that the AD9786 is in the default mode. The default
mode for the AD9786 is for the interpolation set to 1×. The
modulator is turned off in the default mode. The nominal
operating currents for the evaluation board in the power-up
default mode are shown in Table 39.

SERIAL PORT

SW1 is a hard reset switch that sets the AD9786 to its default
state. It should be used every time the AD9786 power supply is
cycled or the clock is interrupted, or if new data is to be written
via the SPI port. Set the SPI software to read back data from the
AD9786 and verify that when the software is run, the expected
values are read back.

Table 39. Nominal Operating Currents in Power-Up Default Mode

Nominal Current @ Speed (mA)

Evaluation Board Power Supply

50 MSPS

100 MSPS

150 MSPS

200 MSPS

DVDD

49 74 99

CLKVDD

83 87 92

ACVDD and ADVDD

AVDD1

30 30 30

AVDD2

27 27 27

Table 40. SPI Registers

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 0

01h INTERP[1]

INTERP[0]

AD9786

Rev. 0 | Page 47 of 60

ANALOG OUTPUT

The analog output of the AD9786 is accessed via connector S3.
Once all settings are selected and current levels and SPI port
functionality are verified, the analog signal at S3 can be viewed.
For most of the AD9786's applications, a spectrum analyzer is
the instrument of choice to verify proper performance. A typical
spectral plot is shown in Figure 86, with the AD9786 synthesiz-
ing a two-tone signal in the default mode with a 200 MSPS
sample rate. A single tone CW signal should provide output
power of approximately +0.5 dBm to the spectrum analyzer.

If the spectrum does not look correct at this point, the data
input may be violating setup and hold times with respect to the
input clock. To correct this, the user should vary the input data
timing. If this is not possible, SPI Register 02h, Bit 4
(DCLKPOL) can be inverted. This bit controls the clock edge
upon which the data is latched. If these methods do not correct
the spectrum, it is unlikely that the issue is timing related. This
note should then be reread to verify that all instructions have
been followed.

03152-0-025

STOP 200MHz

START 100MHz

19.9MHz/

20

10

40

30

60

50

80

70

100

90

110

120

1MA

0dBm

MARKER 1 [T1]

193.00170300MHz

84.96dBm

VBW

SWT

RBW

30kHz

560ms

30kHz

UNIT

RF ATT

dBm

20dB

REF LVL

1AVG

Figure 86. Typical Spectral Plot

AD9786

Rev. 0 | Page 48 of 60

S11

CGND;3,4,5

AGND2; 3,4,5

DGND; 3,4,5

JP8

JP6

AVDD_IN

ADVDD2_IN

DVDD_IN

TP18

BLK

TP30

TP31

TP32

TP33

TP34

BLK

TP36

C28

4.7

6.3V

C75

0.1

JP33

CGND; 5

CLKVDDS; 8

CLKVDDS

C35

0.1

JP30

C47

0.1

ADVDD

ACVDD

C76

0.1

C46

16V

C45

16V

C64

16V

C68

0.1

C63

16V

CLKVDDS; 8

CGND; 5

FERRITE

TP13

RED

FERRITE

L11

FERRITE

L12

FERRITE

TP1

RED

TP12

BLK

TP2

RED

TP3

BLK

FERRITE

TP6

RED

TP5

BLK

C69

0.1

TP16

BLK

C48

0.1

AVD3

FERRITE

TP4

RED

AVD1

AVDD

FERRITE

C65

16V

ACLKX

FERRITE

CLKVDDS

C34

0.1

CLKVDDS

JP10

CVD

CLKVDD

JP5

JP36

TP7

BLK

ADVDD3_IN

C67

0.1

C29

16V

R23

90.9

TP35

JP34

DVDD

VDD

AVD2

JP9

AVDD2

L13

VAL

L10

VAL

L14

VAL

JP7

CLKVDD_IN

TP17

BLK

CLK+

CLK

DVDDS

DVDD

AVDD2

DRVDD

SMAEDGE

AGND; 3,4,5

MC100EPT22

S10

JP1

JP2

115

C32

0.1

MC100EPT22

POWER INPUT FILTERS

2.5VQ

3.3VQ

3.3V

2.5VN

2.5V

03152-

007

Figure 87. Power Supply Distribution Rev F Evaluation Board

AD9786

Rev. 0 | Page 49 of 60

03152-0-008

SPC

BD0

SPC

SPSD

6.3V

0.001

0.1

BD0

ESET

1
1

1
0

CLK+

CLK

CLKCO

CLKV

DD1

CLKV

DD2

DCLK-P

LLL

DCO

DRV

DD1

DD2

DD3

DD4

P1B

0
L

P1B

1
0

P1B

1
1

P1B

1
2

P1B

1
3

P1B

1
4

P1B

15M

P1B

P2B

1
0

P2B

1
1

P2B

1
2

P2B

1
3

P2B

14-

OPC

P2B

15M

-
I
QSEL

P2B

ACCO

ACO

1
1

ACO

1
2

ACO

2
1

ACO

ACV

DDP

ACV

DDP

ADCO

ADV

DDP

ADV

DDP

DD1

DD2

DCO

DNC1

DD5

DD6

ADJ

IOU

P2B

0
L

P2B

ESET

SP-

SPI_C

DNC2

AD9786BTSP

6.3V

0.001

0.1

SW1

ESET

DRV

FLOAT; 5

0.001

0.1

0.001

0.1

DD2

0.1

0.001

0.1

10V

0.01%

0.1

6.3V

0.1

6.3V

ACV

ADTL1-1

ADV

49.9

NC = 5

TTW

B-1

-
B

49.9

2
9

BLK

0.1

6.3V

0.1

0.001

6.3V

0.1

BD0

BD1

AD0

AD1

0.001

6.3V

0.1

CLKV

CLK

CLK+

-1

ND; 3

,
4
,
5

ACLKX

1
5

10k

0.1

10k

0.001

0.1

6.3V

DRV

0.001

6.3V

0.1

0.001

6.3V

0.1

1
4

BD1

CLK_

DATACLK

OPC

BD1

JP27

JP28

JP23

JP22

ND; 3

,
4
,
5

ND; 3

,
4
,
5

ND; 3

,
4
,
5

ND; 3

,
4
,
5

Figure 88. AD9786 Local Circuitry Rev F Evaluation Board

AD9786

Rev. 0 | Page 50 of 60

03152-0-009

R43

100

R44

100

R41

100

R46

100

R39

100

R38

100

R40

100

R34

100

R31

100

R30

100

R32

100

R33

100

R27

100

R26

100

R28

100

R29

100

DATA-A

RIBBON

AX07

AX06

AX05

AX04

AX15

AX14

AX13

AX12

AX00

AX01

AX02

AX03

AX08

AX09

AX10

AX11

JP21

JP19

9 10

R1 R2 R3 R4 R5 R6 R7 R8 R9

9 10

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

RP8

DNP

RP6

DNP

9 10

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

RP7

DNP

RP5

DNP

AD15

AD14

AD13

AD12

AD11

AD10

AD09

AD08

AD07

AD06

AD05

AD04

AD03

AD02

AD01

AD00

AX15

AX14

AX13

AX12

AX11

AX10

AX09

AX08

AX07

AX06

AX05

AX04

AX03

AX02

AX01

AX00

RP1 22

RP2 22

JP3

JP12

Figure 89. Digital Data Port A Input Terminations Rev F Evaluation Boards

AD9786

Rev. 0 | Page 51 of 60

03152-0-010

R49

100

R51

100

R47

100

R52

100

R54

100

R55

100

R53

100

R56

100

R58

100

R57

100

R59

100

R63

100

R61

100

R62

100

R60

100

R64

100

DATA-B

RIBBON

BX07

BX06

BX05

BX04

BX15

BX14

BX13

BX12

BX00

BX01

BX02

BX03

BX08

BX09

BX10

BX11

JP25

JP24

9 10

R1 R2 R3 R4 R5 R6 R7 R8 R9

9 10

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

RP10

DNP

RP11

DNP

9 10

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

RP9

DNP

RP12

DNP

BD15

BD14

BD13

BD12

BD11

BD10

BD09

BD08

BD07

BD06

BD05

BD04

BD03

BD02

BD01

BD00

BX15

BX14

BX13

BX12

BX11

BX10

BX09

BX08

BX07

BX06

BX05

BX04

BX03

BX02

BX01

BX00

SDO

CLK

SDI

CSB

RP3 22

RP4 22

JP26

JP31

Figure 90. Digital Data Port B Input Terminations Rev F Evaluation Board

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