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REV. 0
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
ADP3333
High Accuracy Ultralow I
Q
, 300 mA,
anyCAP
Low Dropout Regulator
FUNCTIONAL BLOCK DIAGRAM
THERMAL
PROTECTION
CC
IN
ADP3333
OUT
GND
Q1
BANDGAP
REF
DRIVER
g
m
SD
R1
R2
FEATURES
High Accuracy Over Line and Load: 0.8% @ 25 C,
1.8% Over Temperature
Ultralow Dropout Voltage: 230 mV (Max) @ 300 mA
Requires Only C
O
= 1.0 F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1 A
2.6 V to 12 V Supply Range
40 C to +85 C Ambient Temperature Range
Ultrasmall 8-Lead MSOP Package
APPLICATIONS
Cellular Phones
PCMCIA Cards
Personal Digital Assistants (PDAs)
DSP/ASIC Supplies
GENERAL DESCRIPTION
ADP3333 is a member of the ADP333x family of precision low
dropout anyCAP voltage regulators. Pin-compatible with the
MAX8860, the ADP3333 operates with a wider input voltage
range of 2.6 V to 12 V and delivers a load current up to 300 mA.
ADP3333 stands out from other conventional LDOs with a
novel architecture and an enhanced process that enables it to
offer performance advantages over its competition. Its patented
design requires only a 1.0
F output capacitor for stability. This
device is insensitive to output capacitor Equivalent Series Resis-
tance (ESR), and is stable with any good quality capacitor,
including ceramic (MLCC) types for space-restricted applica-
tions. ADP3333 achieves exceptional accuracy of
0.8% at
room temperature and
1.8% over temperature, line and load
variations. The dropout voltage of ADP3333 is only 140 mV
(typical) at 300 mA. This device also includes a safety current
limit, thermal overload protection and a shutdown feature. In
shutdown mode, the ground current is reduced to less than
1
A. The ADP3333 has ultralow quiescent current, 70
A (typ)
in light load situations.
ADP3333
NC
V
IN
I N
GND
V
OUT
ON
OFF
OUT
SD
C
IN
1 F
C
OUT
1 F
NC = NO CONNECT
Figure 1. Typical Application Circuit
anyCAP is a registered trademark of Analog Devices, Inc.
REV. 0
2
ADP3333SPECIFICATIONS
1
(V
IN
= 6.0 V, C
IN
= C
OUT
= 1.0 F, T
J
= 40 C to +125 C, unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
OUTPUT
Voltage Accuracy
2
V
OUT
V
IN
= V
OUTNOM
0.3 V to 12 V
0.8
0.8
%
I
L
= 0.1 mA to 300 mA
T
J
= 25
C
V
IN
= V
OUTNOM
0.3 V to 12 V
1.8
+1.8
%
I
L
= 0.1 mA to 300 mA
Line Regulation
2
V
IN
= V
OUTNOM
0.3 V to 12 V
0.04
mV/V
T
J
= 25
C
Load Regulation
I
L
= 0.1 mA to 300 mA
0.04
mV/mA
T
J
= 25
C
Dropout Voltage
V
DROP
V
OUT
= 98% of V
OUTNOM
I
L
= 300 mA
140
230
mV
I
L
= 200 mA
105
185
mV
I
L
= 0.1 mA
30
mV
Peak Load Current
I
LDPK
V
IN
= V
OUTNOM
+ 1 V
600
mA
Output Noise
V
NOISE
f = 10 Hz100 kHz, C
L
= 10
F
45
V rms
I
L
= 300 mA
GROUND CURRENT
In Regulation
I
GND
I
L
= 300 mA
2.0
5.5
mA
I
L
= 300 mA, T
J
= 25
C
2.0
4.3
mA
I
L
= 300 mA, T
J
= 85
C
1.5
3.3
mA
I
L
= 200 mA
1.4
mA
I
L
= 10 mA
200
275
A
I
L
= 0.1 mA
70
100
A
In Dropout
I
GND
V
IN
= V
OUTNOM
100 mV
70
190
A
I
L
= 0.1 mA,
V
IN
= V
OUTNOM
100 mV
70
160
A
I
L
= 0.1 mA, T
J
= 0
C to 125
C
In Shutdown
I
GNDSD
SD = 0 V, V
IN
= 12 V
0.01
1
A
SHUTDOWN
Threshold Voltage
V
THSD
ON
2.0
V
OFF
0.4
V
SD Input Current
I
SD
0
SD
12 V
0.85
7
A
0
SD
5 V
0.8
4.5
A
Output Current In Shutdown
I
OSD
T
J
= 25
C V
IN
= 12 V
0.01
1
A
T
J
= 125
C V
IN
= 12 V
0.01
1
A
NOTES
1
Application stable with no load.
2
V
IN
= 2.6 V for models with V
OUTNOM
2.3 V.
Specifications subject to change without notice.
REV. 0
ADP3333
3
ORDERING GUIDE
Output
Package
Branding
Model
Voltage
Option
Information
ADP3333ARM-1.5
1.5 V
RM-8
LKA
(MSOP-8)
ADP3333ARM-1.8
1.8 V
RM-8
LKB
(MSOP-8)
ADP3333ARM-2.5
2.5 V
RM-8
LKC
(MSOP-8)
ADP3333ARM-2.77
2.77 V
RM-8
LKD
(MSOP-8)
ADP3333ARM-3
3 V
RM-8
LKE
(MSOP-8)
ADP3333ARM-3.15
3.15 V
RM-8
LKF
(MSOP-8)
ADP3333ARM-3.3
3.3 V
RM-8
LKG
(MSOP-8)
ADP3333ARM-5
5 V
RM-8
LKH
(MSOP-8)
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic Function
1
OUT
Output of the Regulator. Bypass to ground
with a 1.0
F or larger capacitor.
2
IN
Input pin. Bypass to ground with a 1.0
F
or larger capacitor.
3
GND
Ground Pin
46, 8 NC
No Connect
7
SD
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, his pin should
be connected to the input pin
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3333 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
GND
IN
OUT
NC
*
SD
NC
ADP3333
NC
NC
NC = NO CONNECT
*
CAN BE CONNECTED
TO ANY OTHER PIN.
ABSOLUTE MAXIMUM RATINGS
*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . 0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . 0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . 40
C to +85
C
Operating Junction Temperature Range . . . 40
C to +125
C
JA
(4-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
C/W
JA
(2-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C/W
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
REV. 0
ADP3333
4
INPUT VOLTAGE V
OUTPUT VOLTAGE V
2.502
3
4
12
6
8
10
V
OUT
= 2.5V
200mA
100mA
300mA
11
9
7
5
2.500
2.498
2.496
2.494
2.492
2.490
2.488
0mA
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
OUTPUT LOAD mA
GROUND CURRENT
mA
0
300
V
IN
= 6V
0
0.5
1.0
1.5
2.0
2.5
50
100
150
200
250
TPC 4. Ground Current vs.
Load Current
OUTPUT LOAD mA
INPUT/OUTPUT VOLTAGE
mV
0
0
50
250
100
150
200
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
300
TPC 7. Dropout Voltage vs.
Output Current
OUTPUT LOAD mA
OUTPUT VOLTAGE
V
2.502
2.500
0
100
150
300
250
2.494
2.492
2.490
2.488
2.498
2.496
V
IN
= 6V
V
OUT
= 2.5V
50
200
TPC 2. Output Voltage vs. Load
Current
JUNCTION TEMPERATURE C
OUTPUT CHANGE
%
1.0
0.5
50
25
0
25
50
75
100
0.6
0.9
0.8
0.7
125
0.0
0.2
0.1
0.4
0.3
0.2
0.3
0.1
0.4
300mA
0
200mA
0
TPC 5. Output Voltage Variation % vs.
Junction Temperature
TIME Sec
1
2
3
4
3.0
2.5
2.0
1.5
1.0
0.5
0
INPUT/OUTPUT VOLTAGE
V
V
OUT
= 2.5V
SD
= V
IN
R
L
= 8.3
TPC 8. Power-Up/Power-Down
INPUT VOLTAGE Volts
GROUND CURRENT
A
140
60
0
0
12
2
4
6
8
10
120
100
40
20
80
V
OUT
= 2.5V
I
L
= 100 A
I
L
= 0
TPC 3. Ground Current vs. Supply
Voltage
JUNCTION TEMPERATURE C
GROUND CURRENT
mA
0.5
0
I
L
= 300mA
V
IN
= 6V
I
L
= 200mA
I
L
= 100mA
I
L
= 0mA
1.0
1.5
2.0
2.5
3.0
3.5
50
25
0
25
50
75
100
125
TPC 6. Ground Current vs.
Junction Temperature
TIME s
200
400
600
800
3
2
1
0
4
2
0
V
IN
V
V
OUT
V
V
OUT
= 2.5V
SD
= V
IN
R
L
= 8.3
C
OUT
= 10 F
C
OUT
= 1 F
TPC 9. Power-Up Response
Typical Performance Characteristics
REV. 0
5
ADP3333
V
OUT
= 2.5V
R
L
= 8.3
C
L
= 1 F
TIME s
3.00
3.50
2.49
2.50
2.51
40
80
140
180
V
IN
V
V
OUT
V
2.52
TPC 10. Line Transient Response
TIME s
10
300
2.4
2.5
2.6
200
400
600
800
mA V
o
lts
V
IN
= 4V
V
OUT
= 2.5V
C
L
= 10 F
2.7
TPC 13. Load Transient Response
FREQUENCY Hz
RIPPLE REJECTION
dB
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
C
L
= 1 F
I
L
= 500mA
C
L
= 1 F
I
L
= 50 A
C
L
= 10 F
I
L
= 500mA
C
L
= 10 F
I
L
= 50 A
V
OUT
= 2.2V
TPC 16. Power Supply Ripple
Rejection
V
OUT
= 2.5V
R
L
= 8.3
C
L
= 10 F
TIME s
3.00
3.50
2.49
2.50
2.51
40
80
140
180
V
IN
V
V
OUT
V
2.52
TPC 11. Line Transient Response
TIME s
0
1
2
2.5
200
400
600
800
A V
o
lts
V
IN
= 6V
3
V
IN
= 6V
0
TPC 14. Short Circuit Current
C
L
F
RMS NOISE
V
0
10
0mA
0
20
40
60
80
120
20
30
40
50
100
300mA
TPC 17. RMS Noise vs. C
L
(10 Hz100 kHz)
V
IN
= 4V
V
OUT
= 2.5V
C
L
= 1 F
TIME s
200
400
600
800
10
2.4
2.5
2.6
mA V
o
lts
300
2.7
TPC 12. Load Transient Response
TIME s
0
0
2
1
2
200
400
600
800
V
SD
V
OUT
1 F
1 F
10 F
10 F
V
IN
= 6V
V
OUT
= 2.5V
R
L
= 8.3
3
TPC 15. Turn ON-Turn OFF
Response
FREQUENCY Hz
100
10
100
1M
1k
10k
100k
10
1
0.1
0.01
0.001
V
OUT
= 2.5V
I
L
= 1mA
C
L
= 1 F
C
L
= 10 F
VOLTAGE NOISE SPECTRAL
DENSITY
V/
Hz
TPC 18. Output Noise Density
REV. 0
ADP3333
6
THEORY OF OPERATION
The new anyCAP LDO ADP3333 uses a single control loop for
regulation and reference functions see (Figure 2). The output
voltage is sensed by a resistive voltage divider consisting of R1
and R2 which is varied to provide the available output voltage
option. Feedback is taken from this network by way of a series
diode (D1) and a second resistor divider (R3 and R4) to the
input of an amplifier.
PTAT
V
OS
NONINVERTING
WIDEBAND
DRIVER
INPUT
Q1
ADP3333
COMPENSATION
CAPACITOR
ATTENUATION
(V
BANDGA P
/V
OUT
)
R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
(a)
C
LOAD
R
LOAD
FB
GND
g
m
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it pro-
duces a large, temperature-proportional input "offset voltage" that
is repeatable and very well controlled. The temperature propor-
tional offset voltage is combined with the complementary diode
voltage to form a "virtual bandgap" voltage, implicit in the network,
although it never appears explicitly in the circuit. Ultimately, this
patented design makes it possible to control the loop with only one
amplifier. This technique also improves the noise characteristics
of the amplifier by providing more flexibility on the trade-off of
noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the load-
ing of the divider so that the error resulting from base current
loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to include
the load capacitor in a pole splitting arrangement to achieve
reduced sensitivity to the value, type and ESR of the load
capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover,
the ESR value, required to keep conventional LDOs stable, changes
depending on load and temperature. These ESR limitations make
designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
With the ADP3333 anyCAP LDO, this is no longer true. It can be
used with virtually any good quality capacitor, with no constraint
on the minimum ESR. This innovative design allows the circuit to
be stable with just a small 1
F capacitor on the output. Additional
advantages of the pole splitting scheme include superior line noise
rejection and very high regulator gain which leads to excellent line
and load regulation. An impressive
1.8% accuracy is guaranteed
over line, load and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown.
APPLICATION INFORMATION
Capacitor Selection
Output Capacitor
The stability and transient response of the LDO is a function of
the output capacitor. The ADP3333 is stable with a wide range
of capacitor values, types and ESR (anyCAP). A capacitor as
low as 1.0
F is all that is needed for stability; larger capacitors
can be used if high current surges on the output are anticipated.
The ADP3333 is stable with extremely low ESR capacitors
(ESR 0), such as Multilayer Ceramic Capacitors (MLCC) or
OSCON. Note that the effective capacitance of some capacitor
types fall below the minimum over temperature or with dc voltage.
Ensure that the capacitor provides at least 1.0
F of capacitance
over temperature and dc bias.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but it is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1.0
F capacitor from the input
to ground reduces the circuit's sensitivity to PC board layout and
input transients. If a larger output capacitor is necessary then a
larger value input capacitor is also recommended.
Output Current Limit
The ADP3333 is short circuit protected by limiting the pass
transistor's base drive current. The maximum output current is
limited to about 1 A. See TPC 14.
Thermal Overload Protection
The ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 165
C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where the die temperature starts to rise above
165
C, the output current will be reduced until the die tempera-
ture has dropped to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device's power dissipation should be externally
limited so that the junction temperature will not exceed 125
C.
REV. 0
ADP3333
7
Calculating Junction Temperature
Device power dissipation is calculated as follows:
P
V
V
I
V
I
D
IN
OUT
LOAD
IN
GND
=
-
(
)
+
( )
Where I
LOAD
and I
GND
are load current and ground current, V
IN
and V
OUT
are the input and output voltages respectively.
Assuming the worst-case operating conditions are I
LOAD
=
300 mA, I
GND
= 2.6 mA, V
IN
= 4.0 V and V
OUT
= 3.0 V, the
device power dissipation is:
P
V
V
mA
V
mA
mW
D
=
-
(
)
+
(
)
=
4 0
3 0
300
4 2
2 0
308
.
.
.
.
The package used on the ADP3333 has a thermal resistance of
158
C/W for 4-layer boards. The junction temperature rise
above ambient will be approximately equal to:
T
W
C W
C
A
J
=
=
0 308
158
48 7
.
/
.
So, to limit the junction temperature to 125
C, the maximum
allowable ambient temperature is:
T
C
C
C
MAX
A(
)
.
.
=
-
=
125
48 7
76 3
Shutdown Mode
Applying a high signal to the shutdown pin, or connecting it to
the input pin, will turn the output ON. Pulling the shutdown
pin to 0.3 V or below, or connecting it to ground, will turn the
output OFF. In shutdown mode, the quiescent current is reduced
to less than 1
A.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
1. Keep the output capacitor as close to the output and ground
pins as possible.
2. Keep the input capacitor as close to the input and ground
pins as possible.
3. PC board traces with larger cross sectional areas will remove
more heat from the ADP3333. For optimum heat transfer,
specify thick copper and use wide traces.
4. Connect the NC pins (Pins 5, 6, and 8) to ground for better
thermal performance.
5. The thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.
6. Use additional copper layers or planes to reduce the thermal
resistance. Again, connecting the other layers to the ground and
NC pins of the ADP3333 is best, but not necessary. When
connecting the ground pad to other layers use multiple vias.
REV. 0
8
C026151.57/01(0)
PRINTED IN U.S.A.
ADP3333
8-Lead Mini/micro SOIC Package [Mini_SO]
(RM-8)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Document Outline
- Specifications
- Pinout
- Package drawings
- Ordering Guide
- Features
- Applications
- Product Description
- Absolute Maximum Ratings
- Functional Block Diagram 1
- Pin Function Description
- Circuit Description
- Typical Characteristics
- CAUTION
- THEORY OF OPERATION
- APPLICATION INFORMATION
- DIAGRAMS
- Typical Application Circuit
- Functional Block Diagram 2
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