Document Outline
- Specifications
- Pinout
- Package Drawings
- Ordering Guide
- Features
- Applications
- Product Description
- Timing characteristics
- Absolute Maximum Ratings
- Functional Block Diagram
- DAC AC CHARACTERISTICS1
- REFERENCE FEEDTHROUGH
- TERMINOLOGY RELATIVE ACCURACY
- DIFFERENTIAL NONLINEARITY
- CHANNEL-TO-CHANNEL ISOLATION
- MAJOR-CODE TRANSITION GLITCH ENERGY
- OFFSET ERROR
- OFFSET ERROR MATCH
- DIGITAL FEEDTHROUGH
- GAIN ERROR
- DIGITAL CROSSTALK
- GAIN ERROR MATCH
- OFFSET ERROR DRIFT
- ANALOG CROSSTALK
- GAIN ERROR DRIFT
- DC POWER-SUPPLY REJECTION RATIO (PSRR)
- DAC-TO-DAC CROSSTALK
- DC CROSSTALK
- MULTIPLYING BANDWIDTH
- TOTAL HARMONIC DISTORTION
- ROUND ROBIN
- FUNCTIONAL DESCRIPTION - DAC
- TEMPERATURE SENSOR
- FUNCTIONAL DESCRIPTION
- POWER-UP TIME
- VDD MONITORING
- ON-CHIP REFERENCE
- ROUND ROBIN MEASUREMENT
- SINGLE CHANNEL MEASUREMENT
- MEASUREMENT METHOD
- LAYOUT CONSIDERATIONS
- TEMPERATURE VALUE FORMAT
- THERMAL VOLTAGE OUTPUT
- INTERRUPTS
- ADT7316/7317/7318 REGISTERS
- INTERNAL TEMPERATURE VALUE/VDD VALUE REGISTER
- INTERNAL TEMPERATURE VALUE REGISTER
- EXTERNAL TEMPERATURE VALUE REGISTER
- DAC A REGISTER LSBS (Read/Write) [Add. = 10h]
- DAC B REGISTER MSBS (Read/Write) [Add. = 13h]
- DAC B REGISTER LSBS (Read/Write) [Add. = 12h]
- DAC C REGISTER MSBS (Read/Write) [Add. = 15h]
- DAC D REGISTER LSBS (Read/Write) [Add. = 16h]
- CONTROL CONFIGURATION 1 REGISTER (Read/WRITE)
- CONTROL CONFIGURATION 2 REGISTER (Read/ Write) [Add. = 19h]
- CONTROL CONFIGURATION 3 REGISTER
- LDAC CONFIGURATION REGISTER
- INTERRUPT MASK 2 REGISTER
- INTERRUPT MASK 1 REGISTER
- INTERNAL TEMPERATURE OFFSET REGISTER
- INTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 21h]
- EXTERNAL ANALOG TEMPERATURE OFFSET
- EXTERNAL THIGH LIMIT REGISTER
- EXTERNAL TLOW LIMIT REGISTER
- DEVICE ID REGISTER (READ ONLY) [ADD. = 4DH]
- ADT7316/7317/7318 SERIAL INTERFACE
- MANUFACTURERS ID REGISTER (Read only)
- SERIAL INTERFACE SELECTION
- SILICON REVISION REGISTER
- I2C SERIAL INTERFACE
- WRITING TO THE ADT7316/7317/7318
- READING DATA FROM THE ADT7316/7317/7318
- SPI SERIAL INTERFACE
- SMBUS/SPI INTERRUPT
- DIAGRAMS
- Diagram for I2C Bus Timing
- Diagram for SPI Bus Timing
- Load Circuit for Access Time and Bus Relinquish Time
- Load Circuit for DAC Outputs
- Single DAC channel architecture
- DAC Reference Buffer Circuit
- Resistor String
- Signal Conditioning for External Diode temperature Sensors
- Top Level Structure of Internal Temperature Sensor
- ADT7316/17/18 Interrupt Structure
- Phase 2 of 10-Bit Read
- Phase 1 of 10-Bit Read
- I2C - Writing to the Address Pointer Register to select a register for a subsequent Read operation
- I2C - Writing to the Address Pointer Register followed by a single byte of data to the selected register
- I2C - Reading a single byte of data from a selected register
- SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register
- SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation
- SPI - Reading a single byte of data from a selected register
- SPI - Reading a two bytes of data from two sequential registers
ADT7316/7317/7318
=
REV. PrN 02/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 Analog Devices, Inc., 200
2
SPI/I
2
C
Compatible, 10-Bit Digital Temperature
Sensor and Quad Voltage Output 12/10/8-Bit DAC
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
FEATURES
ADT7316 - Four 12-Bit DACs
ADT7317 - Four 10-Bit DACs
ADT7318 - Four 8-Bit DACs
Buffered Voltage Output
Guaranteed Monotonic By Design Over All Codes
10-Bit Temperature to Digital Converter
Temperature range:
-40
o
C to +125
o
C
Temperature Sensor Accuracy of 0.5
o
C
Supply Range : + 2.7 V to + 5.5 V
DAC Output Range: 0 - 2V
REF
Power-Down Current 1
A
Internal 2.25 V
Ref
Option
Double-Buffered Input Logic
Buffered / Unbuffered Reference Input Option
Power-on Reset to Zero Volts
Simultaneous Update of Outputs (
LDAC
Function)
On-Chip Rail-to-Rail Output Buffer Amplifier
I
2
C
, SPI
TM
, QSPI
TM
, MICROWIRE
TM
and DSP-Compatible 4-
wire Serial Interface
16-Lead QSOP Package
APPLICATIONS
Portable Battery Powered Instruments
Personal Computers
Telecommunications Systems
Electronic Test Equipment
Domestic Appliances
Process Control
GENERAL DESCRIPTION
The ADT7316/7317/7318 combines a 10-Bit Tempera-
ture-to-Digital Converter and a quad 12/10/8-Bit DAC
respectively, in a 16-Lead QSOP package. This includes a
bandgap temperature sensor and a 10-bit ADC to monitor
and digitize the temperature reading to a resolution of
0.25
o
C. The ADT7316/17/18 operates from a single
+2.7V to +5.5V supply. The output voltage of the DAC
ranges from 0 V to 2V
REF
, with an output voltage settling
time of typ 7 msec. The ADT7316/17/18 provides two
serial interface options, a four-wire serial interface which
is compatible with SPI
TM
, QSPI
TM
, MICROWIRE
TM
and
DSP interface standards; and a two-wire I
2
C interface. It
features a standby mode that is controlled via the serial
interface.
The reference for the four DACs is derived either inter-
nally or from two reference pins (one per DAC pair) .The
outputs of all DACs may be updated simultaneously using
the software
LDAC
function or external LDAC pin. The
ADT7316/7317/7318 incorporates a power-on-reset cir-
cuit, which ensures that the DAC output powers-up to
zero volts and it remains there until a valid write takes
place.
The ADT7316/7317/7318's wide supply voltage range,
low supply current and SPI/I
2
C-compatible interface,
make it ideal for a variety of applications, including per-
sonal computers, office equipment and domestic appli-
ances.
I
2
C is a registered trademark of Philips Corporation
* Protected by U.S. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, INC.
MICROWIRE is a trademark of National Semiconductor Corporation.
FUNCTIONAL BLOCK DIAGRAM
V
D D
VA LUE
REGISTER
STRING
DA C B
EXTERNA L TEMPERATURE
VALUE REGISTER
A -TO-D
CONVERTER
INTERNAL TEMPERATURE
VA LUE REGISTER
ON-CHIP
TEMPERA TURE
SENSOR
ANAL OG
MUX
D
I
G
I
T
A
L
M
U
X
LIMIT
COMPARATOR
D
I
G
I
T
A
L
M
U
X
DAC C
REGISTERS
ADDRESS POINTER
REGISTER
T
H IGH
LIMIT
REGISTERS
T
L OW
L IMIT
REGISTERS
V
D D
L im it
REGISTERS
CONTROL CONFIG . 1
REGISTER
CONTROL CONFIG . 3
REGISTER
CONTROL CONFIG. 2
REGISTER
DA C CONFIGURATION
REGISTER
L DA C CONFIGURATION
REGISTER
INTERRUPT MASK
REGISTERS
DAC A
REGISTERS
DA C B
REG ISTERS
DAC D
REGISTERS
STRING
DAC A
STRING
DA C C
STRING
DA C D
GAIN
SELECT
LO GIC
POWER
DOWN
L OGIC
V
OUT
-A
V
OUT
-B
V
OUT
-C
V
OUT
-D
D+
D-
SMB us/SPI INTERFACE
CS
SCL/SCL K
SDA /DIN
DOUT/ADD
INTERRUPT
STA TUS
REGISTERS
V
D D
SENSOR
V
D D
GND
INTERNAL TEMP
SENSOR
V
R EF
-A B
V
R EF
-CD
LDAC
ADT7316/17/18
7
8
6
5
4
13
12
11
9
3
14
10
15
16
1
2
2
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/ADT7317/ADT7318-SPECIFICATIONS
1
(V
DD
=2.7 V to 5.5 V, GND=0 V, REF
IN
=2.25 V, unless otherwise noted)
Parameter
2
Min
Typ
M a x
Units
Conditions/Comments
DAC DC PERFORMANCE
3,4
ADT7318
Resolution
8
Bits
Relative Accuracy
0.15
1
L S B
Relative Accuracy
tbd
tbd
L S B
Excluding Offset and Gain errors
Differential Nonlinearity
0.02
0.25
L S B
Guaranteed Monotonic by design over all codes
ADT7317
Resolution
10
Bits
Relative Accuracy
0.5
4
L S B
Relative Accuracy
tbd
tbd
L S B
Excluding Offset and Gain errors
Differential Nonlinearity
0.05
0.5
L S B
Guaranteed Monotonic by design over all codes
ADT7316
Resolution
12
Bits
Relative Accuracy
2
16
L S B
Relative Accuracy
tbd
tbd
L S B
Excluding Offset and Gain errors
Differential Nonlinearity
0.02
0.9
L S B
Guaranteed Monotonic by design over all codes
Offset Error
0.4
3
% of FSR
Offset Error Match
0.5
L S B
Gain Error
0.3
1.25
% of FSR
Gain Error Match
0.5
L S B
Lower Deadband
20
60
m V
Lower Deadband exists only if Offset Error is
Negative. See Figure 5.
Upper Deadband
tbd
tbd
m V
Upper Deadband exists if V
REF
= V
DD
and Offset
plus Gain Error is positive. See Figure 6.
Offset Error Drift
6
-12
ppm of FSR/C
Gain Error Drift
6
- 5
ppm of FSR/C
DC Power Supply Rejection Ratio
6
-60
dB
V
DD
= 10%
DC Crosstalk
6
200
V
R
L
= 2 K
to GND or V
DD
THERMAL CHARACTERISTICS
Internal Reference used.
INTERNAL TEMPERATURE
SENSOR
Accuracy @ V
DD
=3.3V
2
C
T
A
= 0C to +85C
3
C
T
A
= -40C to +125C
Accuracy @ V
DD
=5V
2
C
T
A
= 0C to +85C
3
C
T
A
= -40C to +125C
Resolution
1 0
Bits
Long Term Drift
0.5
C/1000hrs
EXTERNAL TEMPERATURE
S E N S O R
External Transistor = 2N3906.
Accuracy @ V
DD
=3.3V
2
C
T
A
= 0C to +85C.
3
C
T
A
= -40C to +125C
Accuracy @ V
DD
=5V
2
C
T
A
= 0C to +85C
3
C
T
A
= -40C to +125C
Resolution
1 0
Bits
Update Rate, t
R
T B D
s
Round Robin
5
enabled
T B D
s
Round Robin disabled
Temperature Conversion Time
T B D
s
Output Source Current
180
A
High Level
11
A
Low Level
VOLTAGE OUTPUT
8-Bit DAC Output
Resolution
1
C
Scale Factor
8.79
mV/C
0-V
REF
Output. T
A
= -40C to +125C
17.58
mV/C
0-2V
REF
Output. T
A
= -40C to +125C
10-Bit DAC Output
Resolution
0.25
C
ADT7316/7317/7318
3
REV. PrN
PRELIMINARY TECHNICAL DATA
Scale Factor
2.2
mV/C
0-V
REF
Output. T
A
= -40C to +125C
4.39
mV/C
0-2V
REF
Output. T
A
= -40C to +125C
DAC ERTERNAL
REFERENCE INPUT
6
V
REF
Input Range
1
V
DD
V
Buffered Reference Mode
V
REF
Input Range
0.25
V
DD
V
Unbuffered Reference Mode
V
REF
Input Impedance
3 7
4 5
k
Unbuffered Reference Mode. 0-2 V
REF
Output Range.
7 4
9 0
k
Unbuffered Reference Mode. 0- V
REF
Output Range.
>10
M
Buffered reference mode and Power-Down Mode
Reference Feedthrough
-90
d B
Frequency=10KHz
Channel-toChannel Isolation
-75
d B
Frequency=10KHz
ON-CHIP REFERENCE
Reference Voltage
6
2.25
V
Temperature Coefficient
6
8 0
ppm/
C
OUTPUT CHARACTERISTICS
6
Output Voltage
7
0.001
V
DD
-0.001
V
This is a measure of the minimum and maximum drive
capability of the output amplifier
DC Output Impedance
0.5
Short Circuit Current
2 5
m A
V
DD
= +5V
1 6
m A
V
DD
= +3V
Power Up Time
2.5
s
Coming out of Power Down Mode. V
DD
= +5 V
5
s
Coming out of Power Down Mode. V
DD
= +3 V
DIGITAL INPUTS
6
Input Current
1
A
V
IN
= 0V to V
DD
V
IL
, Input Low Voltage
0.8
V
V
DD
= +5V10%
0.6
V
V
DD
= +3V10%
V
IH
, Input High Voltage
1.89
V
Pin Capacitance
3
1 0
p F
All Digital Inputs
SCL, SDA Glitch Rejection
5 0
ns
Input Filtering Suppresses Noise Spikes of Less than 50
ns
DIGITAL OUTPUT
Output High Voltage, V
OH
2.4
V
I
SOURCE
= I
SINK
= 200 A
Output Low Voltage, V
OL
0.4
V
I
OL
= 3 mA
Output High Current, I
OH
1
m A
V
OH
= 5 V
Output Capacitance, C
OUT
50
p F
ALERT Output Saturation Voltage
0.8
V
I
OUT
= 4 mA
I
2
C TIMING CHARACTERISTICS
8,9
Serial Clock Period, t
1
2.5
s
Fast-Mode I
2
C. See Figure 1
Data In Setup Time to SCL High, t
2
Data Out Stable after SCL Low, t
3
0
ns
See Figure 1
SDA Low Setup Time to SCL Low
(Start Condition), t
4
50
ns
See Figure 1
SDA High Hold Time after SCL High
(Stop Condition), t
5
50
ns
See Figure 1
SDA and SCL Fall Time, t
6
90
ns
See Figure 1
SPI TIMING CHARACTERISTICS
10, 11
CS to SCLK Setup Time, t
1
0
ns
See Figure 2
SCLK High Pulsewidth, t
2
50
ns
See Figure 2
SCLK Low Pulse, t
3
50
ns
See Figure 2
Data Access Time after
SCLK Falling edge, t
4
12
35
ns
See Figure 2
Data Setup Time Prior
to SCLK Rising Edge, t
5
20
ns
See Figure 2
Data Hold Time after
SCLK Rising Edge, t
6
0
ns
See Figure 2
CS to SCLK Hold Time, t
7
0
ns
See Figure 2
CS to DOUT High Impedance, t
8
40
ns
See Figure 2
POWER REQUIREMENTS
V
DD
2.7
5.5
V
V
DD
Settling Time
50
ms
V
DD
settles to within 10% of it's final voltage
level.
Parameter
2
Min
Typ
M a x
Units
Conditions/Comments
4 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
DAC AC CHARACTERISTICS
1
(V
DD
= +2.7V to +5.5 V; R
L
=4k7
to GND; C
L
=200pF to GND;
4K7
to V
DD
; All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
2
Min
Typ @ 25C
M a x
Units
Conditions/Comments
Output Voltage Settling Time
V
REF
=V
DD
=+5V
ADT7318
6
8
s
1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)
ADT7317
7
9
s
1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)
ADT7316
8
1 0
s
1/4 Scale to 3/4 Scale change (400 Hex to
C00 Hex)
Slew Rate
0.7
V/s
Major-Code Change Glitch Energy
1 2
nV-s
1 LSB change around major carry.
Digital Feedthrough
0.5
nV-s
Digital Crosstalk
1
nV-s
Analog Crosstalk
0.5
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
k H z
V
REF
=2V0.1Vpp
Total Harmonic Distortion
-70
d B
V
REF
=2.5V0.1Vpp. Frequency=10kHz.
NOTES
1
Guaranteed by Design and Characterization, not production tested
2
See Terminology
Specifications subject to change without notice.
t
1
t
4
t
2
t
3
t
5
S C L
S D A
DA T A IN
S D A
DA T A O U T
t6
Figure 1. Diagram for I
2
C Bus Timing
I
DD
(Normal Mode)
13
0.85
1.3
m A
V
IH
= V
DD
and V
IL
= GND
I
DD
(Power Down Mode)
1
3
A
V
DD
= +4.5V to +5.5V, V
IH
=V
DD
and V
IL
=GND
0.5
1
A
V
DD
= +2.7V to +3.6V, V
IH
=V
DD
and V
IL
=GND
Power Dissipation
tbd
tbd
tbd
W
V
DD
= +2.7 V. Using Normal Mode
tbd
tbd
tbd
W
V
DD
= +2.7 V. Using Shutdown Mode
Notes:
1
Temperature ranges are as follows: A Version: -40C to +125C.
2
See Terminology.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)
5
See Terminology.
6
Guaranteed by Design and Characterization, not production tested
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF
=V
DD
,
"Offset plus Gain" Error must be positive.
8
The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I
2
C specification. Switching off the input filters improves the transfer
rate but has a negative affect on the EMC behaviour of the part.
9
Guaranteed by design. Not tested in production.
10
Guaranteed by design and characterization, not production tested.
11
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
12
Measured with the load circuit of Figure 3.
13
I
DD
spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Specifications subject to change without notice.
ADT7316/7317/7318
5
REV. PrN
PRELIMINARY TECHNICAL DATA
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
1.6V
I
O L
200 A
200 A
I
O L
TO
O UTPUT
P IN
C
L
50pF
Figure 2. Diagram for SPI Bus Timing
DOU T
D BX
DBX
DBX
DBX
DB7
+5
SCLK
1
2
3
4
8
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
DIN
DB7
DB6
DB0
DB5
DB8
MSB
L SB
MSB
MSB
V
DD
47
47
200
pF
To DAC
Ou tp ut
Figure 4. Load Circuit for DAC Outputs
6 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
ABSOLUTE MAXIMUM RATINGS*
V
DD
to GND
0.3 V to +7 V
Digital Input Voltage to GND
0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND
0.3 V to V
DD
+ 0.3 V
Reference Input voltage to GND 0.3 V to V
DD
+ 0.3V
Operating Temperature Range
40C to +125C
Storage Temperature Range
65C to +150C
Junction Temperature
+150C
16-Lead QSOP Package
Power Dissipation
(T
j
max - T
A
) /
JA
JA
Thermal Impedance
150 C/W (QSOP)
Reflow Soldering
Peak Temperature
+220 +/- 0C
Time of Peak Temperature
10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
DAC Resolution
Package Description
Package Options
ADT7318ARQ
40C to +125C
8-Bits
16-Lead QSOP
RQ-16
ADT7317ARQ
-40C to +125C
10-Bits
16-Lead QSOP
RQ-16
ADT7316ARQ
-40C to +125C
12-Bits
16-Lead QSOP
RQ-16
C A U T I O N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADT7316/7317/7318 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
QSOP
Table 1. I
2
C Address Selection
ADD Pin
I
2
C Address
Low
1001 000
Float
1001 010
High
1001 011
ADT7316/
7317/7318
TO P VIE W
(Not to Sc al e)
INTERRUPT
V
ou t
-A
V
ou t
-B
GND
SDA/DIN
DOUT/ADD
VDD
D+
D-
CS
SCL/SCLK
V
ou t
-C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
ou t
-D
LDAC
V
r ef
-AB
V
r ef
-CD
ADT7316/7317/7318
7
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318 PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
V
OUT
B
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
2
V
OUT
A
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3
V
REF
AB
Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input
to each or both of the DACs A and B. It has an input range from 0.25 V to V
DD
in unbuffered
mode and from 1 V to V
DD
in buffered mode.
4
C S
SPI Active low control Input. This is the frame synchronization signal for the input data.
When CS goes low, it enables the input register and data is transferred in and out on the ris-
ing edges of the following serial clocks. This pin must be kept high for I
2
C mode of operation.
CS is also used as a control pin when selecting the serial interface type after power-up.
5
G N D
Ground Reference Point for All Circuitry on the part. Analog and Digital Ground.
6
V
DD
Positive Supply Voltage, +2.7 V to +5.5 V.The supply should be decoupled to ground.
7
D +
Positive connection to external temperature sensor
8
D -
Negative connection to external temperature sensor
9
LDAC
Active low control input that transfers the contents of the input registers to their respective
DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input
registers have new data. This allows simultaneous update of all DAC outputs.
Bit C3 of Con-
trol Configuration 3 register enables
LDAC pin. Default is with LDAC pin controlling the
loading of DAC registers.
10
INTERRUPT
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active
high interrupt when temperature, V
DD
and AIN limits are exceeded. Default is active low.
11
D O U T / A D D
SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is
clocked out at the falling edge of SCLK.
ADD, I
2
C serial bus address selection pin. Logic input. During the first valid I
2
C bus commu-
nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/
18. Any subsequent changes on this pin will have no affect on the I
2
C serial bus address. A low
on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and set-
ting it high gives the address 1001 011.
12
S D A / D I N
SDA - I
2
C Serial Data Input. I
2
C serial data to be loaded into the parts registers is provided
on this input.
DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on
this input. Data is clocked into a register on the rising edge of SCLK.
13
SCL/SCLK
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock
data out of any register of the ADT7316/7317/7318 and also to clock data into any register
that can be written to.
14
V
REF
CD
Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input
to each or both of the DACs C and D. It has an input range from 0.25 V to V
DD
in unbuffered
mode and from 1 V to V
DD
in buffered mode.
15
V
OUT
D
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
16
V
OUT
C
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
8 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or integral nonlinearity (INL) is a mea-
sure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. Typical INL versus Code plots can be seen in
TPCs 1, 2, and 3.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference be-
tween the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified differential
nonlinearity of 1 LSB maximum ensures monotonicity.
This DAC and Temperature Sensor ADC is guaranteed
monotonic by design. Typical DAC DNL versus Code
plots can be seen in TPCs 4, 5, and 6.
OFFSET ERROR
This is a measure of the offset error of the DAC and the
output amplifier. (See Figures 5 and 6.) It can be negative
or positive. It is expressed in mV.
OFFSET ERROR MATCH
This is the difference in Offset Error between any two
channels.
GAIN ERROR
This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic
from the ideal expressed as a percentage of the full-scale
range.
GAIN ERROR MATCH
This is the difference in Gain Error between any two
channels.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with
changes in temperature. It is expressed in (ppm of full-
scale range)/C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-
scale range)/C.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the
change in V
OUT
to a change in V
DD
for full-scale output of
the DAC. It is measured in dBs. V
REF
is held at 2 V and
V
DD
is varied 10%.
DC CROSSTALK
This is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC
while monitoring another DAC. It is expressed in V.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the
DAC output to the reference input when the DAC output
is not being updated (i.e.,
LDAC is high). It is expressed
in dBs.
CHANNEL-TO-CHANNEL ISOLATION
This is the ratio of the amplitude of the signal at the out-
put of one DAC to a sine wave on the reference input of
another DAC. It is measured in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the
impulse injected into the analog output when the code in
the DAC register changes state. It is normally specified as
the area of the glitch in nV secs and is measured when the
digital code is changed by 1 LSB at the major carry transi-
tion (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to
011 . . . 11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected
into the analog output of a DAC from the digital input
pins of the device but is measured when the DAC is not
being written to the. It is specified in nV secs and is mea-
sured with a full-scale change on the digital input pins,
i.e., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one
DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of
another DAC. It is measured in stand-alone mode and is
expressed in nV secs.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one
DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-
scale code change (all 0s to all 1s and vice versa) while
keeping
LDAC high. Then pulse LDAC low and monitor
the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one
DAC due to a digital code change and subsequent out-
put change of another DAC. This includes both digital
and analog crosstalk. It is measured by loading one of the
DACs with a full-scale code change (all 0s to all 1s and
vice versa) with
LDAC low and monitoring the output of
another DAC. The energy of the glitch is expressed in nV
secs.
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth.
The multiplying bandwidth is a measure of this. A sine
wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying band-
width is the frequency at which the output amplitude falls
to 3 dB below the input.
ADT7316/7317/7318
9
REV. PrN
PRELIMINARY TECHNICAL DATA
GAIN ERROR
+
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
DAC CODE
NEGATIVE
OFFSET
ERROR
AMPL IFIER
FOOTROOM
L OWER
DEADBAND
CODES
ACTUA L
IDEAL
OUTPUT
VOL TAGE
POSITIVE
OFFSET
ERROR
DAC C ODE
GAIN ERROR
+
OFFSET ERROR
ACTUAL
IDEAL
UPPER
DEADBAND
CODES
FULL SCALE
Figure 5. Transfer Function with Negative Offset
Figure 6. Transfer Function with Positive Offset (V
REF
= V
DD
)
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measure of
the harmonics present on the DAC output. It is measured
in dBs.
ROUND ROBIN
This term is used to describe the ADT7316/17/18 cycling
through the available measurement channels in sequence
taking a measurement on each channel.
10 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
CODE
I
N
L
E
R
R
O
R
-
L
S
B
s
1.0
0.5
-1.0
0
50
250
100
150
200
0
-0.5
T
A
= 25 C
V
DD
= 5V
TPC 1. ADT7318 Typical INL Plot
TPC 2. ADT7317 Typical INL Plot
TPC 3. ADT7316 Typical INL Plot
COD E
I
N
L
E
R
R
O
R
-
L
S
B
s
12
0
-4
-8
8
4
0
4000
1000
2000
3000
-12
T
A
= 25 C
V
DD
= 5V
CODE
I
N
L
E
R
R
O
R
-
L
S
B
s
3
0
200
1000
400
600
800
0
-1
-2
-3
2
1
T
A
= 25 C
V
DD
= 5V
CODE
D
N
L
E
R
R
O
R
-
L
S
B
s
0.4
-0.4
600
400
800
1000
0
-0.6
0.6
0.2
-0.2
T
A
= 25 C
V
DD
= 5V
200
0
C ODE
D
N
L
E
R
R
O
R
-
L
S
B
s
0
5 0
2 5
1 00
1 5 0
2 00
- 0. 1
- 0. 2
- 0. 3
0. 3
0. 1
0. 2
0
T
A
= 2 5 C
V
DD
= 5 V
TPC 4. ADT7318 Typical DNL Plot
TPC 5. ADT7317 Typical DNL Plot
TPC 6. ADT7316 Typical DNL Plot
V
REF
- V
E
R
R
O
R
-
L
S
B
s
0.5
0.25
-0.5
0
1
5
2
3
4
0
-0.25
V
DD
= 5V
T
A
= 25 C
M A X INL
MA X DNL
M IN DNL
M IN INL
TEMPERATURE - C
E
R
R
O
R
-
L
S
B
s
0.5
0.2
-0.5
40
0
40
0
-0.2
V
DD
= 5V
V
RE F
= 3V
MA X INL
80
120
-0.4
-0.3
-0.1
0.1
0.3
0.4
MA X DNL
MIN INL
M IN DNL
GA IN E RRO R
TEMPERATURE - C
E
R
R
O
R
-
%
F
S
R
1
0.5
-1
40
0
40
0
-0.5
V
DD
= 5V
V
RE F
= 2V
O F FS ET ERRO R
80
120
TPC 7. ADT7318 INL and DNL
Error vs V
REF
TPC 8. ADT7318 INL Error and DNL
Error vs Temperature
TPC 9. ADT7318 Offset Error and Gain
Error vs Temperature
CODE
D
N
L
E
R
R
O
R
-
L
S
B
s
0.5
2000
3000
4000
0
-1
1
-0.5
T
A
= 25 C
V
DD
= 5V
1000
0
ADT7316/7317/7318
11
REV. PrN
PRELIMINARY TECHNICAL DATA
G A IN ERRO R
V
DD
- Vol ts
E
R
R
O
R
-
%
F
S
R
0.2
-0.6
0
1
3
0
-0.4
T
A
= 25 C
V
RE F
= 2V
4
6
-0.5
-0.3
-0.2
-0.1
0.1
2
5
O F FS ET ERRO R
TPC 10. Offset Error and Gain
Error vs V
DD
5V SO URCE
SINK/SOURCE CURRENT - mA
V
O
U
T
-
V
o
l
t
s
5
0
0
1
3
4
4
6
1
2
3
2
5
3V SO URCE
3V SINK
5V SINK
TPC 11. V
OUT
Source and Sink Current
Capability
CODE
I
D
D
-
A
600
ZERO-SCAL E
FULL -SCAL E
500
400
300
200
100
0
T
A
= 25 C
V
DD
= 5V
V
REF
= 2V
TPC 12. Supply Current vs. DAC Code
V
DD
- Vo lt s
I
D
D
-
A
600
2.5
500
400
300
200
100
0
3.0
3.5
4.0
4.5
5.0
5.5
-40 C
+25 C
+105 C
TPC 13. Supply Current vs. Supply Volt-
age
V
DD
- Vo lts
I
D
D
-
A
0.5
0
0.4
0.1
0.2
0.3
2.5
3.
0
4.0
4.5
5.5
3.5
5.0
+105 C
- 40 C
+25 C
TPC 14. Power-Down Current vs. Supply
Voltage
V
OUT
A
5 s
CH1
CH2
S CLK
T
A
= 25 C
V
D D
= 5V
V
R E F
= 5V
CH1 1V, CH2 5V, TIME BASE= 1 s/DIV
TPC 15. Half-Scale Settling (1/4 to 3/4
Scale Code Change)
T
A
= 25 C
V
DD
= 5V
V
REF
= 2V
CH1
CH2
CH 1 500mV, CH2 5.00V, TIME BASE = 1 s/DIV
V
OUT
A
2,
TPC 16. Exiting Power-Down to Midscale
1 s/DIV
2.4
8
2.49
V
O
U
T
-
V
o
l
t
s
2.47
2.50
TPC 17. ADT7316 Major-Code Transition
Glitch Energy
FR EQUENCY - kHz
10
-40
0.01
-20
-30
0
-10
d
B
0.1
1
10
100
1k
10k
-50
-60
TPC 18. Multiplying Bandwidth (Small-
Signal Frequency Response)
12 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
V
D D
= 5V
T
A
= 25 C
V
REF
- Vol ts
F
U
L
L
-
S
C
A
L
E
E
R
R
O
R
-
V
o
l
t
s
0.02
-0.02
0
1
3
0.01
-0.01
4
6
0
2
5
TPC 19. Full-Scale Error vs. V
REF
150n s/DIV
1
m
V
/
D
I
V
TPC 20. DAC-to-DAC Crosstalk
TPC 21. PSRR vs Supply Ripple Frequency
TITLE
0
0
0
0
0
0
T
I
T
L
E
0
0
0
0
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
TEMPERATURE ('C)
TEMPERATURE ERROR ('
C
5.5V
3.3V
TPC 22. Temperature Error @ 3.3 V and 5.5 V
ADT7316/7317/7318
13
REV. PrN
PRELIMINARY TECHNICAL DATA
FUNCTIONAL DESCRIPTION - DAC
The ADT7316/7317/7318 has quad resistor-string DACs
fabricated on a CMOS process with a resolutions of 12,
10 and 8 bits respectively. They contain four output buffer
amplifiers and is written to via I
2
C serial interface or SPI
serial interface. See Serial Interface Selection section for
more information.
The ADT7316/7317/7318 operates from a single supply
of 2.7 V to 5.5 V and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7V/
s.
DACs A and B share a common reference input, namely
V
REF
AB. DACs C and D share a common reference input,
namely V
REF
CD. Each reference input may be buffered to
draw virtually no current from the reference source, or
unbuffered to give a reference input range from GND to
V
DD
. The devices have a power-down mode, in which all
DACs may be turned off completely with a high-imped-
ance output.
Each DAC output will not be updated until it receives the
LDAC command. Therefore while the DAC registers
would have been written to with a new value, this value
will not be represented by a voltage output until the DACs
have received the LDAC command. Reading back from
any DAC register prior to issuing an LDAC command
will result in the digital value that corresponds to the
DAC output voltage. Thus the digital value written to the
DAC register cannot be read back until after the LDAC
command has been initiated. This LDAC command can
be given by either pulling the
LDAC pin low, setting up
Bits D4 and D5 of DAC Configuration register(Address =
1Bh) or using the LDAC register(Address = 1Ch).
Digital-to-Analog Section
The architecture of one DAC channel consists of a resis-
tor-string DAC followed by an output buffer amplifier.
The voltage at the V
REF
pin or the on-chip reference of
2.25 V provides the reference voltage for the correspond-
ing DAC. Figure 7 shows a block diagram of the DAC
architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
V
REF
* D
V
OUT
= ----------
2
N
where D=decimal equivalent of the binary code which is
loaded to the DAC register;
0-255 for ADT7318 (8-Bits)
0-1023 for ADT7317 (10-Bits)
0-4095 for ADT7316 (12-Bits)
N = DAC resolution.
V
REF
AB
Int V
REF
REFERENCE
BUFFER
BUF
GA IN MODE
(GAIN=1 OR 2)
V
O UT
A
OUTPUT BUFFER
AMPLIFIER
RESISTOR
STRING
DAC
REGISTER
INPUT
REGISTER
Figure 7. Single DAC channel architecture
Resistor String
The resistor string section is shown in Figure 9. It is sim-
ply a string of resistors, each of value R. The digital code
loaded to the DAC register determines at what node on
the string the voltage is tapped off to be fed into the out-
put amplifier. The voltage is tapped off by closing one of
the switches connecting the string to the amplifier. Be-
cause it is a string of resistors, it is guaranteed monotonic.
DAC Reference Inputs
There is a reference pin for each pair of DACs. The refer-
ence inputs are buffered but can also be individually con-
figured as unbuffered.
2 . 25 V
I nte r n a l V
R EF
STRING
DAC A
STRING
DAC B
V
RE F
-AB
Figure 8. DAC Reference Buffer Circuit
The advantage with the buffered input is the high imped-
ance it presents to the voltage source driving it. However
if the unbuffered mode is used, the user can have a refer-
ence voltage as low as 0.25 V and as high as V
DD
since
there is no restriction due to headroom and footroom of
the reference amplifier.
14 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
R
R
R
R
R
TO OUTPUT
AMPLIFIER
Figure 9. Resistor String
If there is a buffered reference in the circuit , there is no
need to use the on-chip buffers. In unbuffered mode the
input impedance is still large at typically 90 k
per refer-
ence input for 0-V
REF
output mode and 45 k
for 0-2V
REF
output mode.
The buffered/unbuffered option is controlled by the DAC
Configuration Register (address 1Bh, see data register
descriptions). The LDAC Configuration register controls
the option to select between internal and external voltage
references. The default setting is for external reference
selected.
Output Amplifier
The output buffer amplifier is capable of generating out-
put voltages to within 1mV of either rail. Its actual range
depends on the value of V
REF
, GAIN and offset error.
If a gain of 1 is selected (Bits 0-3 of DAC Configuration
register = 0) the output range is 0.001 V to V
REF
.
If a gain of 2 is selected (Bits 0-3 of DAC Configuration
register = 1) the output range is 0.001 V to 2V
REF
. How-
ever because of clamping the maximum output is limited
to V
DD
- 0.001V.
The output amplifier is capable of driving a load of 2k
to GND or V
DD,
in parallel with 500pF to GND or V
DD
.
The source and sink capabilities of the output amplifier
can be seen in the plot in TPC 11.
The slew rate is 0.7V/
s with a half-scale settling time to
+/-0.5 LSB (at 8 bits) of 6
s.
FUNCTIONAL DESCRIPTION
POWER-UP TIME
On power-up it is important that no communication to the
part is initiated until 200ms after Vcc has settled. During
this 200ms the part is performing a calibration routine and
any communication to the device will interrupt this rou-
tine and could cause erroneous temperature measurements.
V
DD
must have settled to within 10% of it's final value
after 50ms power-on time has elasped. Therefore once
power is applied to the ADT7316/17/18, it can be ad-
dressed 250ms later. If it not possible to have V
DD
at it's
nominal value by the time 50ms has elasped then it is
recommended that a measurement be taken on the V
DD
channel before a temperature measurement is taken.
TEMPERATURE SENSOR
The ADT7316/7317/7318 contains a two-channel A to D
converter with special input signal conditioning to enable
operation with external and on-chip diode temperature
sensors. When the ADT7316/7317/7318 is operating nor-
mally, the A to D converter operates in a free-running
mode. When in Round Robin mode the analog input mul-
tiplexer sequently selects the V
DD
input channel, on-chip
temperature sensor to measure its internal temperature and
then the external temperature sensor. These signals are
digitized by the ADC and the results stored in the various
Value Registers.
The measured results are compared with the Internal and
External, T
HIGH
, T
LOW
limits. These temperature limits are
stored in on-chip registers. If the temperature limits are
not masked out then any out of limit comparisons generate
flags that are stored in Interrupt Status 1 Register and one
or more out-of limit results will cause the INTERRUPT
output to pull either high or low depending on the output
polarity setting.
Theoretically, the temperature sensor and ADC can mea-
sure temperatures from -128
o
C to +127
o
C with a resolu-
tion of 0.25
o
C. However, temperatures outside T
A
are
outside the guaranteed operating temperature range of the
device. Temperature measurement from -128
o
C to
+127
o
C is possible using an external sensor.
Temperature measurement is initiated by three methods.
The first method is applicable when the part is in single
channel measurement mode. It uses an internal clock
countdown of 20ms and then a conversion is preformed.
The internal oscillator is the only circuit that's powered
up between conversions and once it times out, every 20ms,
a wake-up signal is sent to power-up the rest of the cir-
cuitry. A monostable is activated at the beginning of the
wake-up signal to ensure that sufficient time is given to
the power-up process. The monostable typically takes 4
s
to time out. It then takes typically 25s for each conver-
sion to be completed. The temperature is measured 16
times and internally averaged to reduce noise. The total
time to measure a temperature channel is typically 400us
(25us x 16). The new temperature value is loaded into the
Temperature Value Register and ready for reading by the
I
2
C or SPI interface. The user has the option of disabling
the averaging by setting a bit (Bit 5) in the Control Con-
figuration Register 2 (address 19h). The ADT7316/7317/
7318 defaults on power-up with the averaging enabled.
Temperature measurement is also initiated after every read
or write to the part when the part is in single channel mea-
surement mode. Once serial communication has started,
any conversion in progress is stopped and the ADC reset.
Conversion will start again immediately after the serial
communication has finished. The temperature measure-
ment proceeds normally as described above.
The third method is applicable when the part is in round
robin measurement mode. The part measures both the
ADT7316/7317/7318
15
REV. PrN
PRELIMINARY TECHNICAL DATA
internal and external temperature sensors as it cycles
through all possible measurement channels. The two tem-
perature channels are measured each time the part runs a
round robin sequence. In round robin mode the part is
continously measuring.
V
DD
MONITORING
The ADT7316/17/18 also has the capability of monitoring
it's own power supply. The part measures the voltage on
it's V
DD
pin to a resolution of 10 bits. The resultant value
is stored in two 8-bit registers, the two LSBs stored in
register address 03h and the eight MSBs are stored in
register address 06h. This allows the user to have the op-
tion of just doing a one byte read if 10-bit resolution is not
important. The measured result is compared with V
HIGH
and V
LOW
limits. If the V
DD
interrupt is not masked out
then any out of limit comparison generates a flag in Inter-
rupt Status 2 Register and one or more out-of-limit results
will cause the INTERRUPT output to pull either high or
low depending on the output polarity setting.
Measuring the voltage on the V
DD
pin is regarded as moni-
toring a channel. Therefore, along with the Internal and
External temperature sensors the V
DD
voltage makes up
the third and final monitoring channel. You can select the
V
DD
channel for single channel measurement by setting Bit
C4 = 1 and setting Bit 0 to Bit 2 to all 0's in Control
Configuration 2 register.
When measuring the V
DD
value the reference for the ADC
is sourced from the Internal Reference. Table 2 shows the
data format. As the max V
CC
voltage measurable is 7 V,
internal scaling is performed on the V
CC
voltage to match
the 2.25V internal reference value. Below is an example of
how the transfer function works.
V
DD
= 5 V
ADC Reference = 2.25 V
1 LSB = ADC Reference / 2^10 = 2.25 / 1024 =
2.197mV
Scale Factor = Fullscale V
CC
/ ADC Reference = 7 / 2.25
= 3.11
Conversion Result = V
DD
/ ((7/Scale Factor) x LSB size)
= 5 / (3.11 x 2.197mV)
= 2DBh
TABLE 2. V
DD
Data Format, V
REF
= 2.25V
V
DD
Value
Digital Output
Binary
Hex
2.5 V
01 0110 1110
16E
3 V
01 1011 0111
1B7
3.5 V
10 0000 0000
200
4 V
10 0100 1001
249
4.5 V
10 1001 0010
292
5 V
10 1101 1011
2 D B
5.5 V
11 0010 0100
324
6 V
11 0110 1101
36D
6.5 V
11 1011 0110
3B6
7 V
11 1111 1111
3 F F
ON-CHIP REFERENCE
The ADT7316/17/18 has an on-chip 1.2 V band-gap
refernece which is gained up by a switched capacitor am-
plifier to give an output of 2.25 V. The amplifier is only
powered up at the start of the conversion phase and is
powered down at the end of conversion. On power-up the
default mode is to have the internal reference selected as
the reference for the DAC and ADC. The internal refer-
ence is always used when measuring the internal and ex-
ternal temperature sensors.
ROUND ROBIN MEASUREMENT
On power-up the ADT7316/17/18 goes into Round Robin
mode but monitoring is disabled. Setting Bit C0 of Con-
figuration Register 1 to a 1 enables conversions. It se-
quences through the three channels of V
DD
, Internal
temperature sensor and External temperature sensor and
takes a measurement from each. At intervals of tbd ms
another measurement cycle is performed on all three chan-
nels. This method of taking a measurement on all three
channels in one cycle is called Round Robin. Setting Bit 4
of Control Configuration 2 (address 19h) disables the
Round Robin mode and in turn sets up the single channel
mode. The single channel mode is where only one chan-
nel, eg. Internal temperature sensor, is measured in each
conversion cycle.
The time taken to monitor all channels will normally not
be of interest, as the most recently measured value can be
read at any time.
For applications where the Round Robin time is impor-
tant, it can be easily calculated.
As mentioned previously a conversion on each temperature
channel takes 25 us and on the V
DD
channel it takes 15 us.
Each channel is measured 16 times and internally aver-
aged to reduce noise.
The total cycle time for voltage and temperature channels
is therefore nominally :
(2 x 16 x 25) + (16 x 15) = 1.04 ms
SINGLE CHANNEL MEASUREMENT
Setting C4 of Control Configuration 2 register enables the
single channel mode and allows the ADT7316/17/18 to
focus on one channel only. A channel is selected by writ-
ing to Bits 0:2 in register Control Configuration 2 regis-
ter. For example, to select the V
DD
channel for monitoring
write to the Control Configuration 2 register and set C4
to 1 (if not done so already), then write all 0's to bits 0 to
2 . All subsequent conversions will be done on the V
DD
channel only. To change the channel selection to the In-
ternal temperature channel, write to the Control Configu-
ration 2 register and set C0 = 1. When measuring in
single channel mode there is a time delay of TBD us be-
tween each measurement. A measurement is also initiated
after every read or write operation.
16 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
MEASUREMENT METHOD
INTERNAL TEMPERATURE MEASUREMENT
The ADT7316/7317/7318 contains an on-chip bandgap
temperature sensor, whose output is digitized by the on-
chip ADC. The temperature data is stored in the Internal
Temperature Value Register. As both positive and nega-
tive temperatures can be measured, the temperature data is
stored in two's complement format, as shown in Table 3
.
The thermal characteristics of the measurement sensor
could change and therefore an offset is added to the mea-
sured value to enable the transfer function to match the
thermal characteristics. This offset is added before the
temperature data is stored. The offset value used is stored
in the Internal Temperature Offset Register.
EXTERNAL TEMPERATURE MEASUREMENT
The ADT7316/7317/7318 can measure the temperature of
one external diode sensor or diode-connected transistor.
The forward voltage of a diode or diode-connected tran-
sistor, operated at a constant current, exhibits a negative
temperature coefficient of about -2mV/
o
C. Unfortunately,
the absolute value of V
be
, varies from device to device, and
individual calibration is required to null this out, so the
technique is unsuitable for mass-production.
The time taken to measure the external temperature can
be reduced by setting C0 of Control Config. 3 register
(1Ah). This increases the ADC clock speed from 1.4KHz
to 22KHz but the analog filters on the D+ and D- input
pins are switched off to accommodate the higher clock
speeds. Running at the slower ADC speed, the time taken
to measure the external temperature is TBD while on the
fast ADC this time is reduced to TBD.
The technique used in the ADT7316/7317/7318 is to
measure the change in V
be
when the device is operated at
two different currents.
This is given by:
V
be
= KT/q x ln(N)
where:
K is Boltzmann's constant
q is charge on the carrier
T is absolute temperature in Kelvins
N is ratio of the two currents
Figure 10 shows the input signal conditioning used to
measure the output of an external temperature sensor.
This figure shows the external sensor as a substrate tran-
sistor, provided for temperature monitoring on some mi-
croprocessors, but it could equally well be a discrete
transistor.
If a discrete transistor is used, the collector will not be
grounded, and should be linked to the base. If a PNP
transistor is used the base is connected to the D- input and
the emitter to the D+ input. If an NPN transistor is used,
the emitter is connected to the D- input and the base to
the D+ input.
We recommend that a 2N3906 be used as the external
transistor.
To prevent ground noise interfering with the measure-
ment, the more negative terminal of the sensor is not ref-
erenced to ground, but is biased above ground by an
internal diode at the D- input. As the sensor is operating
in a noisy environment, C1 is provided as a noise filter.
See the section on layout considerations for more informa-
tion on C1.
To measure
V
be
, the sensor is switched between operating
currents of I and N x I. The resulting waveform is passed
through a lowpass filter to remove noise, thence to a chop-
per-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce
a DC voltage proportional to
V
be
. This voltage is mea-
sured by the ADC to give a temperature output in 8-bit
two's complement format. To further reduce the effects of
noise, digital filtering is performed by averaging the re-
sults of 16 measurement cycles.
Figure 10. Signal Conditioning for External Diode temperature Sensors
V
DD
I
N x I
I
BIAS
D+
D-
REMOTE
SENSING
TR ANSISTOR
(2N3906)
LOWPASS FILTER
f
c
= 65kHz
TO ADC
V
OUT+
V
O UT-
BIAS
DIODE
C1
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
ADT7316/7317/7318
17
REV. PrN
PRELIMINARY TECHNICAL DATA
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and
care must be taken to protect the analog inputs from
noise, particularly when measuring the very small voltages
from a remote diode sensor. The following precautions
should be taken:
1. Place the ADT7316/17/18 as close as possible to the
remote sensing diode. Provided that the worst noise
sources such as clock generators, data/address buses and
CRTs are avoided, this distance can be 4 to 8 inches.
2. Route the D+ and D- tracks close together, in parallel,
with grounded guard tracks on each side. Provide a
ground plane under the tracks if possible.
3. Use wide tracks to minimize inductance and reduce
noise pickup. 10 mil track minimum width and spacing
is recommended.
GND
D+
D-
GND
10 mil.
10 mil.
10 mil.
10 mil.
10 mil.
10 mil.
10 mil.
Figure 12. Arrangement of Signal Tracks
4. Try to minimize the number of copper/solder joints,
which can cause thermocouple effects. Where copper/
solder joints are used, make sure that they are in both
the D+ and D- path and at the same temperature.
Thermocouple effects should not be a major problem as
1
o
C corresponds to about 240V, and thermocouple
voltages are about 3V/
o
C of temperature difference.
Unless there are two thermocouples with a big tempera-
ture differential between them, thermocouple voltages
should be much less than 200mV.
5. Place 0.1F bypass and 2200pF input filter capacitors
close to the ADT7316/17/18.
6. If the distance to the remote sensor is more than 8
inches, the use of twisted pair cable is recommended.
This will work up to about 6 to 12 feet.
7. For really long distances (up to 100 feet) use shielded
twisted pair such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D- and the shield
to GND close to the ADT7316/17/18. Leave the re-
mote end of the shield unconnected to avoid ground
loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect
the measurement. When using long cables, the filter ca-
pacitor may be reduced or removed.
Cable resistance can also introduce errors. 1 series resis-
tance introduces about 0.5
o
C error.
TEMPERATURE VALUE FORMAT
One LSB of the ADC corresponds to 0.25C. The ADC
can theoretically measure a temperature span of 255 C.
The internal temperature sensor is guaranteed to a low
value limit of -40 C. It is possible to measure the full
temperature span using the external temperature sensor.
The temperature data format is shown in Tables 3.
The result of the internal or external temperature mea-
surements is stored in the temperature value registers, and
is compared with limits programmed into the Internal or
External High and Low Registers.
TABLE 3. Temperature Data Format (Internal and Ex-
ternal Temperature)
Temperature
Digital Output
DB9..........DB0
-40 C
11 0110 0000
N x I
I
V
DD
I
BIAS
TO A DC
V
OUT+
V
OUT-
BIAS
DIODE
INTERNAL
SENSE
TRA NSISTOR
Figure 11. Top Level Structure of Internal Temperature Sensor
18 REV. P
rN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
-25 C
11 1001 1100
-10 C
11 1101 1000
-0.25 C
11 1111 1111
0 C
00 0000 0000
+0.25 C
00 0000 0001
+10 C
00 0010 1000
+25 C
00 0110 0100
+50 C
00 1100 1000
+75 C
01 0010 1100
+100 C
01 1001 0000
+105 C
01 1010 0100
+125 C
01 1111 0100
Temperature Conversion Formula:
1. Positive Temperature = ADC Code/4
2. Negative Temperature = (ADC Code* - 512)/4
*DB9 is removed from the ADC Code
INTERRUPTS
The measured results from the inetrnal temperature sen-
sor, external temperature sensor and the V
DD
pin are com-
pared with the T
HIGH
/V
HIGH
and T
LOW
/V
LOW
limits. These
limits are stored in on-chip registers. Please note that the
limit registers are 8 bits long while the conversion results
are 10 bits long. If the limits are not masked out then any
out of limit comparisons generate flags that are stored in
Interrupt Status 1 Register (address = 00h) and Interrupt
Status 2 Register (address = 01h). One or more out-of
limit results will cause the INTERRUPT output to pull
either high or low depending on the output polarity set-
ting.
Figure 13 shows the interrupt structure for the ADT7316/
17/18. It gives a block diagram representation of how the
various measurement channels affect the INTERRUPT
pin.
THERMAL VOLTAGE OUTPUT
The ADT7316/17/18 has the capability of outputting a
voltage that is proportional to temperature. DAC A output
can be configured to reperesent the temperature of the
internal sensor while DAC B output can be configured to
reperesent the external temperature sensor. Bits 5 and 6 of
Control Configuration 3 register select the temperature
proportional output voltage. Each time a temperature
measurement is taken the DAC output is updated. The
output resolution ADT7318 is 8 bits with 1C change
corresponding to one LSB change. The output resolution
for the ADT7316 and ADT7317 is capable of 10 bits with
0.25C change corresponding to one LSB change. The
default output resolution for the ADT7316 and ADT7317
is 8 bits. To increase this to 10 bits, set bit 1=1 of Con-
trol Configuration 3 register. The default output range is
0V-V
REF
and this can be increased to 0V-2V
REF
. Increasing
the outout voltage span to 2V
REF
can be done by setting
D0 = 1 for DAC A (Internal Temperature Sensor) and
D1 = 1 for DAC B (External Temperature Sensor) in
DAC Configuration register (address 1Bh).
The output voltage is capable of tracking a max tempera-
ture range of -128C to +127C but the default setting is -
40C to +127C. If the output voltage range is 0V-V
REF
CONTROL
CONFIGURATION
REGISTER 1
INTERRUPT
MASK
REGISTERS
S
T
A
T
U
S
B
I
T
S
INTERRUPT
STATUS
REGISTER 1
(TEMP and Ext.
Diode Check)
WATCHDOG
LIMIT
COMPA RISONS
External
Tem p
V
DD
Diode
Fault
INTERRUPT
ENABLE BIT
INTERRUPT
(Latched Output)
Read Reset
S/W Reset
S
T
A
T
U
S
B
I
T
INTERRUPT
STATUS
REGISTER 2
(V
D D
)
Internal
Temp
Figure 13. ADT7316/17/18 Interrupt Structure
ADT7316/7317/7318
19
REV. PrN
PRELIMINARY TECHNICAL DATA
(V
REF
= 2.25 V) then this corresponds to 0V representing -
40C and 1.48V representing +127C. This of course will
give an upper deadband between 1.48V and V
REF
.
The Internal and External Analog Temperature Offset
registers can be used to vary this upper deadband and con-
sequently the temperature that 0V corresponds to. Tables
4 and 5 give examples of how this is done using a DAC
output voltage span of V
REF
and 2V
REF
respectivily. Simply
write in the temperature value, in 2's complement format,
that you want 0V to start at. For example, if you are using
the DAC A output and you want 0V to start at -40C then
program D8h into the Internal Analog Temperature Off-
set register (address 21h). This is an 8-bit register and
thus only has a temperature offset resolution of 1C for all
device models. Use the following formulas to determine
the value to program into the offset registers.
Negative temperatures : -
Offset Register Code(d)* = (0V Temp) + 128
*D7 of Offset Register Code is set to 1 for negative temperatures.
Example : -
Offset Register Code(d) = (-40) + 128
= 88d = 58h
Since a negative temperature has been inputted into the
equation, DB7 (MSB) of the Offset Register code is set to
a 1. Therefore 58h becomes D8h.
58h + DB7(1)
D8h
Positive temperatures : -
Offset Register Code(d) = 0V Temp
Example : -
Offset Register Code (d) = 10d = 0Ah
Table 4. Thermal Voltage Output (0V-V
REF
)
O/P Voltage
Default C
Max C
Sample C
0 V
-40
-128
0
0.5V
+17
-71
+56
1 V
+73
-15
+113
1.12V
+87
- 1
+127
1.47V
+127
+39
U D B *
1.5V
U D B *
+42
U D B *
2 V
U D B *
+99
U D B *
2.25V
U D B *
+127
U D B *
* Upper deadband has been reached. DAC output is not capable of increasing.
Reference Figure 6.
Table 5. Thermal Voltage Output, (0V-2V
REF
)
O/P Voltage
Default C
Max C
Sample C
0 V
-40
-128
0
0.25V
-26
-114
14
0.5V
+12
-100
+28
0.75V
+ 3
-85
43
1 V
+17
-71
+57
1.12V
+23
-65
+63
1.47V
+43
-45
+83
1.5V
+45
-43
+85
2 V
+73
-15
+113
2.25V
+88
0
+127
2.5V
+102
+14
U D B *
2.75V
+116
+28
U D B *
3 V
U D B *
+42
U D B *
3.25V
U D B *
+56
U D B *
3.5V
U D B *
+70
U D B *
3.75V
U D B *
+85
U D B *
4 V
U D B *
+99
U D B *
4.25V
U D B *
+113
U D B *
4.5V
U D B *
+127
U D B *
* Upper deadband has been reached. DAC output is not capable of increasing.
Reference Figure 6.
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output :-
8-Bit Temp = (DAC O/P
1 LSB) + ( 0V Temp)
For example, if the output is 1.5V, V
REF
= 2.25 V, 8-bit
DAC has an LSB size = 2.25V/255 = 8.82x10
-3
, and 0V
Temp is at -128C then the resultant temperature works
out to be :-
(1.5
8.82x10
-3
) + (-128) = +42C
The following equation is used to work out the various
temperatures for the corresponding 10-bit DAC output :-
10-Bit Temp = ((DAC O/P
1 LSB)x0.25) + ( 0V Temp)
For example, if the output is 0.4991V, V
REF
= 2.25 V, 10-
bit DAC has an LSB size = 2.25V/1024 = 2.197x10
-3
, and
0V Temp is at -40C then the resultant temperature works
out to be :-
((0.4991
2.197x10
-3
)x0.25) + (-40) = +16.75C
Figure 14 shows a graph of DAC output vs temperature
for a V
REF
= 2.25 V.
20 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.65
1.80
1.95
2.10
2.25
127
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-128
Temperature ('C)
DA
C
O
U
TP
UT
(
V
)
0 V = 0'C
0 V = -40'C
0 V = -128'C
Figure 14. DAC Output vs Temperature, V
REF
= 2.25 V
ADT7316/7317/7318 REGISTERS
The ADT7316/17/18 contains registers that are used to
store the results of external and internal temperature mea-
surements, V
DD
value measurements, high and low tem-
perature and supply voltage limits, set output DAC
voltage levels, configure multipurpose pins and generally
control the device. A description of these registers follows.
The register map is divided into registers of 8-bits long.
Each register has it's own indvidual address but some
consist of data that is linked with other registers. These
registers hold the 10-bit conversion results of measure-
ments taken on the Temperature and V
DD
channels. For
example, the 8 MSBs of the V
DD
measurement are stored
in register address 06h while the 2 LSBs are stored in
register address 03h. The link involved between these
types of registers is that when the LSB register is read first
then the MSB registers associated with that LSB register
are locked to prevent any updates. To unlock these MSB
registers the user has only to read any one of them, which
will have the affect of unlocking all previously locked
MSB registers. So for the example given above if register
03h was read first then MSB registers 06h and 07h would
be locked to prevent any updates to them. If register 06h
was read then this register and register 07h would be sub-
sequently unlocked.
1st READ
COMMAND
LSB
REGISTER
OUTPUT
DATA
LOCK ASSOCIATED
MSB REGISTERS
Figure 15. Phase 1 of 10-Bit Read
2nd READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
UNLOCK ASSOCIATED
MSB REGISTERS
Figure 16. Phase 2 of 10-Bit Read
If an MSB register is read first, it's corresponding LSB
register is not locked thus leaving the user with the option
of just reading back 8 bits (MSB) of a 10-bit conversion
result. Reading an MSB register first does not lock up
other MSB registers and likewise reading an LSB register
first does not lock up other LSB registers.
Table 6. List of ADT7316/7317/7318 Registers
RD/WR
Name
Power-on
Address
Default
00h
Interrupt Status 1
00h
01h
Interrupt Status 2
00h
02h
RESERVED
03h
Internal Temp & V
DD
LSBs
00h
04h
External Temp LSBs
00h
05h
RESERVED
06h
V
DD
MSBs
00h
07h
Internal Temperature MSBs
00h
08h
External Temp MSBs
00h
09h-0Fh
RESERVED
10h
DAC A LSBs (ADT7316/17 only)
00h
11h
DAC A MSBs
00h
12h
DAC B LSBs (ADT7316/17 only)
00h
13h
DAC B MSBs
00h
14h
DAC C LSBs (ADT7316/17 only)
00h
15h
DAC C MSBs
00h
16h
DAC D LSBs (ADT7316/17 only)
00h
17h
DAC D MSBs
00h
18h
Control CONFIG 1
00h
19h
Control CONFIG 2
00h
1Ah
Control CONFIG 3
00h
1Bh
DAC CONFIG
00h
1Ch
LDAC CONFIG
00h
1Dh
Interrupt Mask 1
00h
1Eh
Interrput Mask 2
00h
1Fh
Internal Temp Offset
00h
20h
External Temp Offset
00h
21h
Internal Analog Temp Offset
D8h
ADT7316/7317/7318
21
REV. PrN
PRELIMINARY TECHNICAL DATA
22h
External Analog Temp Offset
D8h
23h
V
DD
V
HIGH
Limit
C9h
24h
V
DD
V
LOW
Limit
62h
25h
Internal T
HIGH
Limit
64h
26h
Internal T
LOW
Limit
C9h
27h
External T
HIGH
F F h
28h
External T
LOW
00h
29h-4CH
RESERVED
4Dh
Device ID
01h/05h/09h
4Eh
Manufacturer's ID
41h
4Fh
Silicon Revision
00h
50h-FFh
RESERVED
Interrupt Status 1 Register (Read only) [Add. = 00h]
This 8-bit read only register reflects the status of some of
the interrupts that can cause the INTERRUPT pin to go
active. This register is reset by a read operation or by a
software reset.
Table 7. Interrupt Status 1 Register
D7
D6
D5
D4
D3
D2
D1
D0
N / A
N / A
N / A
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
D 0
1 when Internal Temp Value exceeds T
HIGH
limit
D 1
1 when Internal Temp Value exceeds T
LOW
limit
D 2
1 when External Temp Value exceeds T
HIGH
limit
D 3
1 when External Temp Value exceeds T
LOW
limit
D 4
1 indicates a fault (open or short) for the external
temperature sensor.
Interrupt Status 2 Register (Read only) [Add. = 01h]
This 8-bit read only register reflects the status of the V
DD
interrupt that can cause the INTERRUPT pin to go ac-
tive. This register is reset by a read operation or by a soft-
ware reset.
Table 8. Interrupt Status 1 Register
D7
D6
D5
D4
D3
D2
D1
D0
N / A
N / A
N / A
0 *
N / A
N / A
N / A
N / A
*Default settings at Power-up.
Bit
Function
D 4
1 when V
DD
value exceeds corrosponding V
HIGH
and
V
LOW
limits
INTERNAL TEMPERATURE VALUE/V
DD
VALUE REG-
ISTER LSBs (Read only) [Add. = 03h]
This Internal Temperature Value and V
DD
Value Register
is a 8-bit read-only register. It stores the two LSBs of the
10-bit temperature reading from the internal temperature
sensor and also the two LSBs of the 10-bit supply voltage
reading.
Table 9. Internal Temp/V
DD
LSBs
D7
D6
D5
D4
D3
D2
D1
D0
N / A
N / A
N / A
N / A
V 1
L S B
T 1
L S B
N / A
N / A
N / A
N / A
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
D 0
LSB of Internal Temperature Value
D 1
B1 of Internal Temperature Value
D 2
LSB of V
DD
Value
D 3
B1 of V
DD
Value
EXTERNAL TEMPERATURE VALUE REGISTER
LSBS (Read only) [Add. = 04h]
This External Temperature Value is a 8-bit read-only
register. It stores the two LSBs of the 10-bit temperature
reading from the external temperature sensor.
Table 10. External Temperature LSBs
D7
D6
D5
D4
D3
D2
D1
D0
N / A
N / A
N / A
N / A
N / A
N / A
T 1
L S B
N / A
N / A
N / A
N / A
N / A
N / A
0 *
0 *
*Default settings at Power-up.
Bit
Function
D 0
LSB of External Temperature Value
D 1
B1 of External Temperature Value
V
DD
VALUE REGISTER MSBS (Read only) [Add. = 06h]
This 8-bit read only register stores the supply voltage
value. The 8 MSBs of the 10-bit value are stored in this
register.
Table 11. V
DD
Value MSBs
22 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
D7
D6
D5
D4
D3
D2
D1
D0
V 9
V 8
V 7
V 6
V 5
V 4
V 3
V 2
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
INTERNAL TEMPERATURE VALUE REGISTER
MSBS (Read only) [Add. = 07h]
This 8-bit read only register stores the Internal Tempera-
ture value from the internal temperature sensor in twos
complement format. The 8 MSBs of the 10-bit value are
stored in this register.
Table 12. Internal Temperature Value MSBs
D7
D6
D5
D4
D3
D2
D1
D0
T 9
T 8
T 7
T 6
T 5
T 4
T 3
T 2
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
EXTERNAL TEMPERATURE VALUE REGISTER
MSBS (Read only) [Add. = 08h]
This 8-bit read only register stores the External Tempera-
ture value from the external temperature sensor in twos
complement format. The 8 MSBs of the 10-bit value are
stored in this register.
Table 13. External Temperature Value MSBs
D7
D6
D5
D4
D3
D2
D1
D0
T 9
T 8
T 7
T 6
T 5
T 4
T 3
T 2
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
DAC A REGISTER LSBS (Read/Write) [Add. = 10h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC A word respectivily. The value in
this register is combined with the value in the DAC A
Register MSBs and converted to an analog voltage on the
V
OUT
A pin. On power-up the voltage output on the V
OUT
A
pin is 0 V.
Table 14. DAC A (ADT7316) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 3
B 2
B 1
L S B
N / A
N / A
N / A
N / A
0 *
0 *
0 *
0 *
N / A
N / A
N / A
N / A
*Default settings at Power-up.
Table 15. DAC A (ADT7317) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 2
L S B
N / A
N / A
N / A
N / A
N / A
N / A
0 *
0 *
N / A
N / A
N / A
N / A
N / A
N / A
*Default settings at Power-up.
DAC A REGISTER MSBS (Read/Write) [Add. = 11h]
This 8-bit read/write register contains the 8 MSBs of the
DAC A word. The value in this register is combined with
the value in the DAC A Register LSBs and converted to
an analog voltage on the V
OUT
A pin. On power-up the
voltage output on the V
OUT
A pin is 0 V.
Table 16. DAC A MSBs
D7
D6
D5
D4
D3
D2
D1
D0
M S B
B 8
B 7
B 6
B 5
B 4
B 3
B 2
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
DAC B REGISTER LSBS (Read/Write) [Add. = 12h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC B word respectivily. The value in
this register is combined with the value in the DAC B
Register MSBs and converted to an analog voltage on the
V
OUT
B pin. On power-up the voltage output on the V
OUT
B
pin is 0 V.
Table 17. DAC B (ADT7316) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 3
B 2
B 1
L S B
N / A
N / A
N / A
N / A
0 *
0 *
0 *
0 *
N / A
N / A
N / A
N / A
*Default settings at Power-up.
Table 18. DAC B (ADT7317) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 2
L S B
N / A
N / A
N / A
N / A
N / A
N / A
0 *
0 *
N / A
N / A
N / A
N / A
N / A
N / A
*Default settings at Power-up.
DAC B REGISTER MSBS (Read/Write) [Add. = 13h]
This 8-bit read/write register contains the 8 MSBs of the
DAC B word. The value in this register is combined with
the value in the DAC B Register LSBs and converted to
an analog voltage on the V
OUT
B pin. On power-up the
voltage output on the V
OUT
B pin is 0 V.
Table 19. DAC B MSBs
D7
D6
D5
D4
D3
D2
D1
D0
M S B
B 8
B 7
B 6
B 5
B 4
B 3
B 2
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
DAC C REGISTER LSBS (Read/Write) [Add. = 14h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC C word respectivily. The value in
this register is combined with the value in the DAC C
Register MSBs and converted to an analog voltage on the
V
OUT
C pin. On power-up the voltage output on the V
OUT
C
pin is 0 V.
ADT7316/7317/7318
23
REV. PrN
PRELIMINARY TECHNICAL DATA
Table 20. DAC C (ADT7316) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 3
B 2
B 1
L S B
N / A
N / A
N / A
N / A
0 *
0 *
0 *
0 *
N / A
N / A
N / A
N / A
*Default settings at Power-up.
Table 21. DAC C (ADT7317) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 2
L S B
N / A
N / A
N / A
N / A
N / A
N / A
0 *
0 *
N / A
N / A
N / A
N / A
N / A
N / A
*Default settings at Power-up.
DAC C REGISTER MSBS (Read/Write) [Add. = 15h]
This 8-bit read/write register contains the 8 MSBs of the
DAC C word. The value in this register is combined with
the value in the DAC C Register LSBs and converted to
an analog voltage on the V
OUT
C pin. On power-up the
voltage output on the V
OUT
C pin is 0 V.
Table 22. DAC C MSBs
D7
D6
D5
D4
D3
D2
D1
D0
M S B
B 8
B 7
B 6
B 5
B 4
B 3
B 2
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
DAC D REGISTER LSBS (Read/Write) [Add. = 16h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC D word respectivily. The value in
this register is combined with the value in the DAC D
Register MSBs and converted to an analog voltage on the
V
OUT
D pin. On power-up the voltage output on the V
OUT
D
pin is 0 V.
Table 23. DAC D (ADT7316) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 3
B 2
B 1
L S B
N / A
N / A
N / A
N / A
0 *
0 *
0 *
0 *
N / A
N / A
N / A
N / A
*Default settings at Power-up.
Table 24. DAC D (ADT7317) LSBs
D7
D6
D5
D4
D3
D2
D1
D0
B 2
L S B
N / A
N / A
N / A
N / A
N / A
N / A
0 *
0 *
N / A
N / A
N / A
N / A
N / A
N / A
*Default settings at Power-up.
DAC D REGISTER MSBS (Read/Write) [Add. = 17h]
This 8-bit read/write register contains the 8 MSBs of the
DAC D word. The value in this register is combined with
the value in the DAC D Register LSBs and converted to
an analog voltage on the V
OUT
D pin. On power-up the
voltage output on the V
OUT
D pin is 0 V.
Table 25. DAC D MSBs
D7
D6
D5
D4
D3
D2
D1
D0
M S B
B 8
B 7
B 6
B 5
B 4
B 3
B 2
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
CONTROL CONFIGURATION 1 REGISTER (Read/
Write) [Add. = 18h]
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
Table 26. Control Configuration 1
D7
D6
D5
D4
D3
D2
D1
D0
P D
C 6
C 5
C 4
C 3
C 2
C 1
C 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
C 0
This bit enables/disables conversions in Round
Robin mode. ADT7316/17/18 powers up in
Round Robin mode but monitoring is not initi-
ated until this bit is set. Default = 0.
0 = Disable Round Robin monitoring.
1 = Enable Round Robin monitoring.
C1:4
RESERVED. Only write 0's.
C 5
0
Enable INTERRUPT
1
Disable INTERRUPT
C 6
Configures INTERRUPT output polarity.
0
Active low
1
Active High
C 7
Power-down Bit. Setting this bit to 1 puts the
ADT7316/17/18 into standby mode. In this
mode both ADC and DACs are fully powered
down, but serial interface is still operational. To
power up the part again just write 0 to this bit
.
CONTROL CONFIGURATION 2 REGISTER (Read/
Write) [Add. = 19h]
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
Table 27. Control Configuration 2
D7
D6
D5
D4
D3
D2
D1
D0
C 7
C 6
C 5
C 4
C 3
C 2
C 1
C 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
24 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
C2:0
In single channel mode these bits select between
V
DD
, the internal temperature sensor and the
external temperature sensor for conversion. De-
fault is V
DD
.
000 = V
DD
001 = Internal Temperature Sensor.
010 = External Temperature Sensor
011 - 111 = RESERVED
C 3
RESERVED
C 4
Selects between single channel and Round Robin
conversion cycle. Default is Round Robin.
0 = Round Robin.
1 = Single Channel.
C 5
Default condition is to average every measure-
ment on all channels 16 times. This bit disables
this averaging. Channels consist of temperature,
analog inputs and V
DD
.
0 = Enable averaging.
1 = Disable averaging.
C 6
SMBus timeout on the serial clock puts a max
limit on the pulse width of the clock. Ensures
that a fault on the master SCL does not lock up
the SDA line.
0 = Disable SMBus Timeout.
1 = Enable SMBus Timeout.
C 7
Software Reset. Setting this bit to a 1 causes a
software reset. All registers and DAC outputs
will reset to their default settings.
CONTROL CONFIGURATION 3 REGISTER (Read/
Write) [Add. = 1Ah]
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
Table 28. Control Configuration 3
D7
D6
D5
D4
D3
D2
D1
D0
C 7
C 6
C 5
C 4
C 3
C 2
C 1
C 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
C 0
Selects between fast and normal ADC conver-
sion speeds for all three monitoring channels.
0 = ADC clock at 1.4 KHz.
1 = ADC clock at 22.5 KHz.
C 1
On the ADT7316 and ADT7317, this bit selects
between 8 bits and 10 bits DAC output resolu-
tion on the Thermal Voltage Output feature.
Default = 8 bits. This bit has no affect on the
ADT7318 output as this part has only an 8-bit
DAC. In the ADT7318 case, write 0 to this bit.
0 = 8 bits resolution.
1 = 10 bits resolution.
C 2
RESERVED. Only write 0's.
C 3
0 =
LDAC pin controls updating of DAC out-
puts.
1 = DAC Configration register and LDAC Con-
figuration register control updating of DAC
outputs.
C 4
RESERVED. Only write 0.
C 5
Setting this bit selects DAC A voltage output to
be proportional to the internal temperature mea-
surement.
C 6
Setting this bit selects DAC B voltage output to
be proportional to the external temperature mea-
surement.
C 7
RESERVED. Only write 0.
DAC CONFIGURATION REGISTER (Read/Write)
[Add. = 1Bh]
This configuration register is an 8-bit read/write register
that is used to control the output ranges of all four DACs
and also to control the loading of the DAC registers if the
LDAC pin is disabled (bit C3 = 1, Control Configuration
3 register).
Table 29. DAC Configuration
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
D 0
Selects the output range of DAC A.
0 = 0 V to V
REF
.
1 = 0 V to 2V
REF
.
D 1
Selects the output range of DAC B.
0 = 0 V to V
REF
.
1 = 0 V to 2V
REF
.
D 2
Selects the output range of DAC C.
0 = 0 V to V
REF
.
1 = 0 V to 2V
REF
.
D 3
Selects the output range of DAC D.
0 = 0 V to V
REF
.
1 = 0 V to 2V
REF
.
D5:D4
00
MSB write to any DAC register generates
LDAC command which updates that
DAC only.
01
MSB write to DAC B or DAC D register
generates LDAC command which up-
dates DACs A, B or DACs C, D.
10
MSB write to DAC D register generates
LDAC command which updates all 4
DACs.
11
LDAC command generated from LDAC
register.
ADT7316/7317/7318
25
REV. PrN
PRELIMINARY TECHNICAL DATA
D 6
Setting this bit allows the external V
REF
to bypass
the reference buffer when supplying DACs A
and B.
D 7
Setting this bit allows the external V
REF
to bypass
the reference buffer when supplying DACs C
and D.
LDAC CONFIGURATION REGISTER (Write only)
[Add. = 1Ch]
This configuration register is an 8-bit write register that is
used to control the updating of the quad DAC outputs if
the
LDAC pin is disabled and Bits 4 and 5 of DAC Con-
figuration register are both set to 1. Also selects V
REF
for
all four DACs. All of the bits in this register are self clear-
ing i.e. reading back from this register will always give
0's.
Table 30. LDAC Configuration
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
D 0
Writing a 1 to this bit will generate the LDAC
command to update DAC A output only.
D 1
Writing a 1 to this bit will generate the LDAC
command to update DAC B output only.
D 2
Writing a 1 to this bit will generate the LDAC
command to update DAC C output only.
D 3
Writing a 1 to this bit will generate the LDAC
command to update DAC D output only.
D 4
Selects either internal or external V
REF
AB for
DACs A and B.
0 = External V
REF
1 = Internal V
REF
D 5
Selects either internal or external V
REF
CD for
DACs C and D.
0 = External V
REF
1 = Internal V
REF
D6:D7
RESERVED. Only write 0's.
INTERRUPT MASK 1 REGISTER (Read/Write) [Add. =
1Dh]
This mask register is an 8-bit read/write register that can
be used to mask out any interrupts that can can cause the
INTERRUPT pin to go active.
Table 31. Interrupt Mask 1
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
D 0
0 = Enable internal T
HIGH
interrupt.
1 = Disable internal T
HIGH
interrupt.
D 1
0 = Enable internal T
LOW
interrupt.
1 = Disable internal T
LOW
interrupt.
D 2
0 = Enable external T
HIGH
interrupt.
1 = Disable external T
HIGH
interrupt.
D 3
0 = Enable external T
low
interrupt.
1 = Disable external T
low
interrupt.
D 4
0 = Enable external temperature fault interrupt.
1 = Disable external temperature fault interrupt.
D5:D7
RESERVED. Only write 0's.
INTERRUPT MASK 2 REGISTER (Read/Write) [Add. =
1Eh]
This mask register is an 8-bit read/write register that can
be used to mask out any interrupts that can can cause the
INTERRUPT pin to go active.
Table 32. Interrupt Mask 2
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
Bit
Function
D0:D3
RESERVED. Only write 0's.
D 4
0 = Enable V
DD
interrupts.
1 = Disable V
DD
interrupts.
D5:D7
RESERVED. Only write 0's.
INTERNAL TEMPERATURE OFFSET REGISTER
(Read/Write) [Add. = 1Fh]
This register contains the Offset Value for the Internal
Temperature Channel. A 2's complement number can be
written to this register which is then 'added' to the mea-
sured result before it is stored or compared to limits. In
this way a sort of one-point calibration can be done
whereby the whole transfer function of the channel can be
moved up or down. From a software point of view this
may be a very simple method to vary the characteristics of
the measurement channel if the thermal characteristics
change. As it is an 8-bit register the temperature resolu-
tion is 1
o
C.
Table 33. Internal Temperature Offset
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
26 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
EXTERNAL TEMPERATURE OFFSET REGISTER
(Read/Write) [Add. = 20h]
This register contains the Offset Value for the Internal
Temperature Channel. A 2's complement number can be
written to this register which is then 'added' to the mea-
sured result before it is stored or compared to limits. In
this way a sort of one-point calibration can be done
whereby the whole transfer function of the channel can be
moved up or down. From a software point of view this
may be a very simple method to vary the characteristics of
the measurement channel if the thermal characteristics
change. As it is an 8-bit register the temperature resolu-
tion is 1
o
C.
Table 34. External Temperature Offset
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
INTERNAL ANALOG TEMPERATURE OFFSET
REGISTER (Read/Write) [Add. = 21h]
This register contains the Offset Value for the Internal
Thermal Voltage output. A 2's complement number can
be written to this register which is then 'added' to the mea-
sured result before it is converted by DAC A. Varying the
value in this register has the affect of varying the tempera-
ture span. For example, the output voltage can represent a
temperature span of -128
o
C to +127
o
C or even 0
o
C to
+127
o
C. In essence this register changes the position of
0V on the temperature scale. Anything other than -128
o
C
to +127
o
C will produce an upper deadband on the DAC A
output. As it is an 8-bit register the temperature resolution
is 1
o
C. Default value is -40
o
C.
Table 35. Internal Analog Temperature Offset
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
1 *
1 *
0 *
1 *
1 *
0 *
0 *
0 *
*Default settings at Power-up.
EXTERNAL ANALOG TEMPERATURE OFFSET
REGISTER (Read/Write)[Add. = 22h]
This register contains the Offset Value for the External
Thermal Voltage output. A 2's complement number can
be written to this register which is then 'added' to the mea-
sured result before it is converted by DAC B. Varying the
value in this register has the affect of varying the tempera-
ture span. For example, the output voltage can represent a
temperature span of -128
o
C to +127
o
C or even 0
o
C to
+127
o
C. In essence this register changes the position of
0V on the temperature scale. Anything other than -128
o
C
to +127
o
C will produce an upper deadband on the DAC B
output. As it is an 8-bit register the temperature resolution
is 1
o
C. Default value is -40
o
C.
Table 36. External Analog Temperature Offset
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
1 *
1 *
0 *
1 *
1 *
0 *
0 *
0 *
*Default settings at Power-up.
V
DD
V
HIGH
LIMIT REGISTER (Read/Write) [Add. = 23h]
This limit register is an 8-bit read/write register which
stores the V
DD
upper limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured V
DD
value has to be greater than the
value in this register. Default value is 5.5 V.
Table 37. V
DD
V
HIGH
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
1 *
1 *
0 *
0 *
1 *
0 *
0 *
1 *
*Default settings at Power-up.
V
DD
V
LOW
LIMIT REGISTER (Read/Write) [Add. = 24h]
This limit register is an 8-bit read/write register which
stores the V
DD
lower limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured V
DD
value has to be less than the
value in this register. Default value is 2.7 V.
Table 38. V
DD
V
HIGH
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
1 *
1 *
0 *
0 *
0 *
1 *
0 *
*Default settings at Power-up.
INTERNAL T
HIGH
LIMIT REGISTER (Read/Write) [Add.
= 25h]
This limit register is an 8-bit read/write register which
stores the 2's complement of the internal temperature
upper limit that will cause an interrupt and activate the
INTERRUPT output (if enabled). For this to happen the
measured Internal Temperature Value has to be greater
than the value in this register. As it is an 8-bit register the
temperature resolution is 1
o
C. Default value is +100
o
C.
Table 39. Internal T
HIGH
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0 *
1 *
1 *
0 *
0 *
1 *
0 *
0 *
*Default settings at Power-up.
INTERNAL T
LOW
LIMIT REGISTER (Read/Write) [Add.
26h]
This limit register is an 8-bit read/write register which
stores the 2's complement of the internal temperature
lower limit that will cause an interrupt and activate the
INTERRUPT output (if enabled). For this to happen the
measured Internal Temperature Value has to be more
ADT7316/7317/7318
27
REV. PrN
PRELIMINARY TECHNICAL DATA
negative than the value in this register. As it is an 8-bit
register the temperature resolution is 1
o
C. Default value is
-55
o
C.
Table 40. Internal T
LOW
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
1 *
1 *
0 *
0 *
1 *
0 *
0 *
1 *
*Default settings at Power-up.
EXTERNAL T
HIGH
LIMIT REGISTER (Read/Write) [Add.
= 27h]
If pins 7 and 8 are configured for the external temperature
sensor then this limit register is an 8-bit read/write regis-
ter which stores the 2's complement of the external tem-
perature upper limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured External Temperature Value has to
be greater than the value in this register. As it is an 8-bit
register the temperature resolution is 1
o
C.
Table 41. External T
HIGH
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
1 *
1 *
1 *
1 *
1 *
1 *
1 *
1 *
*Default settings at Power-up.
EXTERNAL T
LOW
LIMIT REGISTER (Read/Write) [Add.
= 28h]
If pins 7 and 8 are configured for the external temperature
sensor then this limit register is an 8-bit read/write regis-
ter which stores the 2's complement of the external tem-
perature lower limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured External Temperature Value has to
be more negative than the value in this register. As it is an
8-bit register the temperature resolution is 1
o
C.
Table 42. External T
LOW
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
R/
9
1
SCL
SDA
0
0
1
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
ACK. BY
ADT7316/17/18
STOP BY
MASTER
START BY
MASTER
FR AME 1
SERIAL BUS ADDRESS B YTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
1
ACK. BY
ADT7316/17/18
9
R/
9
1
SCL
SDA
0
0
1
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
ACK. BY
ADT7316/17/18
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS B YTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
1
ACK. BY
ADT7316/17/18
9
D 7
D 6
D5
D 4
D3
D 2
D 1
D0
ACK. BY
ADT7316/17/18
STOP BY
MASTER
FRAME 3
DATA BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
Figure 18. I
2
C - Writing to the Address Pointer Register followed by a single byte of data to the selected register
Figure 17. I
2
C - Writing to the Address Pointer Register to select a register for a subsequent Read operation
28 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
*Default settings at Power-up.
DEVICE ID REGISTER (READ ONLY) [ADD. = 4DH]
This 8-bit read only register indicates which part the de-
vice is in the model range. ADT7316 = 01h, ADT7317 =
05h and ADT7318 = 09h.
MANUFACTURER'S ID REGISTER (Read only) [Add.
= 4Eh]
This register contains the manufacturers identification
number. ADI's is 41h.
SILICON REVISION REGISTER (Read only) [Add. =
4Fh]
This register is divided into the four lsbs representing the
Stepping and the four msbs representing the Version. The
Stepping contains the manufacturers code for minor revi-
sions or steppings to the silicon. The Version is the
ADT7316/17/18 version number. The ADT7316/17/18's
version number is 0000b.
ADT7316/7317/7318 SERIAL INTERFACE
There are two serial interfaces that can be used on this
part, I
2
C and SPI. A valid serial communication protocol
selects the type of interface.
SERIAL INTERFACE SELECTION
The
CS line controls the selection between I
2
C and SPI. If
CS is held high during a valid I
2
C communication then
the serial interface selects the I
2
C mode once the correct
serial bus address has been recognised.
To set the interface to SPI mode the
CS line must be low
during a valid SPI communication. This will cause the
interface to select the SPI mode once the correct read or
write command has been recognised. As per most SPI
standards the
CS line must be low during every SPI com-
munication to the ADT7316/17/18 and high all other
times.
Figure 20. SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register
D7
D 6
D 5
D4
D 3
D2
D1
D 0
DATA BYTE
1
8
D
IN
(CONTINUED)
SCL K (CONTINUED)
CS (CONTINUED)
D7
SCL K
D
I N
D6
D5
D4
D3
D2
D1
D6
D5
D4
D3
D2
D 1
D 0
START
WRITE COMMAND
REGISTER ADDRESS
1
8
1
8
CS
D0
D7
SDA
NO ACK. BY
MASTER
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRA ME 2
SINGL E DATA BYTE FROM ADT7316/17/18
ACK. BY
ADT7316/17/18
1
9
1
9
D7
D6
D5
D4
D3
D2
D1
D0
R/
9
A0
A1
A2
1
0
1
SCL
STOP BY
MASTER
0
Figure 19. I
2
C - Reading a single byte of data from a selected register
ADT7316/7317/7318
29
REV. PrN
PRELIMINARY TECHNICAL DATA
The following sections describe in detail how to use these
interfaces.
I
2
C SERIAL INTERFACE
Like all I
2
C-compatible devices, the ADT7316/7317/7318
has an 7-bit serial address. The four MSBs of this address
for the ADT7316/7317/7318 are set to 1001. The three
LSBs are set by pin 11, ADD. The ADD pin can be con-
figured three ways to give three different address options;
low, floating and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
address 1001 010 and setting it high gives the address
1001 011.
There is a programmable SMBus timout. When this is
enabled the SMBus will timeout after 25 ms of no activity.
To enable it, set Bit 6 of Control Configuration 2 regis-
ter. The power-up default is with the SMBus timeout
disabled.
The ADT7316/17/18 supports SMBus Packet Error
Checking (PEC) and it's use is optional. It is triggered by
supplying the extra clocks for the PEC byte. The PEC is
calculated using CRC-8. The Frame Clock Sequence
(FCS) conforms to CRC-8 by the polynominal :
C(x) = x
8
+ x
2
+ x
1
+ 1
Consult SMBus specification for more information.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. This indicates that an address/data
stream will follow. All slave peripherals connected to
the serial bus respond to the START condition, and
shift in the next 8 bits, consisting of a 7-bit address
(MSB first) plus a R/
W bit, which determines the direc-
tion of the data transfer, i.e. whether data will be writ-
ten to or read from the slave device.
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices on the
bus now remain idle whilst the selected device waits for
data to be read from or written to it. If the R/
W bit is a
0 then the master will write to the slave device. If the
R/
W bit is a 1 the master will read from the slave de-
vice.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the receiver of data. Transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
high transition when the clock is high may be inter-
preted as a STOP signal.
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the mas-
ter device will pull the data line high during the low
period before the 9th clock pulse. This is known as No
Acknowledge. The master will then take the data line
low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation, because the type of opera-
tion is determined at the beginning and cannot subse-
quently be changed without starting a new operation.
WRITING TO THE ADT7316/7317/7318
Depending on the register being written to, there are two
different writes for the ADT7316/7317/7318. It is not
possible to do a block write to this part i.e no I
2
C auto-
increment.
Writing to the Address Pointer Register for a subsequent
read.
In order to read data from a particular register, the Ad-
dress Pointer Register must contain the address of that
register. If it does not, the correct address must be written
to the Address Pointer Register by performing a single-
byte write operation, as shown in Figure 17. The write
operation consists of the serial bus address followed by the
address pointer byte. No data is written to any of the data
registers. A read operation is then performed to read the
register.
Figure 21. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation
D7
SCL K
D
I N
D6
D5
D4
D3
D2
D1
D6
D5
D 4
D3
D 2
D1
D 0
START
WRITE COMMAND
REGISTER ADDRESS
1
8
1
8
CS
D0
D7
STOP
30 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Writing data to a Register.
All registers are 8-bit registers so only one byte of data
can be written to each register. Writing a single byte of
data to one of these Read/Write registers consists of the
serial bus address, the data register address written to the
Address Pointer Register, followed by the data byte written
to the selected data register. This is illustrated in Figure
18. To write to a different register, another START or
repeated START is required. If more than one byte of
data is sent in one communication operation, the ad-
dressed register will be repeately loaded until the last data
byte has been sent.
READING DATA FROM THE ADT7316/7317/7318
Reading data from the ADT7516/7517/7518 is done in a
one byte operation. Reading back the contents of a register
is shown in Figure 19. The register address previously
Figure 23. SPI - Reading a two bytes of data from two sequential registers
Figure 22. SPI - Reading a single byte of data from a selected register
D7
D
I N
D6
D5
D4
D3
D 2
D1
X
X
X
X
X
X
X
D0
X
SCLK
START
READ COMMAND
DATA BYTE 1
1
8
1
8
CS
X
D
OUT
X
X
X
X
X
X
D6
D 5
D4
D 3
D2
D 1
D 0
X
D7
STOP
D7
D
IN
D6
D5
D4
D3
D2
D1
X
X
X
X
X
X
X
D0
X
SCLK
START
READ COMMAND
DATA BYTE 1
1
8
1
8
CS
X
D
OUT
X
X
X
X
X
X
D6
D 5
D 4
D 3
D 2
D1
D 0
X
D7
STOP
DATA BYTE 2
X
X
X
X
X
X
X
X
D
IN
(CONTINUED)
1
8
SCLK (CONTINUED)
CS (CONTINUED)
D 7
D 6
D 5
D4
D 3
D 2
D1
D 0
D
OUT
(CONTINUED)
having been set up by a single byte write operation to the
Address Pointer Register. If you want to read from another
register then you will have to write to the Address Pointer
Register again to set up the relevant register address. Thus
block reads are not possible i.e. no I
2
C auto-increment.
SPI SERIAL INTERFACE
The SPI serial interface of the ADT7316/7317/7318 con-
sists of four wires,
CS, SCLK, DIN and DOUT. The CS
is used to select the device when more than one device is
connected to the serial clock and data lines. The SCLK is
used to clock data in and out of the part. The DIN line is
used to write to the registers and the DOUT line is used
to read data back from the registers.
The part operates in a slave mode and requires an exter-
nally applied serial clock to the SCLK input. The serial
ADT7316/7317/7318
31
REV. PrN
PRELIMINARY TECHNICAL DATA
interface is designed to allow the part to be interfaced to
systems that provide a serial clock that is synchronized to
the serial data.
There are two types of serial operations, a read and a
write. Command words are used to distinguish between a
read and a write operation. These command words are
given in Table 43. Address auto-increment is possible in
SPI mode
Table 43. SPI COMMAND WORDS
WRITE
READ
90h (1001 0000)
91h (1001 0001)
Write Operation
Figures 20 and 21 show the timing diagrams for a write
operation to the ADT7316/7317/7318. Data is clocked
into the registers on the rising edge of SCLK. When the
CS line is high the DIN and DOUT lines are in three-
state mode. Only when the
CS goes from a high to a low
does the part accept any data on the DIN line. In SPI
mode the Address Pointer Register is capable of auto-
incrementing to the next register in the register map with-
out having to load the Address Pointer register each time.
In Figure 20 the register address portion of the diagram
gives the first register that will be written to. Subsequent
data bytes will be written into sequential writable registers.
Thus after each data byte has been written into a register,
the Address Pointer Register auto increments it's value to
the next available register. The Address Pointer Register
will auto-increment from 00h to 3Fh and will loop back
to start all over again at 00h when it reaches 3Fh.
Read Operation
Figures 22 and 23 show the timing diagrams necessary to
accomplish correct read operations. To read back from a
register you first have to write to the Address Pointer Reg-
ister with the address of the register you wish to read
from. This operation is shown in Figure 21. Figure 22
shows the procedure for reading back a single byte of data.
The read command is first sent to the part during the first
8 clock cycles, during the following 8 clock cycles the
data contained in the register selected by the Address
Pointer register is outputted onto the DOUT line. Data is
outputted onto the DOUT line on the falling edge of
SCLK. Figure 23 shows the procedure when reading data
from two sequential registers. Multiple data reads are
possible in SPI interface mode as the Address Pointer
Register is auto-incremental. The Address Pointer Regis-
ter will auto-increment from 00h to 3Fh and will loop
back to start all over again at 00h when it reaches 3Fh.
SMBUS/SPI INTERRUPT
The ADT7316/17/18 INTERRUPT output is an interrupt
line for devices that want to trade their ability to master
for an extra pin. The ADT7316/17/18 is a slave only de-
vice and uses the SMBus/SPI INTERRUPT to signal the
host device that it wants to talk. The SMBus/SPI INTER-
RUPT on the ADT7316/17/18 is used as an over/under
limit indicator.
The INTERRUPT pin has an open-drain configuration
which allows the outputs of several devices to be wired-
AND together when the INTERRUPT pin is active low.
Use D6 of the Control Configuration 1 Register to set the
active polarity of the INTERRUPT output. The power-up
default is active low. The INTERRUPT function can be
disabled or enabled by setting D5 of Control Configura-
tion 1 Register to a 1 or 0 respectively.
The INTERRUPT output becomes active when either the
Internal Temperature Value, the External Temperature
Value or the V
DD
Value exceed the values in their corre-
sponding T
HIGH
/V
HIGH
or T
LOW
/V
LOW
Registers. The IN-
TERRUPT output goes inactive again when a conversion
result has the measured value back within the trip limits.
The INTERRUPT output requires an external pull-up
resistor. This can be connected to a voltage different from
V
DD
provided the maximum voltage rating of the INTER-
RUPT output pin is not exceeded. The value of the pull-
up resistor depends on the application, but should be as
large enough to avoid excessive sink currents at the IN-
TERRUPT output, which can heat the chip and affect the
temperature reading.
32 REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Outline Dimensions
(Dimensions shown in inches and mm )
16-Lead QSOP Package
( RQ-16 )
1 6
9
8
1
0.19 7 (5.00)
0.18 9 (4.80)
0.24 4 (6.20)
0.22 8 (5.79)
P IN 1
0.157 (3.99)
0.150 (3.81)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0 .012 (0.30 )
0 .008 (0.20 )
0.025
(0.64)
BSC
0 .059 (1.50 )
MAX
0.069 (1.75)
0.053 (1.35)
0.010 (0.20)
0.007 (0.18)
8
o
0
o
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