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SPI
/I
2
C
Compatible, 10-Bit Digital
Temperature Sensor and 8-Channel ADC
ADT7411
*
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
10-bit temperature-to-digital converter
10-bit 8-channel ADC
DC input bandwidth
Input range: 0 V to 2.25 V, and 0 V to V
DD
Temperature range: 40C to +120C
Temperature sensor accuracy of 0.5C
Supply range: 2.7 V to 5.5 V
Power-down current 1 A
Internal 2.25 V
REF
option
Double-buffered input logic
I
2
C, SPI, QSPITM, MICROWIRETM, and DSP compatible
4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP package
APPLICATIONS
Portable battery-powered instruments
Personal computers
Smart battery chargers
Telecommunications systems electronic test equipment
Domestic appliances
Process control
PIN CONFIGURATION
02882-A
-
005
ADT7411
TOP VIEW
(Not to Scale)
AIN6
1
AIN7
16
AIN5
2
AIN8
15
NC
3
AIN4
14
CS
4
SCL/SCLK
13
GND
5
SDA/DIN
12
V
DD
6
DOUT/ADD
11
D+/AIN1
7
INT/INT
10
D/AIN2
8
AIN3
9
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION
The ADT7411 combines a 10-bit temperature-to-digital con-
verter and a 10-bit 8-channel ADC in a 16-lead QSOP package.
This includes a band gap temperature sensor and a 10-bit ADC
to monitor and digitize the temperature reading to a resolution
of 0.25C. The ADT7411 operates from a single 2.7 V to 5.5 V
supply. The input voltage on the ADC channels has a range of
0 V to 2.25 V and the input bandwidth is dc. The reference for
the ADC channels is derived internally. The ADT7411 provides
two serial interface options: a 4-wire serial interface compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards,
and a 2-wire SMBus/I
2
C interface. It features a standby mode
that is controlled via the serial interface.
The ADT7411's wide supply voltage range, low supply current,
and SPI/I
2
C compatible interface make it ideal for a variety of
applications, including personal computers, office equipment,
and domestic appliances.
*Protected by the following U.S. Patent Numbers: 6,169,442; 5,867,012; 5,764174. Other patents pending.
ADT7411
Rev. A | Page 2 of 36
TABLE OF CONTENTS
Specifications..................................................................................... 3
Functional Block Diagram .............................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Functional Description ........................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
Power-Up Calibration................................................................ 13
Conversion Speed....................................................................... 13
Functional Description.................................................................. 14
Analog Inputs.............................................................................. 14
Functional Description--Measurement.................................. 15
ADT7411 Registers .................................................................... 19
Serial Interface ............................................................................ 27
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
Revision A
3/04Data Sheet Changed from Rev. 0 to Rev. A
Format Updated
Universal
Change to Equation.............................................................................17
8/03Revision 0: Initial Version
ADT7411
Rev. A | Page 3 of 36
SPECIFICATIONS
Table 1. V
DD
= 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Temperature ranges are -40C to +120C.
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
ADC DC ACCURACY
Max V
DD
= 5 V.
Resolution
10
Bits
Total Unadjusted Error (TUE)
2
3
% of FSR
Offset Error
0.5
% of FSR
Gain Error
2
% of FSR
ADC BANDWIDTH
DC
Hz
ANALOG
INPUTS
Input Voltage Range
0
2.25
V
AIN1 to AIN8. C4 = 0 in Control Configuration 3.
0
V
DD
V
AIN1 to AIN8. C4 = 1 in Control Configuration 3.
DC Leakage Current
1
A
Input Capacitance
5
20
pF
Input Resistance
10
M
THERMAL
CHARACTERISTICS
Internal reference used. Averaging on.
Internal Temperature Sensor
Accuracy @ V
DD
= 3.3 V 10%
1.5
C
T
A
= 85C.
0.5
3
C
T
A
= 0C to 85C.
2 5 C
T
A
= -40C to +120C.
Accuracy @ V
DD
= 5 V 5%
2
3
C
T
A
= 0C to 85C.
3 5 C
T
A
= -40C to +120C.
Resolution
10
Bits
Equivalent to 0.25C.
Long-term Drift
0.25
C
Drift over 10 years if part is operated at 55C.
External Temperature Sensor
External transistor = 2N3906.
Accuracy @ V
DD
= 3.3 V 10%
1.5
C
T
A
= 85C.
3
C
T
A
= 0C to 85C.
5
C
T
A
= -40C to +120C.
Accuracy @ V
DD
= 5 V 5%
2
3
C
T
A
= 0C to 85C.
3 5 C
T
A
= -40C to +120C.
Resolution
10
Bits
Equivalent to 0.25C.
Output Source Current
180
A
High Level.
11
A
Low
Level.
CONVERSION
TIMES
Single-channel
Mode.
Slow
ADC
V
DD
/AIN
11.4
ms
Averaging (16 samples) on.
712
s
Averaging
off.
Internal Temperature
11.4
ms
Averaging (16 samples) on.
712
s
Averaging
off.
External Temperature
24.22
ms
Averaging (16 samples) on.
1.51
ms
Averaging
off.
Fast ADC
V
DD
/AIN
712
s
Averaging (16 samples) on.
44.5
s
Averaging
off.
Internal Temperature
2.14
ms
Averaging (16 samples) on.
134
s
Averaging
off.
External Temperature
14.25
ms
Averaging (16 samples) on.
890
s
Averaging
off.
1
See the Terminology section.
ADT7411
Rev. A | Page 4 of 36
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
ROUND ROBIN UPDATE RATE
2
Time to complete one measurement cycle through all
channels.
Slow ADC @ 25C
Averaging On
125.4
ms
AIN1 and AIN2 are selected on Pins 7 and 8.
Averaging Off
17.1
ms
AIN1 and AIN2 are selected on Pins 7 and 8.
Averaging On
140.36
ms
D+ and D are selected on Pins 7 and 8.
Averaging Off
12.11
ms
D+ and D- are selected on Pins 7 and 8.
Fast ADC @ 25C
Averaging On
9.26
ms
AIN1 and AIN2 are selected on Pins 7 and 8.
Averaging Off
578.96
s
AIN1 and AIN2 are selected on pins 7 and 8.
Averaging On
24.62
ms
D+ and D- are selected on Pins 7 and 8.
Averaging Off
3.25
ms
D+ and D- are selected on Pins 7 and 8.
ON-CHIP REFERENCE
3
Reference Voltage
2.25
V
Temperature Coefficient
80
ppm/C
DIGITAL INPUTS
1, 3
Input Current
1
A
V
IN
= 0 V to V
DD
.
V
IL
, Input Low Voltage
0.8
V
V
IH
, Input High Voltage
1.89
V
Pin Capacitance
3
10
pF
All Digital Inputs.
SCL, SDA Glitch Rejection
50
ns
Input filtering suppresses noise spikes of less than 50 ns.
DIGITAL
OUTPUT
Output High Voltage, V
OH
2.4
V
I
SOURCE
= I
SINK
= 200 A.
Output Low Voltage, V
OL
0.4
V
I
OL
= 3 mA.
Output High Current, I
OH
1
mA
V
OH
= 5 V.
Output Capacitance, C
OUT
50
pF
INT/INT Output Saturation Voltage
0.8 V
I
OUT
= 4 mA.
I
2
C TIMING CHARACTERISTICS
4, 5
Serial Clock Period, t
1
2.5
s
Fast-Mode
I
2
C. See Figure 2.
Data In Setup Time to SCL High, t
2
50
ns
Data Out Stable after SCL Low, t
3
0
ns
See
Figure
2.
SDA Low Setup Time to SCL Low
(Start Condition), t
4
50
ns
See
Figure
2.
SDA High Hold Time after SCL High
(Stop Condition), t
5
50
ns
See
Figure
2.
SDA and SCL Fall Time, t
6
90
ns
See Figure 2.
SPI TIMING CHARACTERISTICS
1, 3, 6
CS to SCLK Setup Time, t
1
0
ns
See
Figure
3.
SCLK High Pulse Width, t
2
50
ns
See
Figure
3.
SCLK Low Pulse Width, t
3
50
ns
See
Figure
3.
Data Access Time after SCLK
Falling Edge, t
4
6
35
ns
See Figure 3.
Data Setup Time Prior to SCLK
Rising Edge, t
5
20
ns
See
Figure
3.
Data Hold Time after SCLK
Rising Edge, t
6
0
ns
See
Figure
3.
2
Round robin is the continuous sequential measurement of the following channels: V
DD
, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8.
3
Guaranteed by design and characterization, not production tested.
4
The SDA and SCL timing is measured with the input filters turned on so as to meet the FAST-Mode I
2
C specification. Switching off the input filters improves the transfer
rate, but has a negative effect on the EMC behavior of the part.
5
Guaranteed by design. Not tested in production.
6
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
), and timed from a voltage level of 1.6 V.
ADT7411
Rev. A | Page 5 of 36
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
CS to SCLK Hold Time, t
7
0
ns
See
Figure
3.
CS to DOUT High Impedance, t
8
40
ns
See Figure 3.
POWER REQUIREMENTS
V
DD
2.7
5.5
V
V
DD
Settling Time
50
ms
V
DD
settles to within 10% of its final voltage level.
I
DD
(Normal Mode)
7
3
mA
V
DD
= 3.3 V, V
IH
= V
DD
and V
IL
= GND.
2.2
3
mA
V
DD
= 5 V, V
IH
= V
DD
and V
IL
= GND.
I
DD
(Power-Down Mode)
10
A
V
DD
= 3.3 V, V
IH
=V
DD
and V
IL
= GND.
10
A
V
DD
= 5 V, V
IH
= V
DD
and V
IL
= GND.
Power Dissipation
10
mW
V
DD
= 3.3 V. Using normal mode.
33
W
V
DD
= 3.3 V. Using shutdown mode.
02882-A
-
002
SCL
t
4
t
2
t
1
t
3
t
5
t
6
SDA
DATA IN
SDA
DATA OUT
Figure 2. I
2
C Bus Timing Diagram
02882-A
-
003
t
1
t
2
t
3
t
5
t
6
t
4
t
7
t
8
D7
CS
SCLK
D
IN
D
OUT
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. SPI Bus Timing Diagram
02882-A
-
004
200
A
I
OH
1.6V
TO
OUTPUT
PIN
C
L
50pF
200
A
I
OL
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
7
I
DD
specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.
ADT7411
Rev. A | Page 6 of 36
FUNCTIONAL BLOCK DIAGRAM
02882-A
-
001
7
D+/AIN1
8
D/AIN2
9
AIN3
14
AIN4
2
AIN5
1
AIN6
16
AIN7
15
AIN8
V
DD
VALUE REGISTER
12
SDA/DIN
5
GND
6
V
DD
13
SCL/SCLK
11
DOUT/ADD
4
CS
ADDRESS POINTER
REGISTER
DIGITAL MUX
T
HIGH
LIMIT
REGISTERS
LIMIT
COMPARATOR
T
LOW
LIMIT
REGISTERS
V
DD
LIMIT
REGISTERS
AIN
HIGH
LIMIT
REGISTERS
AIN
LOW
LIMIT
REGISTERS
CONTROL CONFIG. 1
REGISTER
CONTROL CONFIG. 2
REGISTER
CONTROL CONFIG. 3
REGISTER
INTERRUPT MASK
REGISTERS
STATUS
REGISTERS
ON-CHIP
TEMPERATURE
SENSOR
INTERNAL
TEMPERATURE
VALUE REGISTER
EXTERNAL
TEMPERATURE
VALUE REGISTER
V
DD
SENSOR
ADT7411
ANALOG
MUX
A-TO-D
CONVERTER
INT/INT
AIN4
VALUE REGISTER
AIN3
VALUE REGISTER
AIN2
VALUE REGISTER
AIN1
VALUE REGISTER
AIN7
VALUE REGISTER
AIN6
VALUE REGISTER
AIN5
VALUE REGISTER
10
SPI/SMBus INTERFACE
AIN8
VALUE REGISTER
DIGITAL MUX
Figure 5. Functional Block Diagram
ADT7411
Rev. A | Page 7 of 36
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
V
DD
to GND
-0.3 V to +7 V
Analog Input Voltage to GND
-0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
-40C to +120C
Storage Temperature Range
-65C to +150C
Junction Temperature
150C
16-Lead QSOP Package
Power Dissipation
8
(T
Jmax
- TA)/
JA
Thermal Impedance
9
JA
Junction-to-Ambient
105.44C/W
JC
Junction-to-Case
38.8C/W
IR Reflow Soldering
Peak Temperature
220C (0C/5C)
Time at Peak Temperature
10 sec to 20 sec
Ramp-Up Rate
2C/sec to 3C/sec
Ramp-Down Rate
-6C/sec
8
Values relate to package being used on a 4-layer board
9
Junction-to-case resistance is applicable to components featuring a
preferential flow direction, e.g., components mounted on a heat sink.
Junction-to-ambient resistance is more useful for air-cooled PCB-mounted
components.
Table 3. I
2
C Address Selection
ADD Pin
I
2
C Address
Low
1001 000
Float
1001 010
High
1001 011
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electro-static discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADT7411
Rev. A | Page 8 of 36
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTION
02882-A
-
005
ADT7411
TOP VIEW
(Not to Scale)
AIN6
1
AIN7
16
AIN5
2
AIN8
15
NC
3
AIN4
14
CS
4
SCL/SCLK
13
GND
5
SDA/DIN
12
V
DD
6
DOUT/ADD
11
D+/AIN1
7
INT/INT
10
D/AIN2
8
AIN3
9
NC = NO CONNECT
Figure 6. Pin Configuration
Table 4. Pin Function Description
Pin
No.
Mnemonic
Description
1
AIN6
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
DD
.
2
AIN5
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
DD
.
3
NC
No Connection to This Pin.
4
CS
SPI--Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it
enables the input register and data is transferred in on the rising edges and out on the falling edges of the
subsequent serial clocks. It is recommended that this pin be tied high to V
DD
when operating the serial interface in I
2
C
mode.
5
GND
Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
6 V
DD
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
7 D+/AIN D+. Positive connection to external temperature sensor. AIN1. Analog Input. Single-ended analog input channel.
Input range is 0 V to 2.25 V or 0 V to 5 V.
8 D-/AIN2
D-. Negative connection to external temperature sensor. AIN2. Analog Input. Single-ended analog input channel.
Input range is 0 V to 2.25 V or 0 V to 5 V.
9
AIN3
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
DD
.
10
INT/INT
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature, V
DD
, or AIN limits are exceeded. Default is active low. Open-drain output, needs a pull-up resistor.
11 DOUT/ADD
SPI. Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling
edge of SCLK. Open-drain output, needs a pull-up resistor.
ADD. I
2
C serial bus address selection pin. Logic input. A low on this pin gives the Address 1001 000. Leaving it floating
gives the address 1001 010, and setting it high gives the Address 1001 011. The I
2
C address set up by the ADD pin is
not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid
communication, the serial bus address is latched in. Any subsequent changes on this pin will have no effect on the I
2
C
serial bus address.
12 SDA/DIN SDA. I
2
C serial data input. I
2
C serial data to be loaded into the part's registers is provided on this input. An open-drain
configuration, it needs a pull-up resistor.
DIN. SPI serial data input. Serial data to be loaded into the part's registers is provided on this input. Data is clocked
into a register on the rising edge of SCLK. Open-drain configuration, needs a pull-up resistor.
13 SCL/SCLK Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of
the ADT7411 and also to clock data into any register that can be written to. An open-drain configuration, it needs a
pull-up resistor.
14
AIN4
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
DD
.
15
AIN8
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
DD
.
16
AIN7
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
DD
.
ADT7411
Rev. A | Page 9 of 36
TERMINOLOGY
Relative Accuracy
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the ADC transfer function. A typical
INL versus code plot can be seen in Figure 10.
Total Unadjusted Error (TUE)
Total unadjusted error is a comprehensive specification that
includes the sum of the relative accuracy error, gain error, and
offset error under a specified set of conditions.
Offset Error
This is a measure of the offset error of the ADC. It can be
negative or positive. It is expressed in mV.
Gain Error
This is a measure of the span error of the ADC. It is the
deviation in slope of the actual ADC transfer characteristic
from the ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/C.
Long -term Temperature Drift
This is a measure of the change in temperature error with the
passage of time. It is expressed in degrees Celsius. The concept
of long-term stability has been used for many years to describe
by what amount an IC's parameter would shift during its
lifetime. This is a concept that has been typically applied to both
voltage references and monolithic temperature sensors.
Unfortunately, integrated circuits cannot be evaluated at room
temperature (25C) for 10 years or so to determine this shift. As
a result, manufacturers typically perform accelerated lifetime
testing of integrated circuits by operating ICs at elevated
temperatures (between 125C and 150C) over a shorter period
of time (typically, between 500 and 1,000 hours). As a result of
this operation, the lifetime of an integrated circuit is
significantly accelerated due to the increase in rates of reaction
within the semiconductor material.
DC Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio (PSRR) is defined as the ratio
of the power in the ADC output at full-scale frequency f, to the
power of a 100 mV sine wave applied to the V
DD
supply of
frequency fs:
( )
(
)
Pfs
Pf
dB
PSRR
log
10
=
Pf
= power at frequency f in ADC output
Pfs
= power at frequency fs coupled into the V
DD
supply
Round Robin
This term is used to describe the ADT7411 cycling through
the available measurement channels in sequence, taking a
measurement on each channel.
ADT7411
Rev. A | Page 10 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
02882-A
-
006
2.00
2.7
3.1
3.5
3.9
4.3
4.7
5.1
2.9
3.3
3.7
4.1
4.5
4.9
5.3 5.5
V
CC
(V)
I
CC
(mA)
1.75
1.80
1.85
1.90
1.95
ADC OFF
Figure 7. Supply Current vs. Supply Voltage at 25C
02882-A
-
007
10
AC P
S
RR (dB)
60
50
40
30
20
0
1
10
100
FREQUENCY (kHz)
100mV RIPPLE ON V
CC
V
REF
= 2.25V
V
DD
= 3.3V
TEMPERATURE = 25
C
Figure 8. PSRR vs. Supply Ripple Frequency
02882-A
-
008
7
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V
CC
(V)
I
CC
(
A)
0
1
2
3
4
5
6
Figure 9. Power-Down Current vs. Supply Voltage at 25C
02882-A
-
009
1.0
0
200
400
600
800
1000
ADC CODE
INL E
RROR (LS
B
)
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
Figure 10. ADC INL with Ref = V
DD
(3.3V)
02882-A
-
010
TEMPERATURE (
C)
30
0
40
85
120
1.5
TE
MP
E
RATURE
E
RROR (
C)
1.0
0.5
0
0.5
1.0
EXTERNAL TEMPERATURE @ 3.3V
INTERNAL TEMPERATURE @ 5V
INTERNAL TEMPERATURE @ 3.3V
EXTERNAL TEMPERATURE @ 5V
Figure 11. Temperature Error at 3.3 V and 5 V
02882-A
-
011
E
RROR (LS
B
)
1
0
1
2
3
2
3
4
V
DD
= 3.3V
40
20
0
TEMPERATURE (
C)
20
40
60
80
100
120
GAIN ERROR
OFFSET ERROR
Figure 12. ADC Offset Error and Gain Error vs. Temperature
ADT7411
Rev. A | Page 11 of 36
02882-A
-
012
15
TE
MP
E
R
ATURE
E
RROR (
C)
10
5
0
5
10
15
20
25
0
10
20
PCB LEAKAGE RESISTANCE (M
)
30
40
50
60
70
80
90
100
V
DD
= 3.3V
TEMPERATURE = 25
C
D+ TO GND
D+ TO V
CC
Figure 13. External Temperature Error vs. PCB Track Resistance
02882-A
-
013
10
TE
MP
E
RATURE
E
RROR (
C)
0
2
4
6
8
2
4
6
NOISE FREQUENCY (Hz)
V
DD
= 3.3V
COMMON-MODE
VOLTAGE = 100mV
1
100
200
300
400
500
600
Figure 14. External Temperature Error vs.
Common-Mode Noise Frequency
02882-A
-
014
V
DD
(V)
E
RROR (LS
B
)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
3
2
1
0
1
2
3
OFFSET ERROR
GAIN ERROR
Figure 15. ADC Offset Error and Gain Error vs. V
DD
02882-A
-
015
TE
MP
E
RATURE
E
RROR (
C)
60
50
40
30
20
10
0
V
DD
= 3.3V
0
5
10
15
20
25
CAPACITANCE (nF)
30
35
40
45
50
Figure 16. External Temperature Error vs. Capacitance
between D+ and D-
02882-A
-
016
70
TE
MP
E
RATURE
E
RROR (
C)
20
30
40
50
60
10
0
10
1
100
200
NOISE FREQUENCY (MHz)
300
400
500
600
V
DD
= 3.3V
DIFFERENTIAL-MODE
VOLTAGE = 100mV
Figure 17. External Temperature Error vs. Differential Mode
Noise Frequency
02882-A
-
017
NOISE FREQUENCY (Hz)
250mV
V
DD
= 3.3V
1
100
200
300
400
500
600
0.6
TE
MP
E
RATURE
E
RROR (
C)
0.4
0.2
0
0.2
0.4
0.6
Figure 18. Internal Temperature Error vs. Power Supply Noise Frequency
ADT7411
Rev. A | Page 12 of 36
02882-A
-
018
140
TE
MP
E
RATURE
(
C)
40
60
80
100
120
20
0
10
20
TIME (s)
30
40
50
0
60
EXTERNAL TEMPERATURE
TEMPERATURE OF
ENVIRONMENT
CHANGED HERE
INTERNAL TEMPERATURE
Figure 19. Temperature Sensor Response to Thermal Shock
ADT7411
Rev. A | Page 13 of 36
THEORY OF OPERATION
Directly after the power-up calibration routine, the ADT7411
goes into idle mode. In this mode, the device is not performing
any measurements and is fully powered up.
To begin monitoring, write to the Control Configuration 1
register (Address 18h) and set Bit C0 = 1. The ADT7411 goes
into its power-up default measurement mode, which is round
robin. The device proceeds to take measurements on the V
DD
channel, internal temperature sensor channel, external temp-
erature sensor channel, or AIN1 and AIN2, AIN3, AIN4, AIN5,
AIN6, AIN7, and finally AIN8. Once it finishes taking measure-
ments on the AIN8 channel, the device immediately loops back
to start taking measurements on the V
DD
channel and repeats
the same cycle as before. This loop continues until the mon-
itoring is stopped by resetting Bit C0 of the Control Config-
uration 1 register to 0. It is also possible to continue monitoring
as well as switching to single-channel mode by writing to the
Control Configuration 2 register (Address 19h) and setting
Bit C4 = 1. Further explanations of the single-channel and
round robin measurement modes are given in later sections. All
measurement channels have averaging enabled on them at
power-up. Averaging forces the device to take an average of 16
readings before giving a final measured result. To disable aver-
aging and consequently decrease the conversion time by a factor
of 16, set C5 = 1 in the Control Configuration 2 register.
There are eight single-ended analog input channels on the
ADT7411: AIN1 to AIN8. AIN1 and AIN2 are multiplexed with
the external temperature sensors D+ and D- terminals. Bits C1
and C2 of the Control Configuration 1 register (Address 18h)
are used to select between AIN1/2 and the external temperature
sensor. The input range on the analog input channels is
dependent on whether the ADC reference used is the internal
V
REF
or V
DD
. To meet linearity specifications, it is recommended
that the maximum V
DD
value is 5 V. Bit C4 of the Control
Configuration 3 register is used to select between the internal
reference and V
DD
as the analog inputs' ADC reference.
The dual serial interface defaults to the I
2
C protocol on power-
up. To select and lock in the SPI protocol, follow the selection
process as described in the Serial Interface Selection section.
The I
2
C protocol cannot be locked in, while the SPI protocol on
selection is automatically locked in. The interface can only be
switched back to I
2
C when the device is powered off and on.
When using I
2
C, the CS pin should be tied to either V
DD
or
GND.
There are a number of different operating modes on the
ADT7411 devices and all of them can be controlled by the
configuration registers. These features consist of enabling and
disabling interrupts, polarity of the INT/INT pin, enabling and
disabling the averaging on the measurement channels, SMBus
timeout, and software reset.
POWER-UP CALIBRATION
It is recommended that no communication to the part is
initiated until approximately 5 ms after V
DD
has settled to within
10% of its final value. It is generally accepted that most systems
take a maximum of 50 ms to power up. Power-up time is
directly related to the amount of decoupling on the voltage
supply line.
During the 5 ms after V
DD
has settled the part is performing a
calibration routine; any communication to the device will
interrupt this routine and could cause erroneous temperature
measurements. If it is not possible to have V
DD
at its nominal
value by the time 50 ms has elapsed or that communication to
the device has started prior to V
DD
settling, then it is recom-
mended that a measurement be taken on the V
DD
channel
before a temperature measurement is taken. The V
DD
measure-
ment is used to calibrate out any temperature measurement
error due to different supply voltage values.
CONVERSION SPEED
The internal oscillator circuit used by the ADC has the
capability to output two different clock frequencies. This means
that the ADC is capable of running at two different speeds
when doing a conversion on a measurement channel. Thus the
time taken to perform a conversion on a channel can be
reduced by setting C0 of the Control Configuration 3 register
(Address 1Ah). This increases the ADC clock speed from
1.4 kHz to 22 kHz. At the higher clock speed, the analog filters
on the D+ and D- input pins (external temperature sensor) are
switched off. This is why the power-up default setting is to have
the ADC working at the slow speed. The typical times for fast
and slow ADC speeds are given in the specification pages.
The ADT7411 powers up with averaging on. This means every
channel is measured 16 times and internally averaged to reduce
noise. The conversion time can also be reduced by turning the
averaging off. This is done by setting Bit C5 of the Control
Configuration 2 register (Address 19h) to a 1.
ADT7411
Rev. A | Page 14 of 36
FUNCTIONAL DESCRIPTION
ANALOG INPUTS
Single-Ended Inputs
The ADT7411 offers eight single-ended analog input channels.
The analog input range is from 0 V to 2.25 V or 0 V to V
DD
. To
maintain the linearity specification it is recommended that the
maximum V
DD
value be set at 5 V. Selection between the two
input ranges is done by Bit C4 of the Control Configuration
3 register (Address 1Ah). Setting this bit to 0 sets up the analog
input ADC reference to be sourced from the internal voltage
reference of 2.25 V. Setting the bit to 1 sets up the ADC
reference to be sourced from V
DD
.
The ADC resolution is 10 bits and is mostly suitable for dc input
signals or very slowly varying ac signals. Bits C1:2 of the
Control Configuration 1 register (Address 18h) are used to set
up Pins 7 and 8 as AIN1 and AIN2. Figure 20 shows the overall
view of the 8-channel analog input path.
02882-A
-
021
CONTROL
LOGIC
CAP DAC
ACQUISITION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT V
REF
REF
V
DD
AIN
SW1
A
B
SW2
REF/2
Figure 20. Octal Analog Input Path
Converter Operation
The analog input channels use a successive approximation ADC
based around a capacitor DAC. Figure 21 and Figure 22 show
simplified schematics of the ADC. Figure 21 shows the ADC
during acquisition phase. SW2 is closed and SW1 is in position
A. The comparator is held in a balanced condition and the
sampling capacitor acquires the signal on AIN.
02882-A
-
021
CONTROL
LOGIC
CAP DAC
ACQUISITION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT V
REF
REF
V
DD
AIN
SW1
A
B
SW2
REF/2
Figure 21. ADC Acquisition Phase
When the ADC eventually goes into conversion phase (see
Figure 22) SW2 opens and SW1 moves to position B, causing
the comparator to become unbalanced. The control logic and
the DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 24 shows the ADC transfer function for
single-ended analog inputs.
02882-A
-
022
CONTROL
LOGIC
CAP DAC
CONVERSION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT V
REF
REF
V
DD
AIN
SW1
A
B
SW2
REF/2
Figure 22. ADC Conversion Phase
02882-A
-
020
C1
D+
LOW-PASS
FILTER
f
C
= 65kHz
BIAS
DIODE
V
DD
TO ADC
V
OUT+
V
OUT
REMOTE
SENSING
TRANSISTOR
(2N3906)
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
D
I
N
I
I
BIAS
Figure 23. Signal Conditioning for External Diode Temperature Sensor
ADT7411
Rev. A | Page 15 of 36
ADC Transfer Function
The output coding of the ADT7411 analog inputs is straight
binary. The designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB). The LSB is
V
DD
/1024 or Int V
REF
/1024, Int V
REF
= 2.25 V. The ideal transfer
characteristic is shown in Figure 24.
02882-A
-
023
111...111
111...110
111...000
011...111
+V
REF
1LSB
0V 1/2 LSB
ANALOG INPUT
ADC CODE
1LSB = INT V
REF
/1024
1LSB = V
DD
/1024
000...010
000...001
000...000
Figure 24. Transfer Function
To work out the voltage on any analog input channel, the
following method can be used:
( )
1024
1
V
ference
Re
LSB =
Convert the value read back from the AIN value register into
decimal.
( )
size
LSB
d
AINValue
AINVoltage
=
where d = decimal
Example:
Internal reference used. Therefore, V
REF
= 2.25 V.
V
AINVoltage
V
size
LSB
d
value
AIN
125
.
1
10
197
.
2
512
10
197
.
2
1024
25
.
2
1
512
3
3
=
=
=
=
=
-
-
Analog Input ESD Protection
Figure 26 shows the input structure that provides ESD protec-
tion on any of the analog input pins. The diode provides the
main ESD protection for the analog inputs. Care must be taken
that the analog input signal never drops below the GND rail by
more than 200 mV. If this happens, the diode will become
forward biased and start conducting current into the substrate.
The 4 pF capacitor is the typical pin capacitance and the resistor
is a lumped component made up of the on resistance of the
multiplexer switch.
02882-A
-
024
BIAS
DIODE
INTERNAL
SENSE
TRANSISTOR
V
DD
TO ADC
V
OUT+
V
OUT
I
N
I
I
BIAS
Figure 25. Top Level Structure of Internal Temperature Sensor
02882-A
-
025
4pF
AIN
100
Figure 26. Equivalent Analog Input ESD Circuit
AIN Interrupts
The measured results from the AIN inputs are compared with
the AIN V
HIGH
(greater than comparison) and V
LOW
(less than or
equal to comparison) limits. An interrupt occurs if the AIN
inputs exceed or equal the limit registers. These voltage limits
are stored in on-chip registers. Note that the limit registers are
eight bits long while the AIN conversion result is 10 bits long.
If the voltage limits are not masked out, any out-of-limit
comparisons generate flags that are stored in the Interrupt
Status 1 register (Address 00h) and one or more out-of-limit
results will cause the INT/INT output to pull either high or low,
depending on the output polarity setting. It is good design prac-
tice to mask out interrupts for channels that are of no concern
to the application. Figure 27 shows the interrupt structure for
the ADT7411. It shows a block diagram representation of how
the various measurement channels affect the INT/INT pin.
FUNCTIONAL DESCRIPTION--MEASUREMENT
Temperature Sensor
The ADT7411 contains an A/D converter with special input
signal conditioning to enable operation with external and on-
chip diode temperature sensors. When the ADT7411 is oper-
ating in single-channel mode, the A/D converter continually
processes the measurement taken on one channel only. This
channel is preselected by bits C0:C3 in the Control Config-
uration 2 register (Address 19h). When in round robin mode
the analog input multiplexer sequentially selects the V
DD
input
channel, on-chip temperature sensor to measure its internal
temperature, the external temperature sensor, or an AIN
channel, and then the rest of the AIN channels. These signals
are digitized by the ADC and the results stored in the various
value registers.
ADT7411
Rev. A | Page 16 of 36
The measured results from the temperature sensors are com-
pared with the internal and external, T
HIGH
, T
LOW
, limits. These
temperature limits are stored in on-chip registers. If the temp-
erature limits are not masked out, any out-of-limit comparisons
generate flags that are stored in Interrupt Status 1 register. One
or more out-of-limit results will cause the INT/INT output to
pull either high or low, depending on the output polarity setting.
Theoretically, the temperature measuring circuit can measure
temperatures from 128C to +127C with a resolution of
0.25C. However, temperatures outside T
A
are outside the guar-
anteed operating temperature range of the device. Temperature
measurement from 128C to +127C is possible using an
external sensor.
Temperature measurement is initiated by three methods. The
first method is applicable when the part is in single-channel
measurement mode. The temperature is measured 16 times and
internally averaged to reduce noise. In single-channel mode, the
part is continuously monitoring the selected channel, i.e., as
soon as one measurement is taken, another one is started on the
same channel. The total time to measure a temperature channel
with the ADC operating at slow speed is typically 11.4 ms
(712 s 16) for the internal temperature sensor and 24.22 ms
(1.51 ms 16) for the external temperature sensor. The new
temperature value is stored in two 8-bit registers and ready for
reading by the I
2
C or SPI interface. The user has the option of
disabling the averaging by setting Bit 5 in the Control Config-
uration 2 register (Address 19h). The ADT7411 defaults on
power-up with the averaging enabled.
The second method is applicable when the part is in round
robin measurement mode. The part measures both the internal
and external temperature sensors as it cycles through all
possible measurement channels. The two temperature channels
are measured each time the part runs a round robin sequence.
In round robin mode, the part is continuously measuring all
channels.
Temperature measurement is also initiated after every read or
write to the part when the part is in either single-channel
measurement mode or round robin measurement mode. Once
serial communication has started, any conversion in progress is
stopped and the ADC is reset. Conversion will start again
immediately after the serial communication has finished. The
temperature measurement proceeds normally as described
previously.
02882-A
-
026
WATCHDOG
LIMIT
COMPARISONS
INTERRUPT
MASK
REGISTERS
CONTROL
CONFIGURATION
REGISTER 1
INTERRUPT
STATUS
REGISTER 1
(TEMP AND
AIN1 TO AIN4)
INTERRUPT
STATUS
REGISTER 2
(V
DD
AND
AIN5 TO AIN8)
S
TATUS
BITS
S
TATUS
BITS
READ RESET
S/W RESET
INTERNAL
TEMP
INT/INT
(LATCHED OUTPUT)
INT/INT
ENABLE BIT
EXTERNAL
TEMP
V
DD
DIODE
FAULT
AIN1AIN4
AIN5AIN8
Figure 27. ADT7411 Interrupt Structure
ADT7411
Rev. A | Page 17 of 36
V
DD
Monitoring
The ADT7411 also has the capability of monitoring its own
power supply. The part measures the voltage on its V
DD
pin to a
resolution of 10 bits. The resulting value is stored in two 8-bit
registers, with the 2 LSBs stored in register Address 03h and the
8 MSBs stored in register Address 06h. This allows the user to
have the option of just doing a 1-byte read if 10-bit resolution is
not important. The measured result is compared with the V
HIGH
and V
LOW
limits. If the V
DD
interrupt is not masked out then any
out-of-limit comparison generates a flag in the Interrupt Status
2 register, and one or more out-of-limit results will cause the
INT/INT output to pull either high or low, depending on the
output polarity setting.
Measuring the voltage on the V
DD
pin is regarded as monitoring
a channel along with the internal, external, and AIN channels.
The user can select the V
DD
channel for single-channel measure-
ment by setting Bit C4 = 1 and setting Bits C0 to C2 to all 0s in
the Control Configuration 2 register.
When measuring the V
DD
value, the reference for the ADC is
sourced from the internal reference. Table 5 shows the data
format. As the max V
DD
voltage measurable is 7 V, internal
scaling is performed on the V
DD
voltage to match the 2.25 V
internal reference value. The following is an example of how the
transfer function works:
V
ference
e
R
ADC
25
.
2
=
mV
ference
e
R
ADC
LSB
197
.
2
1024
25
.
2
2
1
10
=
=
=
11
.
3
25
.
2
7
e
=
=
=
ference
R
ADC
V
Fullscale
Factor
Scale
CC
Conversion Result = VDD/(Scale Factor LSB Size)
(
)
mV
197
.
2
11
.
3
5
=
DBh
2
=
Table 5. V
DD
Data Format, V
REF
= 2.25 V
Digital
Output
V
DD
Value (V)
Binary Hex
2.5
01 0110 1110
16E
2.7
01 1000 1011
18B
3.0
01 1011 0111
1B7
3.5
10 0000 0000
200
4.0
10 0100 1001
249
4.5
10 1001 0010
292
5.0
10 1101 1011
2DB
5.5
11 0010 0100
324
6.0
11 0110 1101
36D
6.5
11 1011 0110
3B6
7.0
11 1111 1111
3FF
On-Chip Reference
The ADT7411 has an on-chip 1.125 V band gap reference that is
gained up by a switched capacitor amplifier to give an output of
2.25 V. The amplifier is powered up for the duration of the
device monitoring phase and is powered down once monitoring
is disabled. This saves on current consumption. The internal
reference is used as the reference for the ADC.
Round Robin Measurement
Upon power-up, the ADT7411 goes into round robin mode, but
monitoring is disabled. Setting Bit C0 of the Configuration 1
register to 1 enables conversions. It sequences through all
available channels, taking a measurement from each in the
following order: V
DD
, internal temperature sensor, external
temperature sensor/(AIN1 and AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8. Pin 7 and Pin 8 can be configured as
either external temperature sensor pins or standalone analog
input pins. Once conversion is completed on the AIN8 channel,
the device loops around for another measurement cycle. This
method of taking a measurement on all the channels in one
cycle is called round robin. Setting Bit 4 of the Control
Configuration 2 register (Address 19h) disables the round robin
mode and in turn sets up the single-channel mode. The single-
channel mode is where only one channel, e.g., the internal
temperature sensor, is measured in each conversion cycle.
The time taken to monitor all channels will normally not be of
interest, as the most recently measured value can be read at any
time. For applications where the round robin time is important,
typical times at 25C are given in the specification pages.
Single-Channel Measurement
Setting Bit C4 of the Control Configuration 2 register enables
the single-channel mode and allows the ADT7411 to focus on
one channel only. A channel is selected by writing to Bits C0:C3
in the Control Configuration 2 register. For example, to select
the V
DD
channel for monitoring, write to the Control
Configuration 2 register and set C4 to 1 (if not done so already),
then write all 0s to Bits C0 to C3. All subsequent conversions
will be done on the V
DD
channel only. To change the channel
selection to the internal temperature channel, write to the
Control Configuration 2 register and set C0 = 1. When
measuring in single-channel mode, conversions on the channel
selected occur directly after each other. Any communication to
the ADT7411 stops the conversions, but they are restarted once
the read or write operation is completed.
Temperature Measurement Method
Internal Temperature Measurement
The ADT7411 contains an on-chip, band gap temperature
sensor whose output is digitized by the on-chip ADC. The
temperature data is stored in the internal temperature value
register. As both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table 6. The thermal characteristics of the
ADT7411
Rev. A | Page 18 of 36
measurement sensor could change and therefore an offset is
added to the measured value to enable the transfer function to
match the thermal characteristics. This offset is added before
the temperature data is stored. The offset value used is stored in
the internal temperature offset register.
External Temperature Measurement
The ADT7411 can measure the temperature of one external
diode sensor or diode-connected transistor.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about -2 mV/C. Unfortunately, the absolute
value of V
BE
varies from device to device, and individual
calibration is required to null this out, so the technique is
unsuitable for mass production.
The technique used in the ADT7411 is to measure the change in
V
BE
when the device is operated at two different currents.
This is given by:
( )
N
In
q
KT
V
BE
=
where:
K is Boltzmann's constant
q is the charge on the carrier
T is the absolute temperature in Kelvin
N is the ratio of the two currents
Figure 23 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for temp-
erature monitoring on some microprocessors, but it could
equally well be a discrete transistor.
If a discrete transistor is used, the collector will not be
grounded, and should be linked to the base. If a PNP transistor
is used, the base is connected to the D- input and the emitter to
the D+ input. If an NPN transistor is used, the emitter is con-
nected to the D- input and the base to the D+ input. A 2N3906
is recommended as the external transistor.
To prevent ground noise from interfering with the measure-
ment, the more negative terminal of the sensor is not referenced
to ground but is biased above ground by an internal diode at the
D- input. As the sensor is operating in a noisy environment, C1
is provided as a noise filter. See the Layout Considerations
section for more information on C1.
To measure V
BE
, the sensor is switched between operating
currents of I, and N I. The resulting waveform is passed
through a low-pass filter to remove noise, then to a chopper-
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage
proportional to V
BE
. This voltage is measured by the ADC to
give a temperature output in 10-bit twos complement format. To
further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles.
Layout Considerations
Digital boards can be electrically noisy environments, and care
must be taken to protect the analog inputs from noise, particu-
larly when measuring the very small voltages from a remote
diode sensor. The following precautions should be taken:
1.
Place the ADT7411 as close as possible to the remote
sensing diode. Provided that the worst noise sources such
as clock generators, data/address buses, and CRTs are
avoided, this distance can be 4 inches to 8 inches.
2.
Route the D+ and D- tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground
plane under the tracks if possible.
3.
Use wide tracks to minimize inductance and reduce noise
pickup. A 10 mil track minimum width and spacing is
recommended (see Figure 28).
02882-A
-
027
GND
D+
D
GND
10 MIL
10 MIL
10 MIL
10 MIL
10 MIL
10 MIL
10 MIL
Figure 28. Arrangement of Signal Tracks
4.
Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder
joints are used, make sure that they are in both the D+ and
D- path and at the same temperature.
Thermocouple effects should not be a major problem as
1C corresponds to about 240 V, and thermocouple
voltages are about 3 V/C of temperature difference.
Unless there are two thermocouples with a big temperature
differential between them, thermocouple voltages should
be much less than 200 mV.
5.
Place 0.1 F bypass and 2200 pF input filter capacitors
close to the ADT7411.
6.
If the distance to the remote sensor is more than 8 inches,
the use of twisted-pair cable is recommended. This will
work up to about 6 feet to 12 feet.
7.
For long distances (up to 100 feet) use shielded twisted-
pair cable, such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D- and the shield to
GND close to the ADT7411. Leave the remote end of the
shield unconnected to avoid ground loops.
ADT7411
Rev. A | Page 19 of 36
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor may
be reduced or removed.
Cable resistance can also introduce errors. 1 series resistance
introduces about 0.5C error.
Temperature Value Format
One LSB of the ADC corresponds to 0.25C. The ADC can
theoretically measure a temperature span of 255C. The internal
temperature sensor is guaranteed to a low value limit of -40C.
It is possible to measure the full temperature span using the
external temperature sensor. The temperature data format is
shown in Table 6.
The result of the internal or external temperature measure-
ments is stored as twos complement format in the temperature
value registers, and is compared with limits programmed into
the internal or external high and low registers.
Table 6. Temperature Data Format(Internal and External
Temperature)
Temperature (C)
Digital Output
-40
11 0110 0000
-25
11 1001 1100
-10
11 1101 1000
-0.25
11 1111 1111
0
00 0000 0000
+0.25
00 0000 0001
+10
00 0010 1000
+25
00 0110 0100
+50
00 1100 1000
+75
01 0010 1100
+100
01 1001 0000
+105
01 1010 0100
+125
01 1111 0100
Temperature Conversion Formula:
4
Code
ADC
e
Temperatur
Positive
=
(
)
4
512
-
=
Code
ADC
e
Temperatur
Negative
*DB9 is removed from the ADC Code.
Interrupts
The measured results from the internal temperature sensor,
external temperature sensor, VDD pin, and AIN inputs are
compared with their THIGH/VHIGH (greater than coparison)
and TLOW/VLOW (less than or equal to comparison) limits.
An interrupt occurs if the measurement exceeds or equals the
limit registers. These limits are stored in on-chip registers. Note
that the limit registers are eight bits long while the conversion
results are 10 bits long. If the limits are not masked out, then
any out-of-limit comparisons generate flags that are stored in
the Interrupt Status 1 register (Address 00h) and the Interrupt
Status 2 register (Address 01h). One or more out-of limit results
will cause the INT/INT output to pull either high or low
depending on the output polarity setting. It is good design
practice to mask out interrupts for channels that are of no
concern to the application.
Figure 27 shows the interrupt structure for the ADT7411.
It gives a block diagram representation of how the various
measurement channels affect the INT/INT pin.
ADT7411 REGISTERS
The ADT7411 contains registers that are used to store the
results of external and internal temperature measurements,
VDD value measurements, analog input measurements, high
and low temperature limits, supply voltage and analog input
limits, configure multipurpose pins, and generally control the
device. See Table 7 for a detailed description of these registers.
The register map is divided into registers of 8 bits. Each register
has its own individual address but some consist of data that is
linked with other registers. These registers hold the 10-bit con-
version results of measurements taken on the temperature, V
DD
,
and AIN channels. For example, the MSBs of the V
DD
measure-
ment are stored in Register Address 06h while the two LSBs are
stored in Register Address 03h. The link involved between these
types of registers is that when the LSB register is read first, the
MSB registers associated with that LSB register are locked out to
prevent any updates. To unlock these MSB registers the user has
only to read any one of them, which will have the effect of
unlocking all previously locked out MSB registers. So for the
example given above, if Register 03h was read first, MSB
Registers 06h and 07h would be locked out to prevent any
updates to them. If Register 06h was read this register and
Register 07h would be subsequently unlocked.
02882-A
-
028
LOCK ASSOCIATED
MSB REGISTERS
FIRST READ
COMMAND
LSB
REGISTER
OUTPUT
DATA
Figure 29. Phase 1 of 10-Bit Read
02882-A
-
029
UNLOCK ASSOCIATED
MSB REGISTERS
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
Figure 30. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is
not locked out, thus leaving the user with the option of just
reading back 8 bits (MSB) of a 10-bit conversion result. Reading
an MSB register first does not lock out other MSB registers, and
likewise reading an LSB register first does not lock out other
LSB registers.
ADT7411
Rev. A | Page 20 of 36
Table 7. ADT7411 Registers
RD/WR
Power-On
Address Name
Default
00h Interrupt
Status
1
00h
01h Interrupt
Status
2
00h
02h Reserved
03h
Internal Temp and V
DD
LSBs
00h
04h
External Temp and AIN14 LSBs
00h
05h AIN58
LSBs
00h
06h V
DD
MSBs
xxh
07h Internal
Temperature
MSBs
00h
08h External
Temp
MSBs/AIN1 MSBs
00h
09h AIN2
MSBs
00h
0Ah AIN3
MSBs
00h
0Bh AIN4
MSBs
00h
0Ch AIN5
MSBs
00h
0Dh AIN6
MSBs
00h
0Eh AIN7
MSBs
00h
0Fh AIN8
MSBs
00h
10h17h Reserved
18h Control
CONFIG
1
08h
19h Control
CONFIG
2
00h
1Ah Control
CONFIG
3
00h
1Bh1Ch Reserved
1Dh
Interrupt Mask 1
00h
1Eh
Interrupt Mask 2
00h
1Fh Internal
Temp
Offset
00h
20h
External Temp Offset
00h
21h Reserved
22h Reserved
23h V
DD
V
HIGH
Limit
C7h
24h V
DD
V
LOW
Limit
62h
25h Internal
T
HIGH
Limit
64h
26h Internal
T
LOW
Limit
C9h
27h External
T
HIGH
/AIN1 V
HIGH
Limits
FFh
28h External
T
LOW
/AIN1 V
LOW
Limits
00h
29h2Ah Reserved
2Bh AIN2
V
HIGH
Limit
FFh
2Ch AIN2
V
LOW
Limit
00h
2Dh AIN3
V
HIGH
Limit
FFh
2Eh AIN3
V
LOW
Limit
00h
2Fh AIN4
V
HIGH
Limit
FFh
30h AIN4
V
LOW
Limit
00h
31h AIN5
V
HIGH
Limit
FFh
32h AIN5
V
LOW
Limit
00h
33h AIN6
V
HIGH
Limit
FFh
34h AIN6
V
LOW
Limit
00h
35h AIN7
V
HIGH
Limit
FFh
36h AIN7
V
LOW
Limit
00h
37h AIN8
V
HIGH
Limit
FFh
38h AIN8
V
LOW
Limit
00h
39h4Ch Reserved
4Dh Device
ID
02h
4Eh Manufacturer's
ID
41h
4Fh Silicon
Revision
04h
50h7Eh Reserved
00h
7F
SPI Lock Status
00h
80hFFh Reserved
00h
Interrupt Status 1 Register (Read-Only) [Address = 00h]
This 8-bit read-only register reflects the status of some of the
interrupts that can cause the INT/INT pin to go active. This
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
Table 8. Interrupt Status 1 Register
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
Table 9.
Bit Function
D0
1 when internal temperature value exceeds T
HIGH
limit. Any
internal temperature reading greater than the set limit will
cause an out-of-limit event.
D1
1 when internal temperature value exceeds T
LOW
limit. Any
internal temperature reading less than or equal to the set
limit will cause an out-of-limit event.
D2
This status bit is linked to the configuration of pins 7 and 8.
If configured for external temperature sensor, this bit is 1
when external temperature value exceeds T
HIGH
limit. The
default value for this limit register is 1C, so any external
temperature reading greater than the limit set will cause
an out-of-limit event. If configured for AIN1 and AIN2, this
bit is 1 when AIN1 Input Voltage exceeds V
HIGH
or V
LOW
limits.
D3
1 when external temperature value exceeds T
LOW
limit. The
default value for this limit register is 0C, so any external
temperature reading less than or equal to the limit set will
cause an out-of-limit event.
D4
1 indicates a fault (open or short) for the external
temperature sensor.
D5
1 when AIN2 voltage is greater than corresponding V
HIGH
limit. 1 when AIN2 voltage is less than or equal to
corresponding V
LOW
limit.
D6
1 when AIN3 voltage is greater than corresponding V
HIGH
limit. 1 when AIN3 voltage is less than or equal to
corresponding V
LOW
limit.
D7
1 when AIN4 voltage is greater than corresponding V
HIGH
limit. 1 when AIN4 voltage is less than or equal to
corresponding V
LOW
limit.
Interrupt Status 2 Register (Read-Only) [Address = 01h]
This 8-bit read-only register reflects the status of the V
DD
and
AIN5AIN8 interrupts that can cause the INT/INT pin to go
active. This register is reset by a read operation provided that
any out-of-limit event has been corrected. It is also reset by a
software reset.
Table 10. Interrupt Status 2 Register
D7 D6 D5 D4 D3 D2 D1 D0
N/A N/A N/A 0* 0* 0* 0* 0*
*Default settings at power-up.
ADT7411
Rev. A | Page 21 of 36
Table 11.
Bit Function
D0
1 when AIN5 voltage is greater than the corresponding
V
HIGH
limit. 1 when AIN5 voltage is less than or equal to
the corresponding V
LOW
limit.
D1
1 when AIN6 voltage is greater than the corresponding
V
HIGH
limit. 1 when AIN6 voltage is less than or equal to
the corresponding V
LOW
limit.
D2
1 when AIN7 voltage is greater than the corresponding
V
HIGH
limit. 1 when AIN7 voltage is less than or equal to
the corresponding V
LOW
limit.
D3
1 when AIN8 voltage is greater than the corresponding
V
HIGH
limit. 1 when AIN8 voltage is less than or equal to
the corresponding V
LOW
limit.
D4
1 when V
DD
value is greater than the corresponding
V
HIGH
limit. 1 when V
DD
is less than or equal to the
corresponding V
LOW
limit.
D5:D7 Reserved
Internal Temperature Value/V
DD
Value Register LSBs
(Read-Only) [Add. = 03h]
This internal temperature value and V
DD
value register is an
8-bit read-only register. It stores the 2 LSBs of the 10-bit temp-
erature reading from the internal temperature sensor and also
the 2 LSBs of the 10-bit supply voltage reading.
Table 12. Internal Temperature/V
DD
LSBs
D7 D6 D5 D4 D3
D2 D1
D0
N/A N/A N/A N/A V1 LSB T1 LSB
N/A N/A N/A N/A 0* 0* 0* 0*
*Default settings at power-up.
Table 13.
Bit Function
D0
LSB of Internal Temperature Value.
D1
B1 of Internal Temperature Value.
D2
LSB of V
DD
Value.
D3
B1 of V
DD
Value.
External Temperature Value and Analog Inputs1 to 4
Register LSBs (Read-Only) [Address = 04h]
This is an 8-bit read-only register. Bits D2D7 store the 2 LSBs
of the analog inputs AIN2AIN4. Bits D0 and D1 are used to
store the 2 LSBs of either the external temperature value or
AIN1 input value. The type of input for D0 and D1 is selected
by Bits 1:2 of the Control Configuration 1 register.
Table 14. External Temperature and AIN14 LSBs
D7
D6 D5
D4 D3
D2 D1
D0
A4 A4
LSB
A3
A3
LSB
A2
A2
LSB
T/A
T/A
LSB
0*
0* 0*
0* 0*
0* 0*
0*
*Default settings at power-up.
Table 15
Bit Function
D0
LSB of External Temperature Value or AIN1 Value.
D1
Bit 1 of External Temperature Value or AIN1 Value.
D2
LSB of AIN2 Value.
D3
Bit 1 of AIN2 Value.
D4
LSB of AIN3 Value.
D5
Bit 1 of AIN3 Value.
D6
LSB of AIN4 Value.
D7
Bit 1 of AIN4 Value.
Analog Inputs 5 to 8 Registers LSBs (Read-Only)
[Add. = 05h]
This is an 8-bit read-only register. Bits D0 to D7 store the 2 LSBs
of the analog inputs AIN5 to AIN8. The MSBs are stored in
Registers 0Ch to 0Fh.
Table 16. External Temperature and AIN5 to AIN8 LSBs
D7 D6
D5 D4
D3 D2
D1 D0
A8 A8
LSB
A7
A7
LSB
A6
A6
LSB
A5
A5
LSB
0* 0*
0* 0*
0* 0*
0* 0*
*Default settings at power-up.
Table 17.
Bit Function
D0
LSB of AIN5 Value.
D1
Bit 1 of AIN5 Value.
D2
LSB of AIN6 Value.
D3
Bit 1 of AIN6 Value.
D4
LSB of AIN7 Value.
D5
Bit 1 of AIN7 Value.
D6
LSB of AIN8 Value.
D7
Bit 1 of AIN8 Value.
V
DD
Value Register MSBs (Read-Only) [Address = 06h]
This 8-bit read-only register stores the supply voltage value. The
8 MSBs of the 10-bit value are stored in this register.
Table 18. V
DD
Value MSBs
D7 D6 D5 D4 D3 D2 D1 D0
V9 V8 V7 V6 V5 V4 V3 V2
x* x* x* x* x* x* x* x*
*Loaded with V
DD
value after power-up.
Internal Temperature Value Register MSBs (Read-Only)
[Address = 07h]
This 8-bit read-only register stores the internal temperature
value from the internal temperature sensor in twos complement
format. This register stores the 8 MSBs of the 10-bit value.
Table 19. Internal Temperature Value MSBs
D7 D6 D5 D4 D3 D2 D1 D0
T9 T8 T7 T6 T5 T4 T3 T2
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
ADT7411
Rev. A | Page 22 of 36
External Temperature Value or Analog Input AIN1
Register MSBs (Read-Only) [Address = 08h]
This 8-bit read-only register stores, if selected, the external
temperature value or the analog input AIN1 value. Selection is
done in Control Configuration 1 register. The external temp-
erature value is stored in twos complement format. The 8 MSBs
of the 10-bit value are stored in this register.
Table 20. External Temperature Value/Analog Inputs MSBs
D7 D6 D5 D4 D3 D2 D1 D0
T/A9 T/A8 T/A7 T/A6 T/A5 T/A4 T/A3 T/A2
0* 0* 0*
0* 0* 0* 0* 0*
*Default settings at power-up.
AIN2 Register MSBs (Read) [Address = 09h]
This 8-bit read register contains the 8 MSBs of the AIN2 analog
input voltage word. The value in this register is combined with
Bits D2:3 of the external temperature value and Analog Inputs 1
to 4 register LSBs, Address 04h, to give the full 10-bit conversion
result of the analog value on the AIN2 pin.
Table 21. AIN2 MSBs
D7
D6 D5 D4 D3 D2 D1 D0
MSB A8 A7 A6 A5 A4 A3 A2
0*
0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN3 Register MSBs (Read) [Address = 0Ah]
This 8-bit read register contains the 8 MSBs of the AIN3 analog
input voltage word. The value in this register is combined with
Bits D4:5 of the external temperature value and Analog Inputs 1
to 4 register LSBs, Address 04h, to give the full 10-bit conver-
sion result of the analog value on the AIN3 pin.
Table 22. AIN3 MSBs
D7
D6 D5 D4 D3 D2 D1 D0
MSB A8 A7 A6 A5 A4 A3 A2
0*
0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN4 Register MSBs (Read) [Address = 0Bh]
This 8-bit read register contains the 8 MSBs of the AIN4 analog
input voltage word. The value in this register is combined with
Bits D6:7 of the external temperature value and Analog Inputs 1
to 4 register LSBs, Address 04h, to give the full 10-bit conver-
sion result of the analog value on the AIN4 pin.
Table 23. AIN4 MSBs
D7
D6 D5 D4 D3 D2
D1 D0
MSB A8 A7 A6 A5
A4 A3 A2
0*
0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN5 Register MSBs (Read) [Address = 0Ch]
This 8-bit read register contains the 8 MSBs of the AIN5 analog
input voltage word. The value in this register is combined with
Bits D0:1 of the Analog Inputs 5 to 8 register LSBs, Address 05h,
to give the full 10-bit conversion result of the analog value on
the AIN5 pin.
Table 24. AIN5 MSBs
D7
D6 D5 D4 D3 D2 D1 D0
MSB A8 A7 A6 A5 A4 A3 A2
0*
0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN6 Register MSBs (Read) [Address = 0Dh]
This 8-bit read register contains the 8 MSBs of the AIN6 analog
input voltage word. The value in this register is combined with
Bits D2:3 of the Analog Inputs 5 to 8 register LSBs, Address 05h,
to give the full 10-bit conversion result of the analog value on
the AIN6 pin.
Table 25. AIN6 MSBs
D7
D6 D5 D4 D3 D2 D1 D0
MSB A8 A7 A6 A5 A4 A3 A2
0*
0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN7 Register MSBs (Read) [Address = 0Eh]
This 8-bit read register contains the 8 MSBs of the AIN7 analog
input voltage word. The value in this register is combined with
Bits D4:5 of the Analog Inputs 5 to 8 register LSBs, Address 05h,
to give the full 10-bit conversion result of the analog value on
the AIN7 pin.
Table 26. AIN7 MSBs
D7
D6 D5 D4 D3
D2 D1 D0
MSB A8 A7 A6 A5 A4 A3 A2
0*
0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN8 Register MSBs (Read) [Address = 0Fh]
This 8-bit read register contains the 8 MSBs of the AIN8 analog
input voltage word. The value in this register is combined with
Bits D6:7 of the Analog Inputs 5 to 8 register LSBs, Address 05h,
to give the full 10-bit conversion result of the analog value on
the AIN8 pin.
Table 27. AIN8 MSBs
D7
D6 D5
D4 D3 D2 D1 D0
MSB A8 A7 A6 A5 A4 A3 A2
0*
0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
Control Configuration 1 Register (Read/Write)
[Address = 18h]
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7411.
Table 28. Control Configuration 1
D7 D6 D5 D4 D3 D2 D1 D0
PD C6 C5 C4
C3 C2 C1 C0
0* 0* 0* 0*
1* 0* 0* 0*
*Default settings at power-up.
ADT7411
Rev. A | Page 23 of 36
Table 29.
Bit Function
C0
This bit enables/disables conversions in round robin
and single-channel mode. ADT7411 powers up in round
robin mode, but monitoring is not initiated until this bit
is set. Default = 0.
0 = Stop monitoring.
1 = Start monitoring.
C2:C1
Selects between the two different analog inputs on Pins
7 and 8. The ADT7411 powers up with AIN1 and AIN2
selected.
00: AIN1 and AIN2 selected.
01:
Undefined.
10: External TDM selected.
11:
Undefined.
C3
Reserved. Write 1 only to this bit.
C4
Reserved. Write 0 only.
C5
0: Enable INT/INT output.
1: Disable INT/INT output.
C6
Configures INT/INT output polarity.
0: Active low.
1: Active high.
PD
Power-Down Bit. Setting this bit to 1 puts the ADT7411
into standby mode. In this mode, the analog circuitry is
fully powered down, but the serial interface is still
operational. To power up the part again, write 0 to this
bit.
Control Configuration 2 Register (Read/Write)
[Address = 19h]
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7411.
Table 30. Control Configuration 2
D7 D6 D5 D4 D3 D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
Table 31.
Bit Function
C3:0
In single-channel mode, these bits select between V
DD
,
the internal temperature sensor, external temperature
sensor/AIN1, AIN2 to AIN8 for conversion. The default is
V
DD
.
0000 = V
DD
.
0001 = Internal Temperature Sensor.
0010 = External Temperature Sensor/AIN1. (Bits C1:C2 of
Control Configuration 1 affect this selection.)
0011 = AIN2.
0100 = AIN3.
0101 = AIN4.
0110 = AIN5.
0111 = AIN6.
1000 = AIN7.
1001 = AIN8.
Bit Function
1010 to 1111 = Reserved.
C4
Selects between single-channel and round robin
conversion cycle. Default is round robin.
0 = Round robin.
1 = Single-channel.
C5
Default condition is to average every measurement on all
channels 16 times. This bit disables this averaging.
Channels affected are temperature, analog inputs, and
V
DD
.
0 = Enable averaging.
1 = Disable averaging.
C6
SMBus timeout on the serial clock puts a 25 ms limit on
the pulse width of the clock, ensuring that a fault on the
master SCL does not lock up the SDA line.
0 = Disable SMBus timeout.
1 = Enable SMBus timeout.
C7
Software Reset. Setting this bit to a 1 causes a software
reset. All registers will reset to their default settings.
Control Configuration 3 Register (Read/Write)
[Address = 1Ah]
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7411.
Table 32. Control Configuration 3
D7 D6 D5 D4 D3 D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
0* 0* 0* 0* 1* 0* 0* 0*
*Default settings at power-up.
Table 33.
Bit Function
C0
Selects between fast and normal ADC conversion
speeds.
0 = ADC clock at 1.4 kHz.
1 = ADC clock at 22.5 kHz. D+ and D- analog filters are
disabled.
C1:2
Reserved. Only write 0s.
C3
Reserved. Write only 1 to this bit.
C4
Selects the ADC reference to be either Internal V
REF
or
V
DD
for analog inputs.
0 = Int V
REF
1 = V
DD
C5:C7
Reserved. Only write 0s.
Interrupt Mask 1 Register (Read/Write) [Address = 1Dh]
This mask register is an 8-bit read/write register that can be
used to mask out any interrupts that can cause the INT/INT pin
to go active.
Table 34. Interrupt Mask 1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*
Default settings at power-up.
ADT7411
Rev. A | Page 24 of 36
Table 35.
Bit Function
D0
0 = Enable internal T
HIGH
interrupt.
1 = Disable internal T
HIGH
interrupt.
D1
0 = Enable internal T
LOW
interrupt.
1 = Disable internal T
LOW
interrupt.
D2
0 = Enable external T
HIGH
interrupt or AIN1 interrupt.
1 = Disable external T
HIGH
interrupt or AIN1 interrupt.
D3
0 = Enable external T
LOW
interrupt.
1 = Disable external T
LOW
interrupt.
D4
0 = Enable external temperature fault interrupt.
1 = Disable external temperature fault interrupt.
D5
0 = Enable AIN2 interrupt.
1 = Disable AIN2 interrupt.
D6
0 = Enable AIN3 interrupt.
1 = Disable AIN3 interrupt.
D7
0 = Enable AIN4 interrupt.
1 = Disable AIN4 interrupt.
Interrupt Mask 2 Register (Read/Write) [Address = 1Eh]
This mask register is an 8-bit read/write register that can be
used to mask out any interrupts that can cause the INT/INT pin
to go active.
Table 36. Interrupt Mask 2
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
Table 37.
Bit Function
D0
0 = Enable AIN5 interrupt.
1 = Disable AIN5 interrupt.
D1
0 = Enable AIN6 interrupt.
1 = Disable AIN6 interrupt.
D2
0 = Enable AIN7 interrupt.
1 = Disable AIN7 interrupt.
D3
0 = Enable AIN8 interrupt.
1 = Disable AIN8 interrupt.
D4
0 = Enable V
DD
interrupts.
1 = Disable V
DD
interrupts.
D5:D7
Reserved. Only write 0s.
Internal Temperature Offset Register (Read/Write)
[Address = 1Fh]
This register contains the offset value for the internal
temperature channel. A twos complement number can be
written to this register, which is then added to the measured
result before it is stored or compared to limits. In this way, a sort
of one-point calibration can be done whereby the whole
transfer function of the channel can be moved up or down.
From a software point of view this may be a very simple method
to vary the characteristics of the measurement channel if the
thermal characteristics change. Because it is an 8-bit register, the
temperature resolution is 1C.
Table 38. Internal Temperature Offset
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
External Temperature Offset Register (Read/Write)
[Address = 20h]
This register contains the offset value for the external tempera-
ture channel. A twos complement number can be written to this
register, which is then added to the measured result before it is
stored or compared to limits. In this way, a sort of one-point
calibration can be done whereby the whole transfer function of
the channel can be moved up or down. From a software point of
view, this may be a very simple method to vary the character-
istics of the measurement channel if the thermal characteristics
change. Because it is an 8-bit register, the temperature resolution
is 1C.
Table 39. External Temperature Offset
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up
V
DD
V
HIGH
Limit Register (Read/Write) [Address = 23h]
This limit register is an 8-bit read/write register that stores the
V
DD
upper limit that will cause an interrupt and activate the
INT/INT output (if enabled). For this to happen, the measured
V
DD
value has to be greater than the value in this register. The
default value is 5.46 V.
Table 40. V
DD
V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3
D2 D1 D0
1* 1* 0* 0* 0* 1* 1* 1*
*Default settings at power-up.
V
DD
V
LOW
Limit Register (Read/Write) [Address = 24h]
This limit register is an 8-bit read/write register that stores the
V
DD
lower limit that will cause an interrupt and activate the
INT/INT output (if enabled). For this to happen, the measured
V
DD
value has to be less than or equal to the value in this regis-
ter. The default value is 2.7 V.
Table 41. V
DD
V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 1* 1* 0* 0* 0* 1* 0*
*Default settings at power-up.
ADT7411
Rev. A | Page 25 of 36
Internal T
HIGH
Limit Register (Read/Write) [Address = 25h]
This limit register is an 8-bit read/write register that stores the
twos complement of the internal temperature upper limit that
will cause an interrupt and activate the INT/INT output (if
enabled). For this to happen, the measured internal temperature
value has to be greater than the value in this register. Because it
is an 8-bit register, the temperature resolution is 1C. The
default value is +100C.
Table 42. Internal T
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 1* 1* 0* 0* 1* 0* 0*
*Default settings at power-up.
Internal T
LOW
Limit Register (Read/Write) [Address = 26h]
This limit register is an 8-bit read/write register that stores the
twos complement of the internal temperature lower limit that
will cause an interrupt and activate the INT/INT output (if
enabled). For this to happen, the measured internal temperature
value has to be more negative than or equal to the value in this
register. Because it is an 8-bit register, the temperature resolu-
tion is 1C. The default value is -55C.
Table 43. Internal T
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1* 1* 0* 0* 1* 0* 0* 1*
*Default settings at power-up.
External T
HIGH
/AIN1 V
HIGH
Limit Register (Read/Write)
[Address = 27h]
If Pins 7 and 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature upper
limit that will cause an interrupt and activate the INT/INT
output (if enabled). For this to happen, the measured external
temperature value has to be greater than the value in this
register. Because it is an 8-bit register, the temperature
resolution is 1C. The default value is -1C.
If Pins 7 and 8 are configured for AIN1 and AIN2 single-ended
inputs, this limit register is an 8-bit read/write register that
stores the AIN1 input upper limit that will cause an interrupt
and activate the INT/INT output (if enabled). For this to hap-
pen, the measured AIN1 value has to be greater than the value
in this register. Because it is an 8-bit register, the resolution is
four times less than the resolution of the 10-bit ADC. Since the
power-up default settings for Pins 7 and 8 are AIN1 and AIN2
single-ended inputs, the default value for this limit register is
full-scale voltage.
Table 44. AIN1 V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up.
External T
LOW
/AIN1 V
LOW
Limit Register (Read/Write)
[Address = 28h]
If Pins 7 and 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature lower
limit that will cause an interrupt and activate the INT/INT
output (if enabled). For this to happen, the measured external
temperature value has to be more negative than or equal to the
value in this register. Since it is an 8-bit register, the temperature
resolution is 1C. The default value is 0C.
If Pins 7 and 8 are configured for AIN1 and AIN2 single-ended
inputs, this limit register is an 8-bit read/write register that
stores the AIN1 input lower limit that will cause an interrupt
and activate the INT/INT output (if enabled). For this to hap-
pen, the measured AIN1 value has to be less than or equal to the
value in this register. Because it is an 8-bit register the resolution
is four times less than the resolution of the 10-Bit ADC. Since
the power-up default settings for Pins 7 and 8 are AIN1 and
AIN2 single-ended inputs, the default value for this limit
register is 0 V.
Table 45. AIN1 V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN2 V
HIGH
Limit Register (Read/Write) [Address = 2Bh]
This limit register is an 8-bit read/write register that stores the
AIN2 input upper limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN2 value has to be greater than the value in this reg-
ister. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is
full-scale voltage.
Table 46. AIN2 V
HIGH
Limit
D7 D6 D5 D4
D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up.
AIN2 V
LOW
Limit Register (Read/Write) [Address = 2Ch]
This limit register is an 8-bit read/write register that stores the
AIN2 input lower limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN2 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 47. AIN2 V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
ADT7411
Rev. A | Page 26 of 36
AIN3 V
HIGH
Limit Register (Read/Write) [Address = 2Dh]
This limit register is an 8-bit read/write register that stores the
AIN3 input upper limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN3 value has to be greater than the value in this reg-
ister. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is
full-scale voltage.
Table 48. AIN3 V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7
D6 D5 D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up.
AIN3 V
LOW
Limit Register (Read/Write) [Address = 2Eh]
This limit register is an 8-bit read/write register that stores the
AIN3 input lower limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN3 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 49. AIN3 V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN4 V
HIGH
Limit Register (Read/Write) [Address = 2Fh]
This limit register is an 8-bit read/write register that stores the
AIN4 input upper limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN4 value has to be greater than the value in this reg-
ister. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is
full-scale voltage.
Table 50. AIN4 V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up.
AIN4 V
LOW
Limit Register (Read/Write) [Address = 30h]
This limit register is an 8-bit read/write register that stores the
AIN4 input lower limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN4 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 51. AIN4 V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN5 V
HIGH
Limit Register (Read/Write) [Address = 31h]
This limit register is an 8-bit read/write register that stores the
AIN5 input upper limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN5 value has to be greater than the value in this reg-
ister. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is
full-scale voltage.
Table 52. AIN5 V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up.
AIN5 V
LOW
Limit Register (Read/Write) [Address = 32h]
This limit register is an 8-bit read/write register that stores the
AIN5 input lower limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the meas-
ured AIN5 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 53. AIN5 V
LOW
Limit
D7 D6 D5 D4 D3 D2
D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN6 V
HIGH
Limit Register (Read/Write) [Address = 33h]
This limit register is an 8-bit read/write register that stores the
AIN3 input upper limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN6 value has to be greater than the value in this reg-
ister. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is
full-scale voltage.
Table 54. AIN6 V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up at power-up.
AIN6 V
LOW
Limit Register (Read/Write) [Address = 34h]
This limit register is an 8-bit read/write register that stores the
AIN6 input lower limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
ADT7411
Rev. A | Page 27 of 36
sured AIN6 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 55. AIN6 V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN7 V
HIGH
Limit Register (Read/Write) [Address = 35h]
This limit register is an 8-bit read/write register that stores the
AIN7 input upper limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN7 value has to be greater than the value in this reg-
ister. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is
full-scale voltage.
Table 56. AIN7 V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up.
AIN7 V
LOW
Limit Register (Read/Write) [Address = 36h]
This limit register is an 8-bit read/write register that stores the
AIN7 input lower limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN7 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 57. AIN7 V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN8 V
HIGH
Limit Register (Read/Write) [Address = 37h]
This limit register is an 8-bit read/write register that stores the
AIN8 input upper limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN8 value has to be greater than the value in this reg-
ister. As it is an 8-bit register, the resolution is four times less
than the resolution of the 10-bit ADC. The default value is full-
scale voltage.
Table 58. AIN8 V
HIGH
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1*
1*
1*
1*
1*
1*
1*
1*
*Default settings at power-up.
AIN8 V
LOW
Limit Register (Read/Write) [Address = 38h]
This limit register is an 8-bit read/write register that stores the
AIN8 input lower limit that will cause an interrupt and activate
the INT/INT output (if enabled). For this to happen, the mea-
sured AIN8 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 59. AIN8 V
LOW
Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
Device ID Register (Read-Only) [Address = 4Dh]
This 8-bit read-only register gives a unique identification
number for this part. ADT7411 = 02h.
Manufacturer's ID Register (Read-Only) [Address = 4Eh]
This register contains the manufacturer's identification number.
ADI's is 41h.
Silicon Revision Register (Read-Only) [Address = 4Fh]
This register is divided into the four LSBs representing the
stepping and the four MSBs representing the version. The step-
ping contains the manufacturer's code for minor revisions or
steppings to the silicon. The version is the ADT7411 version
number, 0100b (4h).
SPI Lock Status Register (Read-Only) [Address = 7Fh]
Bit D0 (LSB) of this read-only register indicates whether the SPI
interface is locked or not. Writing to this register will cause the
device to malfunction. Default value is 00h.
0 = I
2
C interface.
1 = SPI interface selected and locked.
SERIAL INTERFACE
There are two serial interfaces that can be used on this part:
I
2
C and SPI. The device will power up with the serial interface
in I
2
C mode but it is not locked into this mode. To stay in I
2
C
mode, it is recommended that the user tie the CS line to either
V
CC
or GND. It is not possible to lock the I
2
C mode, but it is
possible to select and lock the SPI mode.
To select and lock the interface into the SPI mode, a number of
pulses must be sent down the CS (Pin 4) line. The following
section describes how this is done.
Once the SPI communication protocol has been locked in, it
cannot be unlocked while the device is still powered up. Bit D0
of the SPI Lock Status register (Address 7Fh) is set to 1 when a
successful SPI interface lock has been accomplished. To reset
the serial interface, the user must power down the part and
power up again. A software reset does not reset the serial
interface.
ADT7411
Rev. A | Page 28 of 36
Serial Interface Selection
The CS line controls the selection between I
2
C and SPI.
Figure 16 shows the selection process necessary to lock the SPI
interface mode.
To communicate to the ADT7411 using the SPI protocol, send
three pulses down the CS line as shown in Figure 33. On the
third rising edge (marked as C in Figure 33), the part selects and
locks the SPI interface. Communication to the device is now
limited to the SPI protocol.
As per most SPI standards, the CS line must be low during
every SPI communication to the ADT7411, and high at all other
times. Typical examples of how to connect the dual interface as
I
2
C or SPI are shown in Figure 31 and Figure 32.
02882-A
-
030
ADT7411
CS
SDA
SCL
ADD
V
DD
V
DD
I
2
C ADDRESS = 1001 000
10k
10k
Figure 31. Typical I
2
C Interface Connection
02882-A
-
031
ADT7411
SCLK
DOUT
CS
V
DD
LOCK AND
SELECT SPI
SPI FRAMING
EDGE
820
820
820
DIN
Figure 32. Typical SPI Interface Connection
The following sections describe in detail how to use the I
2
C and
SPI protocols associated with the ADT7411.
I
2
C Serial Interface
Like all I
2
C compatible devices, the ADT7411 has a 7-bit serial
address. The four MSBs of this address for the ADT7411 are set
to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin
can be configured three ways to give three different address
options: low, floating, and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
Address 1001 010, and setting it high gives the Address 1001
011. The recommended pull-up resistor value is 10 k.
There is an enable/disable bit for the SMBus timeout. When this
is enabled, the SMBus will timeout after 25 ms of no activity. To
enable it, set Bit 6 of the Control Configuration 2 register. The
power-up default is with the SMBus timeout disabled.
The ADT7411 supports SMBus packet error checking (PEC)
and its use is optional. It is triggered by supplying the extra
clocks for the PEC byte. The PEC is calculated using CRC-8.
The frame clock sequence (FCS) conforms to CRC-8 by the
polynomial
( )
1
1
2
8
+
+
+
=
x
x
x
x
C
Consult the SMBus specification (www.smbus.org) for more
information.
The serial bus protocol operates as follows:
1.
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of
a 7-bit address (MSB first) plus an R/W bit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W bit is 0, the master will write to
the slave device. If the R/W bit is 1, the master will read
from the slave device.
2.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the receiver of data. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high trans-
ition when the clock is high may be interpreted as a stop
signal.
3.
When all data bytes have been read or written, stop con-
ditions are established. In write mode, the master will pull
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device will pull
the data line high during the low period before the ninth
clock pulse. This is known as No Acknowledge. The master
will then take the data line low during the low period
before the 10th clock pulse, and then high during the 10th
clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation. This is because the type of
operation is determined at the beginning and cannot sub-
sequently be changed without starting a new operation.
ADT7411
Rev. A | Page 29 of 36
The I
2
C address set up by the ADD pin is not latched by
the device until after this address has been sent twice. On
the eighth SCL cycle of the second valid communication,
the serial bus address is latched in. This is the SCL cycle
directly after the device has seen its own I
2
C serial bus
address. Any subsequent changes on this pin will have no
effect on the I
2
C serial bus address.
Writing to the ADT7411
Depending on the register being written to, there are two dif-
ferent writes for the ADT7411. It is not possible to do a block
write to this part, i.e., no I
2
C auto-increment.
Writing to the Address Pointer Register for a Subsequent
Read
In order to read data from a particular register, the address
pointer register must contain the address of that register. If it
does not, the correct address must be written to the address
pointer register by performing a single-byte write operation, as
shown in Figure 34. The write operation consists of the serial
bus address followed by the address pointer byte. No data is
written to any of the data registers. A read operation is then
performed to read the register.
Writing Data to a Register
All registers are 8-bit registers so only one byte of data can be
written to each register. Writing a single byte of data to one of
these read/write registers consists of the serial bus address, the
data register address written to the address pointer register,
followed by the data byte written to the selected data register.
This is illustrated in Figure 35. To write to a different register,
another START or repeated START is required. If more than
one byte of data is sent in one communication operation, the
addressed register will be repeatedly loaded until the last data
byte has been sent.
Reading Data From the ADT7411
Reading data from the ADT7411 is done in a one-byte
operation. Reading back the contents of a register is shown in
Figure 36. The register address had previously been set up by a
single-byte write operation to the Address Pointer register. To
read from another register, write to the Address Pointer register
again to set up the relevant register address. Thus, block reads
are not possible, i.e., no I
2
C auto-increment.
SPI Serial Interface
The SPI serial interface of the ADT7411 consists of four wires:
CS, SCLK, DIN, and DOUT. The CS is used to select the device
when more than one device is connected to the serial clock and
data lines. The CS is also used to distinguish between any two
separate serial communications (see Figure 41 for a graphical
explanation). The SCLK is used to clock data in and out of the
part. The DIN line is used to write to the registers, and the
DOUT line is used to read data back from the registers. The
recommended pull-up resistor value is between 500 and
820 .
02882-A
-
032
A
B
CS
(START HIGH)
SPI LOCKED ON
THIRD RISING EDGE
C
SPI FRAMING
EDGE
A
B
CS
(START LOW)
SPI LOCKED ON
THIRD RISING EDGE
C
SPI FRAMING
EDGE
Figure 33. Serial Interface--Selecting and Locking SPI Protocol
02882-A
-
033
0
1
1
0
0
R/W
SCL
SDA
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADT7411
ACK. BY
ADT7411
STOP BY
MASTER
START BY
MASTER
A2
A1
A
P7
P6
P5
P4
P3
P2
P1
P0
9
1
9
1
Figure 34. I
2
C--Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
ADT7411
Rev. A | Page 30 of 36
02882-A
-
034
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADT7411
ACK. BY
ADT7411
ACK. BY
ADT7411
STOP BY
MASTER
FRAME 3
DATA BYTE
SDA (CONTINUED)
SCL (CONTINUED)
SCL
SDA
START BY
MASTER
1
0
0
1
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
9
D7
D6
D5
D4
D3
D2
D1
D0
R/W
1
9
1
9
1
Figure 35. I
2
C--Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
02882-A
-
035
1
SDA
START BY
MASTER
STOP BY
MASTER
NO ACK. BY
MASTER
ACK. BY
ADT7411
SCL
9
0
0
1
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
SINGLE DATA BYTE FROM ADT7411
1
9
1
Figure 36. I
2
C--Reading a Single Byte of Data from a Selected Register
The part operates in a slave mode and requires an externally
applied serial clock to the SCLK input. The serial interface is
designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
There are two types of serial operation: a read and a write.
Command words are used to distinguish between a read and a
write operation. These command words are given in Table 60.
Address auto-incrementing is possible in SPI mode.
Table 60. SPI Command Words
Write Read
90h (1001 0000)
91h (1001 0001)
Write Operation
Figure 37 shows the timing diagram for a write operation to the
ADT7411. Data is clocked into the registers on the rising edge
of SCLK. When the CS line is high, the DIN and DOUT lines
are in three-state mode. Only when the CS goes from a high to a
low does the part accept any data on the DIN line. In SPI mode,
the address pointer register is capable of auto-incrementing to
the next register in the register map without having to load the
address pointer register each time. In Figure 37, the register
address portion of the diagram gives the first register that will
be written to. Subsequent data bytes will be written into sequen-
tial writable registers. Thus, after each data byte has been writ-
ten into a register, the address pointer register auto-increments
its value to the next available register. The address pointer
register will auto-increment from 00h to 3Fh and then loop
back to start over again at 00h.
Read Operation
Figure 38 to Figure 40 show the timing diagrams of correct read
operations. To read back from a register, first write to the add-
ress pointer register with the address to be read from. This
operation is shown in Figure 38. Figure 39 shows the procedure
for reading back a single byte of data. The read command is first
sent to the part during the first eight clock cycles, during the
following eight clock cycles the data contained in the register
selected by the address pointer register is output onto the
DOUT line. Data is output onto the DOUT line on the falling
edge of SCLK. Figure 40 shows the procedure when reading
data from two sequential registers.
Multiple data reads are possible in SPI interface mode as the
address pointer register is auto-incremental. The address
pointer register will auto-increment from 00h to 3Fh and will
loop back to start all over again at 00h when it reaches 3Fh.
SMBus/SPI INT/INT
The ADT7411 INT/INT output is an interrupt line for devices
that want to trade their ability to master for an extra pin. The
ADT7411 is a slave-only device and uses the SMBus/SPI
INT/INT to signal the host device that it wants to talk. The
SMBus/SPI INT/INT on the ADT7411 is used as an over/under
limit indicator.
ADT7411
Rev. A | Page 31 of 36
The INT/INT pin has an open-drain configuration that allows
the outputs of several devices to be wired-AND together when
the INT/INT pin is active low. Use C6 of the Control Config-
uration 1 register to set the active polarity of the INT/INT out-
put. The power-up default is active low. The INT/INT output
can be disabled or enabled by setting C5 of Control Configur-
ation 1 register to a 1 or 0, respectively.
The INT/INT output becomes active when either the internal
temperature value, the external temperature value, V
DD
value, or
any of the AIN input values exceed the values in their corres-
ponding T
HIGH
/V
HIGH
or T
LOW
/V
LOW
registers. The INT/INT
output goes inactive again when a conversion result has the
measured value back within the trip limits and when the status
register associated with the out-of-limit event is read. The two
Interrupt Status registers show which event caused the INT/INT
pin to go active.
The INT/INT output requires an external pull-up resistor. This
can be connected to a voltage different from V
DD
, provided the
maximum voltage rating of the INT/INT output pin is not
exceeded. The value of the pull-up resistor depends on the
application, but should be as large enough to avoid excessive
sink currents at the INT/INT output, which can heat the chip
and affect the temperature reading.
SMBus Alert Response
The INT/INT pin behaves the same way as an SMBus alert pin
when the SMBus/I
2
C interface is selected. It is an open-drain
output and requires a pull-up to V
DD
. Several INT/INT outputs
can be wire-AND together, so that the common line will go low
if one or more of the INT/INT outputs goes low. The polarity of
the INT/INT pin must be set for active low for a number of
outputs to be wire-AND together.
02882-A
-
036
D7
D6
D5
D4
D3
D2
D1
D6
D5
D4
D3
D2
D1
D0
D0
D7
START
1
8
1
8
CS
SCLK
D
IN
STOP
D7
D6
D5
D4
D3
D2
D1
D0
1
8
CS (CONTINUED)
SCLK (CONTINUED)
DATA BYTE
REGISTER ADDRESS
WRITE COMMAND
D
IN
(CONTINUED)
Figure 37. SPI--Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
02882-A
-
037
D7
D
IN
D6
D5
D4
D3
D2
D1
D6
D5
D4
D3
D2
D1
D0
D0
D7
SCLK
START
WRITE COMMAND
REGISTER ADDRESS
1
8
1
8
CS
STOP
Figure 38. SPI--Writing to the Address Pointer Register to Select a Register for Subsequent Read Operation
ADT7411
Rev. A | Page 32 of 36
02882-A
-
038
D7
D6
D5
D4
D3
D2
D1
X
X
X
X
X
X
X
D0
X
CS
SCLK
D
IN
D
OUT
START
READ COMMAND
DATA BYTE 1
1
8
1
8
X
X
X
X
X
X
X
D6
D5
D4
D3
D2
D1
D0
X
D7
STOP
Figure 39. SPI--Reading a Single Byte of Data from a Selected Register
02882-A
-
039
D7
D6
D5
D4
D3
D2
D1
X
X
X
X
X
X
X
D0
X
CS
SCLK
D
IN
D
OUT
START
READ COMMAND
1
8
1
8
X
X
X
X
X
X
X
D6
D5
D4
D3
D2
D1
D0
X
D7
CS (CONTINUED)
SCLK (CONTINUED)
D
IN
(CONTINUED)
D
OUT
(CONTINUED)
STOP
DATA BYTE 2
DATA BYTE 1
X
X
X
X
X
X
X
X
1
8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 40. SPI---Reading Two Bytes of Data from Two Sequential Registers
02882-A
-
040
CS
SPI
READ OPERATION
WRITE OPERATION
Figure 41. SPI--Correct Use of CS during SPI Communications
The INT/INT output can operate as an SMBALERT function.
Slave devices on the SMBus can normally not signal to the
master that they want to talk, but the SMBALERT function
allows them to do so. SMBALERT is used in conjunction with
the SMBus general call address.
One or more INT/INT outputs can be connected to a common
SMBALERT line connected to the master. When the
SMBALERT line is pulled low by one of the devices, the
following procedure occurs, as shown in Figure 42.
ADT7411
Rev. A | Page 33 of 36
02882-A
-
041
MASTER
RECEIVES
SMBALERT
START ALERT RESPONSE
ADDRESS
RD ACK DEVICE ADDRESS
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS
ITS ADDRESS
NO
ACK STOP
Figure 42. INT/INT Responds to SMBALERT ARA
1.
SMBALERT is pulled low.
2.
Master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3.
The device whose INT/INT output is low responds to the
alert response address and the master reads its device
address. As the device address is seven bits long, an LSB of
1 is added. The address of the device is now known and it
can be interrogated in the usual way.
4.
If more than one device's INT/INT output is low, the one
with the lowest device address will have priority, in
accordance with normal SMBus specifications.
5.
Once the ADT7411 has responded to the alert response
address, it will reset its INT/INT output, provided that the
condition that caused the out-of-limit event no longer
exists and the status register associated with the out-of-
limit event is read. If the SMBALERT line remains low, the
master will send the ARA again. It will continue to do this
until all devices whose SMBALERT outputs were low have
responded.
02882-
A-
042
MASTER
RECEIVES
SMBALERT
START ALERT RESPONSE
ADDRESS
RD ACK
DEVICE
ADDRESS
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS
ITS ADDRESS
DEVICE ACK
ACK
PEC
NO
ACK STOP
MASTER
ACK
MASTER
NACK
DEVICE SENDS
ITS PEC DATA
Figure 43. INT/INT Responds to SMBALERT ARA with
Packet Error Checking (PEC)
ADT7411
Rev. A | Page 34 of 36
OUTLINE DIMENSIONS
16
9
8
1
PIN 1
SEATING
PLANE
0.010
0.004
0.012
0.008
0.025
BSC
0.010
0.006
0.050
0.016
8
0
COPLANARITY
0.004
0.065
0.049
0.069
0.053
0.154
BSC
0.236
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AB
0.193
BSC
Figure 44. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Purchase of licensed I
2
C components of Analog Devices, Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
2
C
Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
ORDERING GUIDE
Model Temperature
Range
Package
Description
Package
Option
Minimum
Quantities/Reel
ADT7411ARQ
-40C to +120C
16-Lead QSOP
RQ-16
N/A
ADT7411ARQ-REEL
-40C to +120C
16-Lead QSOP
RQ-16
2500
ADT7411ARQ-REEL7
-40C to +120C
16-Lead QSOP
RQ-16
1000
ADT7411ARQZ
10
-40C to +120C
16-Lead QSOP
RQ-16
N/A
ADT7411ARQZ-REEL
1
-40C to +120C
16-Lead QSOP
RQ-16
2500
ADT7411ARQZ-REEL7
1
-40C to +120C
16-Lead QSOP
RQ-16
1000
10
Z = Pb-free part.
ADT7411
Rev. A | Page 35 of 36
NOTES
ADT7411
Rev. A | Page 36 of 36
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners..
C02882-0-3/04(A)
Document Outline
- FEATURES
- APPLICATIONS
- PIN CONFIGURATION
- GENERAL DESCRIPTION
-
-
-
-
-
-
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-
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