ADT7475 dBCool Remote Thermal Monitor and Fan Controller Data Sheet (Rev. 0)
dBCool
Remote Thermal
Monitor and Fan Controller
ADT7475
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Extended temperature measurement range, up to 191C
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel Pentium 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully ROHS compliant
GENERAL DESCRIPTION
The ADT7475 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive or power-
sensitive applications requiring active system cooling. The
ADT7475 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans, so they operate at the
lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed
for a given temperature. The effectiveness of the system's
thermal solution can be monitored using the THERM input.
The ADT7475 also provides critical thermal protection to the
system using the bidirectional THERM pin as an output to
prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
05381-
001
BAND GAP
REFERENCE
10-BIT
ADC
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
GND
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
THERMAL
PROTECTION
PERFORMANCE
MONITORING
THERM
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
V
CC
TO ADT7475
V
CC
D1+
D1
D2+
D2
V
CCP
BAND GAP
TEMP. SENSOR
INTERRUPT
MASKING
PWM
CONFIGURATION
REGISTERS
ADDRESS
POINTER
REGISTER
SERIAL BUS
INTERFACE
SCL SDA SMBALERT
ADT7475
Figure 1.
ADT7475
Rev. 0 | Page 2 of 64
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Product Description......................................................................... 9
Quick Comparison Between ADT7473 and ADT7475 .......... 9
Recommended Implementation................................................. 9
Serial Bus Interface..................................................................... 10
Write Operations ........................................................................ 11
Read Operations ......................................................................... 12
SMBus Timeout .......................................................................... 12
Virus Protection.......................................................................... 12
Voltage Measurement Input...................................................... 12
Analog-to-Digital Converter .................................................... 12
Input Circuitry............................................................................ 13
Voltage Measurement Registers................................................ 13
V
CCP
Limit Registers ................................................................... 13
Extended Resolution Registers ................................................. 13
Additional ADC Functions for Voltage Measurements ........ 13
Temperature Measurement Method ........................................ 15
Factors Affecting Diode Accuracy ........................................... 17
Additional ADC Functions for Temperature
Measurement............................................................................... 18
Limits, Status Registers, and Interrupts....................................... 20
Limit Values ................................................................................ 20
Status Registers ........................................................................... 21
THERM Timer ........................................................................... 23
Fan Drive Using PWM Control ............................................... 26
Operating from 3.3 V Standby ................................................. 31
Standby Mode ............................................................................. 31
XNOR Tree Test Mode .............................................................. 31
Power-On Default ...................................................................... 31
Programming the Automatic Fan Speed Control Loop ............ 32
Automatic Fan Control Overview............................................ 32
Step 1: Hardware Configuration .............................................. 33
Recommended Implementation 1 ........................................... 34
Recommended Implementation 2 ........................................... 35
Step 2: Configuring the Mux .................................................... 36
Step 3: T
MIN
Settings for Thermal Calibration Channels ...... 38
Step 4: PWM
MIN
for Each PWM (Fan) Output ...................... 39
Step 5: PWM
MAX
for PWM (Fan) Outputs.............................. 39
Step 6: T
RANGE
for Temperature Channels................................ 40
Step 7: T
THERM
for Temperature Channels ............................... 43
Step 8: T
HYST
for Temperature Channels.................................. 44
Register Tables ................................................................................ 47
Outline Dimensions ....................................................................... 64
Ordering Guide .......................................................................... 64
REVISION HISTORY
7/05--Revision 0: Initial Version
ADT7475
Rev. 0 | Page 3 of 64
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted.
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at T
A
= 25C and represent most likely parametric
norm. Logic inputs accept input high voltages up to V
MAX
even when device is operating down to V
MIN
. Timing specifications are tested at
logic levels of V
IL
= 0.8 V for a falling edge, and V
IH
= 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and
are not production tested.
Table 1.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
POWER SUPPLY
Supply Voltage
3.0
3.3
3.6
V
Supply Current, I
CC
1.5
3
mA
Interface inactive, ADC active
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy
0.5
1.5
C
0C T
A
85C
2.5
C
-40C
T
A
+125C
Resolution
0.25
C
Remote Diode Sensor Accuracy
0.5
1.5
C
0C T
A
85C
2.5
C
-40C
T
A
+125C
Resolution
0.25
C
Remote Sensor Source Current
180
A
High Level
11
Low
Level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENTUATORS)
Total Unadjusted Error (TUE)
1.5
%
Differential Nonlinearity (DNL)
1
LSB
8 bits
Power Supply Sensitivity
0.1
%/V
Conversion Time (Voltage Input)
11
ms
Averaging enabled
Conversion Time (Local Temperature)
12
ms
Averaging enabled
Conversion Time (Remote Temperature)
38
ms
Averaging enabled
Total Monitoring Cycle Time
145
ms
Averaging enabled
19
ms
Averaging
disabled
Input Resistance
90
120
k
For V
CCP
channel
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
6
%
0C
T
A
70C
10
%
-40C
T
A
+120C
Full-Scale Count
65,535
Nominal Input RPM
109
RPM
Fan count = 0xBFFF
329
RPM
Fan count = 0x3FFF
5,000
RPM
Fan count = 0x0438
10,000
RPM
Fan count = 0x021C
OPEN-DRAIN DIGITAL OUTPUTS (PWM1 TO
PWM3, XTO)
Current Sink, I
OL
8.0
mA
Output Low Voltage, V
OL
0.4 V
I
OUT
= -8.0 mA
High Level Output Current, I
OH
0.1
20
A
V
OUT
= V
CC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, V
OL
0.4
V
I
OUT
= -4.0 mA
High Level Output Current, I
OH
0.1
1.0
A
V
OUT
= V
CC
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V
IH
2.0
V
Input Low Voltage, V
IL
0.4
V
Hysteresis
500
mV
ADT7475
Rev. 0 | Page 4 of 64
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
2.0
V
3.6
V
Maximum input voltage
Input Low Voltage, V
IL
0.8
V
-0.3
V
Minimum
input
voltage
Hysteresis
0.5
V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
0.75
V
CC
V
Input Low Voltage, V
IL
0.4
V
DIGITAL INPUT CURRENT
Input High Current, I
IH
1
A
V
IN
= V
CC
Input Low Current, I
IL
1
A
V
IN
= 0
Input Capacitance, C
IN
5
pF
SERIAL BUS TIMING
See
Figure 2
Clock Frequency, f
SCLK
10
400 kHz
Glitch Immunity, t
SW
50
ns
Bus Free Time, t
BUF
4.7
s
SCL Low Time, t
LOW
4.7
s
SCL High Time, t
HIGH
4.0
50 s
SCL, SDA Rise Time, t
r
1,000
ns
SCL, SDA Fall Time, t
f
300
s
Data Setup Time, t
SU;DAT
250
ns
Detect Clock Low Timeout, t
TIMEOUT
15
35
ms
Can be optionally disabled
SCL
SDA
P
S
S
P
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
05381-002
Figure 2. Serial Bus Timing Diagram
ADT7475
Rev. 0 | Page 5 of 64
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (V
CC
) 3.6
V
Voltage on Any Input or Output Pin
-0.3 V to +3.6 V
Input Current at Any Pin
5 mA
Package Input Current
20 mA
Maximum Junction Temperature (T
JMAX
) 150C
Storage Temperature Range
-65C to +150C
Lead Temperature, Soldering
IR Reflow Peak Temperature
260C
Lead Temperature (Soldering 10 sec)
300C
ESD rating
1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
16-lead QSOP package:
JA
= 150C/W
JC
= 39C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADT7475
Rev. 0 | Page 6 of 64
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05381-003
12
11
10
9
D1
D2+
D2
TACH4/THERM/GPIO/
SMBALERT
16
15
14
13
SDA
PWM1/XTO
V
CCP
D1+
5
6
7
8
PWM2/SMBALERT
TACH1
TACH2
PWM3
1
2
3
4
SCL
GND
V
CC
TACH3
ADT7475
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCL
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2
GND
Ground Pin for the ADT7475.
3 V
CC
Power Supply. V
CC
is also monitored through this pin.
4
TACH3
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
5 PWM2/
Digital Output (Open Drain). Requires 10 k typical pull-up. Pulse-width modulated output to control Fan 2
speed. Can be configured as a high or low frequency drive.
SMBALERT
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
6
TACH1
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
7
TACH2
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
8 PWM3
Digital I/O (Open Drain). Pulse-width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 k
typical pull-up. Can be configured as a high or low frequency drive.
9
TACH4
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
THERM
Digital I/O (Open Drain). Alternatively, the pin can be reconfigured as a bidirectional THERM pin, which can be
used to time and monitor assertions on the THERM input. For example, the pin can be connected to the
PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. This pin can
be used as an output to signal overtemperature conditions.
SMBALERT
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
GPIO
General-Purpose Open Drain Digital I/O.
10
D2-
Cathode Connection to Second Thermal Diode.
11
D2+
Anode Connection to Second Thermal Diode.
12
D1-
Cathode Connection to First Thermal Diode.
13
D1+
Anode Connection to First Thermal Diode.
14 V
CCP
Analog Input. Monitors processor core voltage (0 V - 3 V).
15 PWM1 Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 k typical
pull-up.
XTO
Also functions as the output from the XNOR tree in XNOR test mode.
16
SDA
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 k typical pull-up.
ADT7475
Rev. 0 | Page 7 of 64
TYPICAL PERFORMANCE CHARACTERISTICS
0
10
20
30
40
50
60
0
2
4
6
8
10
12
CAPACITANCE (nF)
TE
MP
E
RATURE
E
RROR (
C)
14
16
18
20
22
05381-004
Figure 4. Temperature Error vs. Capacitance between D+ and D-
30
20
10
0
10
20
30
0
20
40
60
LEAKAGE RESISTANCE (M
)
TE
MP
E
RATURE
E
R
ROR (
C)
80
100
40
05381-005
D+ TO V
CC
D+ TO GND
Figure 5. Temperature Error vs. PCB Resistance
30
25
20
15
10
5
0
5
0
100M
200M
300M
400M
500M
600M
NOISE FREQUENCY (Hz)
TE
MP
E
RATURE
E
RROR (
C)
100mV
60mV
40mV
05381-006
Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency
70
60
50
40
30
20
0
10
0
100M
200M
300M
400M
500M
600M
NOISE FREQUENCY (Hz)
TE
MP
E
R
ATURE
E
RROR (
C)
40mV
05381-007
10
60mV
100mV
Figure 7. Remote Temperature Error vs. Differential Mode Noise Frequency
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
3.0
3.1
3.2
3.3
3.4
V
DD
(V)
I
DD
(mA)
1.04
1.02
3.5
3.6
1.00
0.98
05381-008
Figure 8. Normal I
DD
vs. Power Supply
100mV
250mV
15
10
5
0
5
10
15
0
100M
200M
300M
400M
500M
600M
FREQUENCY (Hz)
TE
MP
E
RATURE
E
RROR (
C)
05381-009
Figure 9. Internal Temperature Error vs. Power Supply
ADT7475
Rev. 0 | Page 8 of 64
05381-010
6
4
2
0
2
4
6
0
100M
200M
300M
FREQUENCY (Hz)
TE
MP
E
RATURE
E
RROR (
C)
400M
500M
600M
8
10
12
100mV
250mV
Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
40
20
0
20
40
60
85
OIL BATH TEMPERATURE (
C)
TE
MP
E
RATURE
E
RROR (
C)
1.0
1.5
105
125
05381-011
Figure 11. Internal Temperature Error vs. ADT7475 Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
40
20
0
20
40
60
85
OIL BATH TEMPERATURE (
C)
TE
MP
E
RATURE
E
RROR (
C)
1.0
1.5
105
125
05381-012
2.0
Figure 12. Remote Temperature Error vs. ADT7475 Temperature
ADT7475
Rev. 0 | Page 9 of 64
PRODUCT DESCRIPTION
The ADT7475 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 16),
and an input line for the serial clock (Pin 1). All control and
programming functions for the ADT7475 are performed over
the serial bus. In addition, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
QUICK COMPARISON BETWEEN ADT7473 AND
ADT7475
The ADT7473 supports Advanced Dynamic T
MIN
features
while the ADT7475 does not.
Acoustic smoothing is improved on the ADT7475.
THERM can be selected as an output only on the
ADT7475.
The ADT7475 has two additional configuration registers.
The ADT7475 has other minor register changes.
RECOMMENDED IMPLEMENTATION
Configuring the ADT7475 as in Figure 13 allows the
system designer to use the following features:
Two PWM outputs for fan control of up to three fans
(the front and rear chassis fans are connected in parallel).
Three TACH fan speed measurement inputs.
V
CC
measured internally through Pin 3.
CPU temperature measured using Remote 1 temperature
channel.
Ambient temperature measured through Remote 2
temperature channel.
Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as
an overtemperature THERM output. The THERM pin
can alternatively be programmed as an SMBALERT system
interrupt output.
05381-015
TACH2
PWM3
TACH3
D1+
D1
GND
ADT7475
SCL
SDA
TACH1
PWM1
AMBIENT
TEMPERATURE
SMBALERT
D2+
D2
THERM
PROCHOT
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
Figure 13. ADT7475 Configuration
ADT7475
Rev. 0 | Page 10 of 64
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7475 is carried out
using the SMBus. The ADT7475 is connected to this bus as
a slave device, under the control of a master controller, which
is usually (but not necessarily) the ICH.
The ADT7475 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). Data is sent over the serial bus in sequences
of nine clock pulses: eight bits of data followed by an acknowl-
edge bit from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high transition
when the clock is high might be interpreted as a stop signal. The
number of data bytes that can be transmitted over the serial bus
in a single read or write operation is limited only by what the
master and slave devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the tenth clock pulse to assert a stop condition.
In read mode, the master device overrides the acknowledge bit
by pulling the data line high during the low period before the
ninth clock pulse; this is known as No Acknowledge. The
master takes the data line low during the low period before
the tenth clock pulse, and then high during the tenth clock
pulse to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined
at the beginning and cannot subsequently be changed without
starting a new operation.
In the ADT7475, write operations contain either one or two
bytes, and read operations contain one byte. To write data to
one of the device data registers or read data from it, the address
pointer register must be set so that the correct data register is
addressed, and then data can be written into that register or
read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data is
to be written to the device, the write operation contains a
second data byte that is written to the register selected by the
address pointer register.
This write operation is shown in Figure 14. The device address
is sent over the bus, and then R/W is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
If the ADT7475's address pointer register value is unknown
or not the desired value, it must first be set to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADT7475 as
before, but only the data byte containing the register
address is sent, because no data is written to the register.
This is shown in Figure 15.
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte
read from the data register. This is shown in Figure 16.
If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, as shown in Figure 16.
R/W
0
SCL
SDA
1
0
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7475
START BY
MASTER
1
9
1
ACK. BY
ADT7475
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7475
STOP BY
MASTER
1
9
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
05381-016
Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
ADT7475
Rev. 0 | Page 11 of 64
R/W
0
SCL
SDA
1
0
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7475
STOP BY
MASTER
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
1
9
ACK. BY
ADT7475
9
05381-017
Figure 15. Writing to the Address Pointer Register Only
R/W
0
SCL
SDA
1
0
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADT745
1
1
9
ACK. BY
ADT7475
9
05381-018
Figure 16. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register, because the first data byte of a write
is always written to the address pointer register.
In addition to supporting the send byte and receive byte pro-
tocols, the ADT7475 also supports the read byte protocol.
(See System Management Bus Specifications Rev. 2 for more
information; this document is available from Intel.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for differ-
ent types of read and write operations. The ones used in the
ADT7475 are discussed below. The following abbreviations
are used in the diagrams:
S--START
P--STOP
R--READ
W--WRITE
A--ACKNOWLEDGE
A--NO ACKNOWLEDGE
The ADT7475 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7475, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is illustrated in Figure 17.
05381-019
SLAVE
ADDRESS
W A
S
A
REGISTER
ADDRESS
2
3
1
5
4
P
6
Figure 17. Setting a Register Address for Subsequent Read
If the master is required to read data from the register immedi-
ately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master sends a data byte.
7.
The slave asserts ACK on SDA.
8.
The master asserts a stop condition on SDA, and the
transaction ends.
ADT7475
Rev. 0 | Page 12 of 64
The byte write operation is shown in Figure 18.
05381-020
SLAVE
ADDRESS W A
DATA
S
A
REGISTER
ADDRESS
2
3
1
5
4
A P
6
7 8
Figure 18. Single Byte Write to a Register
READ OPERATIONS
The ADT7475 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been set up previously.
In this operation, the master device receives a single byte from
a slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts NO ACK on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
In the ADT7475, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is shown in Figure 19.
05381-021
SLAVE
ADDRESS
DATA
A
R
S
A
2
4
3
1
5
P
6
Figure 19. Single Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be con-
nected to a common SMBALERT line connected to the master.
If a device's SMBALERT line goes low, the following events
occur:
1.
SMBALERT is pulled low.
2.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
4.
If more than one device's SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
5.
Once the ADT7475 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition is gone.
SMBus TIMEOUT
The ADT7475 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7475 assumes that the
bus is locked and releases the bus. This prevents the device
from locking or holding the SMBus expecting data. Some
SMBus controllers cannot handle the SMBus timeout feature,
so it can be disabled.
Configuration Register 1 (Reg. 0x40)
<6> TODIS = 0,
SMBus timeout enabled (default).
<6> TODIS = 1,
SMBus timeout disabled.
VIRUS PROTECTION
To prevent rogue programs or viruses from accessing critical
ADT7475 register settings, the lock bit can be set. Setting Bit 1
of Configuration Register 1 (0x40) sets the lock bit and locks
critical registers. In this mode, certain registers can no longer be
written to until the ADT7475 is powered down and powered up
again. For more information on which registers are locked,
please see the ADT7475 Registers.
VOLTAGE MEASUREMENT INPUT
The ADT7475 has one external voltage measurement channel.
It can also measure its own supply voltage, V
CC
. Pin 14 can
measure V
CCP
. The V
CC
supply voltage measurement is carried
out through the V
CC
pin (Pin 3). The V
CCP
input can be used to
monitor a chipset supply voltage in computer systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolu-
tion of 10 bits. The basic input range is 0 V to 2.25 V, but the
input has built-in attenuators to allow measurement of V
CCP
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of 3/4 full scale
(decimal 768 or 300 hex) for the nominal input voltage and so
has adequate headroom to deal with overvoltages.
ADT7475
Rev. 0 | Page 13 of 64
INPUT CIRCUITRY
The internal structure for the V
CCP
analog input is shown in
Figure 20. The input circuit consists of an input protection
diode, an attenuator, and a capacitor, to form a first-order
low-pass filter that gives the input immunity to high fre-
quency noise.
05381-022
V
CCP
17.5k
52.5k
35pF
Figure 20. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Reg. 0x21 V
CCP
Reading
= 0x00 default
Reg. 0x22 V
CC
Reading
= 0x00 default
V
CCP
LIMIT REGISTERS
Associated with the V
CCP
measurement channel is a high and
low limit register. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Reg. 0x46 V
CCP
Low Limit
= 0x00 default
Reg. 0x47 V
CCP
High Limit
= 0xFF default
Table 5 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 s and averages 16 conversions to reduce noise; a
measurement takes nominally 11.38 ms.
EXTENDED RESOLUTION REGISTERS
Voltage measurements can be made with higher accuracy using
the extended resolution registers (0x76 and 0x77). Whenever
the extended resolution registers are read, the corresponding
data in the voltage measurement registers (0x20 to 0x 24) is
locked until their data is read. That is, if extended resolution is
required, then the extended resolution register must be read
first, immediately followed by the appropriate voltage
measurement register.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
A number of other functions are available on the ADT7475 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally, and the
results averaged, before being placed into the value register.
For instances where faster conversions are needed, setting Bit 4
of Configuration Register 2 (Reg. 0x73) turns averaging off.
This effectively gives a reading 16 times faster (711 s), but the
reading may be noisier.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes
the attenuation circuitry from the V
CCP
input. This allows
the user to directly connect external sensors, or to rescale the
analog voltage measurement inputs for other applications. The
input range of the ADC without the attenuators is 0 V to 2.25 V.
Single Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7475 into single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read a single voltage chan-
nel only. If the internal ADT7475 clock is used, the selected
input is read every 711 s. The appropriate ADC channel is
selected by writing to Bits <7:5> of the TACH1 minimum high
byte register (0x55).
Table 4. Single Channel ADC Conversion
Bits <7:5> Reg. 0x55
Channel Selected
001 V
CCP
010 V
CC
101
Remote 1 Temperature
110 Local
Temperature
111 Remote
2
Temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1,
averaging off.
<5> = 1,
bypass input attenuators.
<6> = 1,
single channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5>
selects ADC channel for single channel convert mode.
ADT7475
Rev. 0 | Page 14 of 64
Table 5. 10-Bit A/D Output Code vs. V
IN
A/D Output
V
CC
(3.3 V
IN
)
1
V
CCP
Decimal
Binary (10 Bits)
<0.0042
<0.00293
0
00000000 00
0.00420.0085
0.02930.0058
1
00000000 01
0.00850.0128
0.00580.0087
2
00000000 10
0.01280.0171
0.00870.0117
3
00000000 11
0.01710.0214
0.01170.0146
4
00000001 00
0.02140.0257
0.01460.0175
5
00000001 01
0.02570.0300
0.01750.0205
6
00000001 10
0.03000.0343
0.02050.0234
7
00000001 11
0.03430.0386
0.02340.0263
8
00000010 00
1.1001.1042
0.75000.7529
256 (1/4-scale)
01000000 00
2.2002.2042
1.50001.5029
512 (1/2-scale)
10000000 00
3.3003.3042
2.25002.2529
768 (3/4 scale)
11000000 00
4.35274.3570
2.96772.9707
1013
11111101 01
4.35704.3613
2.97072.9736
1014
11111101 10
4.36134.3656
2.97362.9765
1015
11111101 11
4.36564.3699
2.97652.9794
1016
11111110 00
4.36994.3742
2.97942.9824
1017
11111110 01
4.37424.3785
2.98242.9853
1018
11111110 10
4.37854.3828
2.98532.9882
1019
11111110 11
4.38284.3871
2.98822.9912
1020
11111111 00
4.38714.3914
2.99122.9941
1021
11111111 01
4.39144.3957
2.99412.9970
1022
11111111 10
>4.3957
>2.9970
1023
11111111 11
1
The V
CC
output codes listed assume that V
CC
is 3.3 V, and V
CC
should never exceed 3.6 V.
ADT7475
Rev. 0 | Page 15 of 64
TEMPERATURE MEASUREMENT METHOD
Local Temperature Measurement
The ADT7475 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip, 10-bit ADC. The 8-bit
MSB temperature data is stored in the temperature registers
(Address 0x25, 0x26, and 0x27). Because both positive and
negative temperatures can be measured, the temperature data is
stored in Offset 64 format or twos complement format, as shown
in Table 6 and Table 7.
Theoretically, the temperature sensor and ADC can measure
temperatures from -63C to +127C (or -61C to +191C in
the extended temperature range) with a resolution of 0.25C.
However, this exceeds the operating temperature range of
the device, so local temperature measurements outside the
ADT7475 operating temperature range are not possible.
Remote Temperature Measurement
The ADT7475 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pin 10 and
Pin 11, or Pin 12 and Pin 13.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about 2 mV/C. Unfortunately, the absolute value
of V
BE
varies from device to device and individual calibration is
required to null this out, so the technique is unsuitable for mass
production.
05381-023
D+
BIAS
DIODE
V
DD
TO ADC
V
OUT+
V
OUT
REMOTE
SENSING
TRANSISTOR
D
THERMDA
THERMDC
I
N
I
I
BIAS
LOW-PASS FILTER
f
C
= 65kHz
CPU
Figure 21. Signal Conditioning for Remote Diode Temperature Sensors
ADT7475
Rev. 0 | Page 16 of 64
The technique used in the ADT7475 is to measure the change
in V
BE
when the device is operated at two different currents.
This is given by
V
BE
= KT/q 1n(N)
where:
K is Boltzmann's constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
Figure 21 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could also be a discrete
transistor such as a 2N3904/2N3906.
If a discrete transistor is used, the collector is not grounded
and should be linked to the base. If a PNP transistor is used,
the base is connected to the D- input and the emitter to the
D+ input. If an NPN transistor is used, the emitter is connected
to the D- input and the base to the D+ input. Figure 22 and
Figure 23 show how to connect the ADT7475 to an NPN
or PNP transistor for temperature measurement. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D- input.
To measure V
BE
, the sensor is switched between operating
currents of I and N
I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise, and to a
chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce
a dc voltage proportional to V
BE
. This voltage is measured
by the ADC to give a temperature output in 10-bit, twos
complement format. To further reduce the effects of noise,
digital filtering is performed by averaging the results of
16 measurement cycles.
A remote temperature measurement takes nominally 38 ms. The
results of remote temperature measurements are stored in 10-bit,
twos complement format, as shown in Table 6. The extra resolu-
tion for the temperature measurements is held in the Extended
Resolution Register 2 (Reg. 0x77). This gives temperature
readings with a resolution of 0.25C.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ pin and
D- pin to help combat the effects of noise. However, large capaci-
tances affect the accuracy of the temperature measurement,
leading to a recommended maximum capacitor value of 1000 pF.
This capacitor reduces the noise, but does not eliminate it.
Sometimes, this sensor noise is a problem in a very noisy
environment. In most cases, a capacitor is not required as
differential inputs, by their very nature, have a high immunity
to noise.
2N3904
NPN
ADT7475
D+
D
05381-025
Figure 22. Measuring Temperature Using an NPN Transistor
2N3906
PNP
ADT7475
D+
D
05381-026
Figure 23. Measuring Temperature Using a PNP Transistor
ADT7475
Rev. 0 | Page 17 of 64
FACTORS AFFECTING DIODE ACCURACY
Remote Sensing Diode
The ADT7475 is designed to work with either substrate
transistors built into processors or with discrete transistors.
Substrate transistors are generally PNP types with the collector
connected to the substrate. Discrete types can be either PNP
or NPN transistors connected as a diode (base-shorted to the
collector). If an NPN transistor is used, the collector and base
are connected to D+ and the emitter to D-. If a PNP transistor
is used, the collector and base are connected to D- and the
emitter is connected to D+.
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
The ideality factor, n
f
, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7475 is trimmed for an n
f
value of 1.008. Use the
following equation to calculate the error introduced at a
temperature T (C), when using a transistor whose n
f
does not equal 1.008. See the processor data sheet for the
n
f
values.
T = (n
f
- 1.008) (273.15 K + T)
To factor this in, the user can write the T value to the
offset register. The ADT7475 then automatically adds it
to or subtracts it from the temperature measurement.
Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7475, I
HIGH
, is 180 A and the low level current,
I
LOW
, is 11 A. If the ADT7475 current levels do not match
the current levels specified by the CPU manufacturer, it
might be necessary to remove an offset. The CPU's data
sheet advises whether this offset needs to be removed and
how to calculate it. This offset can be programmed to the
offset register. If more than one offset must be considered,
the algebraic sum of these offsets must be programmed to
the offset register.
If a discrete transistor is used with the ADT7475, the best
accuracy is obtained by choosing devices according to the
following criteria:
Base-emitter voltage greater than 0.25 V at 11 A, at the
highest operating temperature.
Base-emitter voltage less than 0.95 V at 180 A, at the
lowest operating temperature.
Base resistance less than 100 .
Small variation in h
FE
(approximately 50 to 150) that
indicates tight control of V
BE
characteristics.
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
Table 6. Twos Complement Temperature Data Format
Temperature
Digital Output (10-Bit)
1
128C
1000 0000 00 (diode fault)
50C
1100 1110 00
25C
1110 0111 00
10C
1111 0110 00
0C
0000 0000 00
10.25C
0000 1010 01
25.5C
0001 1001 10
50.75C
0011 0010 11
75C
0100 1011 00
100C
0110 0100 00
125C
0111 1101 00
127C
0111 1111 00
1
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25C resolution.
Table 7. Extended Range, Temperature Data Format
Temperature
Digital Output (10-Bit)
1
64C
0000 0000 00 (diode fault)
1C
0011 1111 00
0C
0100 0000 00
1C
0100 0001 00
10C
0100 1010 00
25C
0101 1001 00
50C
0111 0010 00
75C
1000 1001 00
100C
1010 0100 00
125C
1011 1101 00
191C
1111 1111 00
1
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25C resolution.
Nulling Out Temperature Errors
As CPUs run faster, it is more difficult to avoid high frequency
clocks when routing the D+/D traces around a system board.
Even when recommended layout guidelines are followed, some
temperature errors may still be attributable to noise coupled
onto the D+/D lines. Constant high frequency noise usually
attenuates, or increases, temperature measurements by a linear,
constant value.
The ADT7475 has temperature offset registers at
Addresses 0x70, 0x72 for the Remote 1 and Remote 2
temperature channels. By doing a one-time calibration of
the system, the user can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement 8-bit reading to
every temperature measurement.
ADT7475
Rev. 0 | Page 18 of 64
Changing Bit 1 of Configuration Register 5 (0x7C) changes the
resolution and therefore the range of the temperature offset as
either having a range of 63C to +127C, with a resolution of
1C, or having a range of -63C to +64C, with a resolution of
0.5C. This temperature offset can be used to compensate for
linear temperature errors introduced by noise.
Temperature Offset Registers
Reg. 0x70, Remote 1 Temperature Offset = 0x00 (0C default)
Reg. 0x71, Local Temperature Offset = 0x00 (0C default)
Reg. 0x72, Remote 2 Temperature Offset = 0x00 (0C default)
ADT7463/ADT7475 Backwards Compatible Mode
By setting Bit 0 of Configuration Register 5 (0x7C), all tempera-
ture measurements are stored in the zone temp value registers
(0x25, 0x26, and 0x27) in twos complement in the range -63C
to +127C. The temperature limits must be reprogrammed in
twos complement.
If a twos complement temperature below -63C is entered, the
temperature is clamped to -63C. In this mode, the diode fault
condition remains -128C = 1000 0000, while in the extended
temperature range (-63C to +191C), the fault condition is
represented by -64C = 0000 0000.
Temperature Measurement Registers
Reg. 0x25, Remote 1 Temperature
Reg. 0x26, Local Temperature
Reg. 0x27, Remote 2 Temperature
Reg. 0x77, Extended Resolution 2 = 0x00 default
<7:6> TDM2
, Remote 2 Temperature LSBs.
<5:4> LTMP
, Local Temperature LSBs.
<3:2> TDM1
, Remote 1 Temperature LSBs.
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are high
and low limit registers. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts (depending on the
way the interrupt mask register is programmed and assuming
that SMBALERT is set as an output on the appropriate pin).
Reg. 0x4E, Remote 1 Temperature Low Limit = 0x81 default
Reg. 0x4F, Remote 1 Temperature High Limit = 0x7F default
Reg. 0x50, Local Temperature Low Limit = 0x81 default
Reg. 0x51, Local Temperature High Limit = 0x7F default
Reg. 0x52, Remote 2 Temperature Low Limit = 0x81 default
Reg. 0x53, Remote 2 Temperature High Limit = 0x7F default
Reading Temperature from the ADT7475
It is important to note that temperature can be read from the
ADT7475 as an 8-bit value (with 1C resolution) or as a 10-bit
value (with 0.25C resolution). If only 1C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading
registers have been read from. This prevents an MSB reading
from being updated while its two LSBs are being read and
vice versa.
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7475 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally, and the results
averaged, before being placed into the value register. Sometimes
it is necessary to take a very fast measurement. Setting Bit 4 of
Configuration Register 2 (Reg. 0x73) turns averaging off. The
default round-robin cycle time takes 146.5 ms.
Table 8. Conversion Time with Averaging Disabled
Channel Measurement
Time
(ms)
Voltage Channels
0.7
Remote Temperature 1
7
Remote Temperature 2
7
Local Temperature
1.3
When bit 7 of configuration register 6 (0x10) is set, the default
round-robin cycle time increases to 240 ms.
Table 9. Conversion Time with Averaging Enabled
Channel Measurement
Time
(ms)
Voltage Channels
11
Remote Temperature
39
Local Temperature
12
ADT7475
Rev. 0 | Page 19 of 64
Single Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7475 into single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read a single temperature
channel only. The appropriate ADC channel is selected by
writing to Bits <7:5> of the TACH1 minimum high byte
register (0x55).
Table 10. Programming Single Channel ADC Mode
for Temperatures
Bits <7:5> Reg. 0x55
Channel Selected
101
Remote 1 temperature
110 Local
temperature
111
Remote 2 temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1,
averaging off.
<6> = 1,
single channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5>
selects ADC channel for single channel convert mode.
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Register 0x6A to Register 0x6C are the THERM
temperature limits. When a temperature exceeds its THERM
temperature limit, all PWM outputs run at the maximum
PWM duty cycle (Reg. 0x38, Reg. 0x39, and Reg. 0x3A).
This effectively runs the fans at the fastest allowed speed.
The fans run at this speed until the temperature drops below
THERM minus hysteresis. This can be disabled by setting the
boost bit in Configuration Register 3, Bit 2, Reg. 0x78. The
hysteresis value for the THERM temperature limit is the value
programmed into Reg. 0x6D and Reg. 0x6E (hysteresis
registers). The default hysteresis value is 4C.
FANS
TEMPERATURE
100%
HYSTERESIS (
C)
THERM LIMIT
05381-027
Figure 24. THERM Temperature Limit Operation
THERM can be disabled on specific temperature channels using
bits <7:5> of configuration register 5 (0x7C). THERM can also
be disabled by:
In offset 64 mode, writing -64C to the appropriate THERM
temperature limit.
In twos complement mode, writing -128C to the
appropriate THERM temperature limit.
ADT7475
Rev. 0 | Page 20 of 64
LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
Associated with each measurement channel on the ADT7475
are high and low limits. These can form the basis of system
status monitoring; a status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor
or microcontroller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7475.
Voltage Limit Registers
Reg. 0x46 V
CCP
Low Limit
= 0x00 default
Reg. 0x47 V
CCP
High Limi
t = 0xFF default
Reg. 0x48 V
CC
Low Limit
= 0x00 default
Reg. 0x49 V
CC
High Limit
= 0xFF default
Temperature Limit Registers
Reg. 0x4E Remote 1 Temperature Low Limit = 0x01 default
Reg. 0x4F Remote 1 Temperature High Limit = 0x7F default
Reg. 0x6A Remote 1 THERM Limit = 0x64 default
Reg. 0x50 Local Temperature Low Limit = 0x01 default
Reg. 0x51 Local Temperature High Limit = 0x7F default
Reg. 0x6B Local THERM Limit = 0x64 default
Reg. 0x52 Remote 2 Temperature Low Limit = 0x01 default
Reg. 0x53 Remote 2 Temperature High Limit = 0x7F default
Reg. 0x6C Remote 2 THERM Limit = 0x64 default
THERM Limit Register
Reg. 0x7A THERM Limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Because fans running under speed or stalled are normally the
only conditions of interest, only high limits exist for fan TACHs.
Because the fan TACH period is actually being measured,
exceeding the limit indicates a slow or stalled fan.
Fan Limit Registers
Reg. 0x54 TACH1 Minimum Low Byte = 0x00 default
Reg. 0x55 TACH1 Minimum High Byte = 0x00 default
Reg. 0x56 TACH2 Minimum Low Byte = 0x00 default
Reg. 0x57 TACH2 Minimum High Byte = 0x00 default
Reg. 0x58 TACH3 Minimum Low Byte = 0x00 default
Reg. 0x59 TACH3 Minimum High Byte = 0x00 default
Reg. 0x5A TACH4 Minimum Low Byte = 0x00 default
Reg. 0x5B TACH4 Minimum High Byte = 0x00 default
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7475 can
be enabled for monitoring. The ADT7475 measures all voltage
and temperature measurements in round-robin format and
sets the appropriate status bit for out-of-limit conditions.
TACH measurements are not part of this round-robin cycle.
Comparisons are done differently, depending on whether
the measured value is being compared to a high or low limit.
High Limit: > Comparison Performed
Low Limit: Comparison Performed
Voltage and temperature channels use a window comparator
for error detecting and, therefore, have high and low limits.
Fan speed measurements use only a low limit. This fan limit
is needed only in manual fan control mode.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40).
By default, the ADT7463 powers up with this bit set. The ADC
measures each analog input in turn and, as each measurement
is completed, the result is automatically stored in the appropri-
ate value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
As the ADC is normally left to free-run in this manner, the time
taken to monitor all the analog inputs is normally not of inter-
est, because the most recently measured value of any input can
be read out at any time.
For applications where the monitoring cycle time is impor-
tant, it can easily be calculated. The total number of channels
measured is
One dedicated supply voltage input (V
CCP
)
Supply voltage (V
CC
pin)
Local temperature
Two remote temperatures
ADT7475
Rev. 0 | Page 21 of 64
As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged
voltage and temperature monitoring is 146 ms. The total
monitoring cycle time for voltage and temperature moni-
toring with averaging disabled is 19 ms. The ADT7475 is a
derivative of the ADT7467. As a result, the total conversion
time in the ADT7475 is the same as the total conversion time
of the ADT7467.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
STATUS REGISTERS
The results of limit comparisons are stored in Status Register 1
and Status Register 2. The status register bit for each channel
reflects the status of the last measurement and limit comparison
on that channel. If a measurement is within limits, the corre-
sponding status register bit is cleared to 0. If the measurement
is out-of-limits, the corresponding status register bit is set to 1.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. In Bit 7 (OOL) of
Status Register 1 (Reg. 0x41), 1 means that an out-of-limit event
has been flagged in Status Register 2. This means that the user
needs only to read Status Register 2 when this bit is set. Alterna-
tively, Pin 5 or Pin 9 can be configured as an SMBALERT output.
This automatically notifies the system supervisor of an out-of-
limit condition. Reading the status registers clears the appropriate
status bit as long as the error condition that caused the interrupt
has cleared.
Status register bits are sticky. Whenever a status bit is set,
indicating an out-of-limit condition, it remains set even if the
event that caused it has gone away (until read). The only way to
clear the status bit is to read the status register after the event
has gone away. Interrupt status mask registers (Reg. 0x74, 0x75)
allow individual interrupt sources to be masked from causing
an SMBALERT. However, if one of these masked interrupt
sources goes out-of-limit, its associated status bit is set in the
interrupt status registers.
Status Register 1 (Reg. 0x41)
Bit 7 (OOL) = 1
, denotes a bit in Status Register 2 is set and
Status Register 2 should be read.
Bit 6 (R2T) = 1
, Remote 2 temperature high or low limit has
been exceeded.
Bit 5 (LT) = 1
, local temperature high or low limit has been
exceeded.
Bit 4 (R1T) = 1
, Remote 1 temperature high or low limit has
been exceeded.
Bit 2 (V
CC
) = 1,
V
CC
high or low limit has been exceeded.
Bit 1 (V
CCP
) = 1
, V
CCP
high or low limit has been exceeded.
Status Register 2 (Reg. 0x42)
Bit 7 (D2) = 1
, indicates an open or short on D2+/D2 inputs.
Bit 6 (D1) = 1
, indicates an open or short on D1+/D1 inputs.
Bit 5 (F4P) = 1
, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates the THERM limit has been
exceeded, if the THERM function is used.
Bit 4 (FAN3) = 1
, indicates Fan 3 has dropped below minimum
speed.
Bit 3 (FAN2) = 1
, indicates Fan 2 has dropped below minimum
speed.
Bit 2 (FAN1) = 1
, indicates Fan 1 has dropped below minimum
speed.
Bit 1 (OVT) = 1
, indicates a THERM overtemperature limit has
been exceeded.
SMBALERT Interrupt Behavior
The ADT7475 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. Note
how the SMBALERT output and status bits behave when
writing interrupt handler software.
"STICKY"
STATUS BIT
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
05381-028
Figure 25. SMBALERT and Status Bit Behavior
Figure 25 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are referred
to as sticky, because they remain set until read by software. This
ensures an out-of-limit event cannot be missed, if software is
polling the device periodically. Note the SMBALERT output
remains low for the entire duration that a reading is out-of-limit
and until the status register has been read. This has implications
on how software handles the interrupt.
ADT7475
Rev. 0 | Page 22 of 64
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts, it
is recommended to handle the SMBALERT interrupt as follows:
1.
Detect the SMBALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74, Reg. 0x75).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in
.
Figure 26
"STICKY"
STATUS BIT
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
SMBALERT
05381-029
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Figure 26. How Masking the Interrupt Source
Affects SMBALERT Output
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Address 0x74
and Address 0x75. These allow individual interrupt sources to
be masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
normally.
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1
, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1
, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1
, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1
, masks SMBALERT for Remote 1 temperature.
Bit 2 (V
CC
) = 1
, masks SMBALERT for V
CC
channel.
Bit 0 (V
CCP
) = 1
, masks SMBALERT for V
CCP
channel.
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1
, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1
, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1
, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1
, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1
, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1
, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1
, masks SMBALERT for overtemperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default. Pin 5
or Pin 9 can be reconfigured as an SMBALERT output to signal
out-of-limit conditions.
Table 11. Configuring Pin 5 as SMBALERT Output
Register Bit
Setting
Configuration Register 3 (Reg. 0x78)
<0> ALERT = 1
Assigning THERM Functionality to a Pin
Pin 9 on the ADT7475 has four possible functions: SMBus
ALERT, THERM, GPIO, and TACH4. The user chooses the
required functionality by setting Bit 0 and Bit 1 of Configura-
tion Register 4 at Address 0x7D.
Table 12. Pin 9 Configuration
Bit 0
Bit 1
Function
0 0 TACH4
0 1 THERM
1 0 SMBus
ALERT
1 1 GPIO
Once Pin 9 is configured as THERM, it must be enabled (Bit 1,
Configuration Register 3 at Address 0x78).
THERM as an Input
When THERM is configured as an input, the user can time
assertions on the THERM pin. This can be useful for connect-
ing to the PROCHOT output of a CPU to gauge system
performance.
ADT7475
Rev. 0 | Page 23 of 64
The user can also set up the ADT7475 so when the THERM pin
is driven low externally, the fans run at 100%. The fans run at
100% for the duration of the time that the THERM pin is
pulled low. This is done by setting the BOOST bit (Bit 2) in
Configuration Register 3 (Address = 0x78) to 1. This works
only if the fan is already running, for example, in manual mode
when the current duty cycle is above 0x00, or in automatic mode
when the temperature is above T
MIN
. If the temperature is below
T
MIN
or if the duty cycle in manual mode is set to 0x00, then pull-
ing the THERM low externally has no effect. See
for
more information.
Figure 27
05381-030
THERM
T
MIN
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100%, BECAUSE
TEMPERATURE IS BELOW T
MIN
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100%, BECAUSE
TEMPERATURE IS ABOVE T
MIN
AND FANS
ARE ALREADY RUNNING
Figure 27. Asserting THERM Low as an Input in Automatic Fan Speed Control
Mode
THERM TIMER
The ADT7475 has an internal timer to measure THERM
assertion time. For example, the THERM input can be con-
nected to the PROCHOT output of a Pentium 4 CPU to
measure system performance. The THERM input can also be
connected to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7475's THERM
input and stopped when THERM is unasserted. The timer counts
THERM times cumulatively, that is, the timer resumes counting
on the next THERM assertion. The THERM timer continues to
accumulate THERM assertion times until the timer is read (it is
cleared on read) or until it reaches full scale. If the counter
reaches full scale, it stops at that reading until cleared.
The 8-bit THERM timer register (Reg. 0x79) is designed so
that the Bit 0 is set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit 1
of the THERM timer is set and Bit 0 now becomes the LSB of
the timer with a resolution of 22.76 ms (see
).
Figure 28
When using the THERM timer, be aware of the following.
After a THERM timer read (Reg. 0x79):
1.
The contents of the timer are cleared on read.
2.
The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming that the THERM timer limit has been
exceeded).
If the THERM timer is read during a THERM assertion, the
following happens:
1.
The contents of the timer are cleared.
2.
Bit 0 of the THERM timer is set to 1 (because a THERM
assertion is occurring).
3.
The THERM timer increments from zero.
4.
If the THERM timer limit (Reg. 0x7A) = 0x00, then the
F4P bit is set.
THERM
THERM
TIMER
(REG. 0x79)
THERM ASSERTED
22.76ms
7 6 5
3 2 1 0
4
0 0 0
0 0 0 1
0
THERM
TIMER
(REG. 0x79)
THERM ASSERTED
45.52ms
7 6 5
3 2 1 0
4
0 0 0
0 0 1 0
0
THERM
TIMER
(REG. 0x79)
THERM ASSERTED
113.8ms
(91.04ms + 22.76ms)
7 6 5
3 2 1 0
4
0 0 0
0 1 0 1
0
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
05381-031
Figure 28. Understanding the THERM Timer
ADT7475
Rev. 0 | Page 24 of 64
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7475 can generate SMBALERTs when a programma-
ble THERM timer limit has been exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions,
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 sec (first THERM assertion) to 5.825 sec to be set
before an SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit register.
If the THERM timer value exceeds the THERM timer limit
value, then the F4P bit (Bit 5) of Status Register 2 is set, and
an SMBALERT is generated. Note the F4P bit (Bit 5) of Mask
Register 2 (Reg. 0x75) masks out SMBALERTs, if this bit is set
to 1; although the F4P bit of Interrupt Status Register 2 still is
set, if the THERM timer limit is exceeded.
Figure 29 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM timer
limit value of 0x01 generates an SMBALERT, once cumulative
THERM assertions exceed 45.52 ms.
22.76ms
45.52ms
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
IN
OUT
RESET
LATCH
CLEARED
ON READ
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
1 = MASK
F4P BIT (BIT 5)
STATUS REGISTER 2
COMPARATOR
22.76ms
45.52ms
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0
THERM
TIMER LIMIT
(REG. 0x7A)
THERM TIMER
(REG. 0x79)
THERM TIMER CLEARED ON READ
SMBALERT
THERM
05381-032
Figure 29. Functional Block Diagram of ADT7475's THERM Monitoring Circuitry
ADT7475
Rev. 0 | Page 25 of 64
Configuring the THERM Behavior
1.
Configure the relevant pin as the THERM timer input.
Setting Bit 1 (THERM timer enable) of Configuration
Register 3 (Reg. 0x78) enables the THERM timer
monitoring functionality. This is disabled on Pin 9 by
default.
Setting Bit 0 and Bit 1 (PIN9FUNC) of Configuration
Register 4 (Reg. 0x7D) enables THERM timer/output
functionality on Pin 9 (Bit 1 of Configuration
Register 3, THERM, must also be set). Pin 9 can also
be used as TACH4.
2.
Select the desired fan behavior for THERM timer
events.
Assuming that the fans are running, setting Bit 2
(BOOST bit) of Configuration Register 3 (Reg. 0x78)
causes all fans to run at 100% duty cycle whenever
THERM gets asserted. This allows fail-safe system
cooling. If this bit is 0, the fans run at their current
settings and are not affected by THERM events. If the
fans are not already running when THERM is
asserted, the fans do not run to full speed.
3.
Select whether THERM timer events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set,
masks out SMBALERTs when the THERM timer limit
value gets exceeded. This bit should be cleared if
SMBALERTs based on THERM events are required.
4.
Select a suitable THERM limit value.
This value determines whether an SMBALERT is
generated on the first THERM assertion, or only if a
cumulative THERM assertion time limit is exceeded.
A value of 0x00 causes an SMBALERT to be generated
on the first THERM assertion.
5.
Select a THERM monitoring time.
This value specifies how often OS or BIOS level
software checks the THERM timer. For example,
BIOS could read the THERM timer once an hour to
determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system
performance is degrading significantly because
THERM is asserting more frequently on an hourly
basis.
Alternatively, OS- or BIOS-level software can timestamp
when the system is powered on. If an SMBALERT is gen-
erated due to the THERM timer limit being exceeded,
another timestamp can be taken. The difference in time
can be calculated for a fixed THERM timer limit time.
For example, if it takes one week for a THERM timer limit
of 2.914 sec to be exceeded and the next time it takes only
1 hour, then this is an indication of a serious degradation
in system performance.
Configuring the THERM Pin as an Output
In addition to monitoring THERM as an input, the ADT7475
can optionally drive THERM low as an output. In cases where
PROCHOT is bidirectional, THERM can be used to throttle the
processor by asserting PROCHOT. The user can preprogram
system-critical thermal limits. If the temperature exceeds a
thermal limit by 0.25C, THERM asserts low. If the tempera-
ture is still above the thermal limit on the next monitoring
cycle, THERM stays low. THERM remains asserted low until
the temperature is equal to or below the thermal limit. Because
the temperature for that channel is measured only once for
every monitoring cycle, after THERM asserts it is guaranteed
to remain low for at least one monitoring cycle.
The THERM pin can be configured to assert low, if the Remote 1,
local, or Remote 2 THERM temperature limits are exceeded
by 0.25C. The THERM temperature limit registers are at
Registers 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3 of
Registers 0x5F, 0x60, and 0x61 enables the THERM output
feature for the Remote 1, local, and Remote 2 temperature
channels, respectively. Figure 33 shows how the THERM pin
asserts low as an output in the event of a critical
overtemperature.
MONITORING
CYCLE
TEMP
THERM LIMIT
0.25
C
THERM LIMIT
THERM
05381-033
Figure 30. Asserting THERM as an Output, Based on Tripping
THERM Limits
An alternative method of disabling THERM is to program the
THERM temperature limit to -64C or less in Offset 64 mode,
or -128C or less in twos complement mode; that is, for
THERM temperature limit values less than -63C or -128C,
respectively, THERM is disabled.
ADT7475
Rev. 0 | Page 26 of 64
Enabling and Disabling THERM on Individual Channels
THERM can be enabled/disabled for individual or combina-
tions of temperature channels using bits <7:5> of Configuration
Register 5 (0x7C).
THERM Hysteresis
Setting Bit 0 of Configuration Register 7 (0x11) disables
THERM hysteresis.
If THERM hysteresis is enabled and THERM is disabled (Bit 2
of Configuration Register 4, 0x7D), the THERM pin does not
assert low when a THERM event occurs. If THERM hysteresis
is disabled and THERM is disabled (Bit 2 of Configuration
Register 4, 0x7D and assuming the appropriate pin is config-
ured as THERM), the THERM pin asserts low when a THERM
event occurs.
If THERM and THERM hysterisis are both enabled, the
THERM output asserts as expected.
THERM Operation in Manual mode
In Manual mode, THERM events do not cause fans to go to full
speed, unless Bit 3 of Configuration Register 6 (0x10) is set to 1.
Additionally, Bit 3 of Configuration Register 4 (0x7D) can
be used to select PWM speed on THERM event (100% or
maximum PWM).
Bit 2 in Configuration Register 4 (0x7D) can be set to disable
THERM events from affecting the fans.
FAN DRIVE USING PWM CONTROL
The ADT7475 uses pulse-width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan to vary the fan speed. The
external circuitry required to drive a fan using PWM control is
extremely simple. For 4-wire fans, the PWM drive might need
only a pull-up resistor. In many cases, the 4-wire fan PWM
input has a built-in pull-up resistor.
The ADT7475 PWM frequency can be set to a selection of
low frequencies or a single high PWM frequency. The low
frequency options are usually used for 3-wire fans, while the
high frequency option us usually used with 4-wire fans.
For 3-wire fans, a single N-channel MOSFET is the only drive
device required. The specifications of the MOSFET depend on
the maximum current required by the fan being driven. Typical
notebook fans draw a nominal 170 mA, so SOT devices can be
used where board space is a concern. In desktops, fans can
typically draw 250 mA to 300 mA each. If you drive several
fans in parallel from a single PWM output or drive larger
server fans, the MOSFET must handle the higher current
requirements.
The only other stipulation is that the MOSFET should have a
gate voltage drive, V
GS
< 3.3 V, for direct interfacing to the
PWM output pin. The MOSFET should also have a low on
resistance to ensure that there is not significant voltage drop
across the FET, which would reduce the voltage applied across
the fan and, therefore, the maximum operating speed of the fan.
Figure 31 shows how to drive a 3-wire fan using PWM control.
05381-034
ADT7475
TACH/AIN
PWM
12V
FAN
Q1
NDT3055L
3.3V
12V
12V
10k
4.7k
10k
10k
1N4148
Figure 31. Driving a 3-Wire Fan Using an N-Channel MOSFET
Figure 31 uses a 10 k pull-up resistor for the TACH signal. This
assumes that the TACH signal is an open-collector from the fan.
In all cases, the TACH signal from the fan must be kept below
3.6 V maximum to prevent damaging the ADT7475. If in doubt
as to whether the fan used has an open-collector or totem pole
TACH output, use one of the input signal conditioning circuits
shown in the Fan Speed Measurement section.
Figure 32 shows a fan drive circuit using an NPN transistor
such as a general-purpose MMBT2222. While these devices
are inexpensive, they tend to have much lower current han-
dling capabilities and higher on resistance than MOSFETs.
When choosing a transistor, care should be taken to ensure
that it meets the fan's current requirements.
Ensure that the base resistor is chosen, so the transistor is
saturated when the fan is powered on.
05381-035
ADT7475
TACH
TACH
PWM
12V
FAN
Q1
MMBT2222
3.3V
12V
12V
665
4.7k
10k
10k
1N4148
Figure 32. Driving a 3-Wire Fan Using an NPN Transistor
ADT7475
Rev. 0 | Page 27 of 64
Because 4-wire fans are powered continuously, the fan speed is
not switched on or off as with previous PWM driven/powered
fans. This enables it to perform better than 3-wire fans, espe-
cially for high frequency applications. Figure 33 shows a typical
drive circuit for 4-wire fans.
05381-036
ADT7475
TACH
PWM
12V, 4-WIRE FAN
3.3V
12V 12V
2k
4.7k
10k
10k
V
CC
TACH
TACH
PWM
Figure 33. Driving a 4-Wire Fan
Driving Two Fans from PWM3
The ADT7475 has four TACH inputs available for fan speed
measurement, but only three PWM drive outputs. If a fourth
fan is being used in the system, it should be driven from the
PWM3 output in parallel with the third fan. Figure 34 shows
how to drive two fans in parallel using low cost NPN
transistors. Figure 35 shows the equivalent circuit using a
MOSFET.
05381-037
ADT7475
PWM3
3.3V
3.3V
12V
1N
4148
Q1
MMBT3904
Q2
MMBT2222
Q3
MMBT2222
10
10
2.2k
1k
TACH3
TACH4
Figure 34. Interfacing Two Fans in Parallel to the PWM3 Output Using Low
Cost NPN Transistors
05381-038
ADT7475
PWM3
TACH3
TACH4
3.3V
3.3V
3.3V
+V
+V
TACH
TACH
Q1
NDT3055L
1N4148
5V OR
12V FAN
5V OR
12V FAN
10k
TYPICAL
10k
TYPICAL
10k
TYPICAL
Figure 35. Interfacing Two Fans in Parallel to the PWM3 Output Using a
Single N-Channel MOSFET
Because the MOSFET can handle up to 3.5 A, it is simply a
matter of connecting another fan directly in parallel with the
first. Care should be taken in designing drive circuits with
transistors and FETs to ensure that the PWM pins are not
required to source current and that they sink less than the
8 mA maximum current specified on the data sheet.
Driving up to Three Fans from PWM3
TACH measurements for fans are synchronized to particular
PWM channels; for example, TACH1 is synchronized to
PWM1. TACH3 and TACH4 are both synchronized to PWM3,
so PWM3 can drive two fans. Alternatively, PWM3 can be pro-
grammed to synchronize TACH2, TACH3, and TACH4 to the
PWM3 output. This allows PWM3 to drive two or three fans.
In this case, the drive circuitry looks the same, as shown in
Figure 37 and Figure 38. The SYNC bit in Register 0x62 enables
this function.
Synchronization is not required in high frequency mode when
used with 4-wire fans.
<4> (SYNC) Enhance Acoustics Register 1 (Reg. 0x62)
SYNC = 1
, synchronizes TACH2, TACH3, and TACH4
to PWM3.
TACH Inputs
Pin 4, Pin 6, Pin 7, and Pin 9, when configured as TACH
inputs, are open-drain TACH inputs intended for fan speed
measurement.
Signal conditioning in the ADT7475 accommodates the slow
rise and fall times typical of fan tachometer outputs. The maxi-
mum input signal range is 0 V to 3.6 V. In the event these inputs
are supplied from fan outputs that exceed 0 V to 3.6 V, either
resistive attenuation of the fan signal or diode clamping must be
included to keep inputs within an acceptable range.
Figure 36 to Figure 39 show circuits for most common fan
TACH outputs. If the fan TACH output has a resistive pull-up
to V
CC
, it can be connected directly to the fan input, as shown
in Figure 36.
05381-039
12V
V
CC
PULL-UP
4.7k
TYPICAL
TACH
OUTPUT
FAN SPEED
COUNTER
TACH
ADT7475
Figure 36. Fan with TACH Pull-Up to V
B
CC
ADT7475
Rev. 0 | Page 28 of 64
If the fan output has a resistive pull-up to 12 V, or other voltage
greater than 3.6 V, the fan output can be clamped with a Zener
diode, as shown in Figure 37. The Zener diode voltage should
be chosen so that it is greater than V
IH
of the TACH input but
less than 3.6 V, allowing for the voltage tolerance of the Zener.
A value between 3 V and 3.6 V is suitable.
05381-040
12V
V
CC
PULL-UP
4.7k
TYPICAL
TACH
OUTPUT
FAN SPEED
COUNTER
TACH
ADT7475
ZD1*
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8
V
CC
Figure 37. Fan with TACH Pull-Up to Voltage > 3.6 V (for example, 12 V)
Clamped with Zener Diode
If the fan has a strong pull-up (less than 1 k) to 12 V or a
totem-pole output, then a series resistor can be added to limit
the Zener current, as shown in Figure 38.
05381-041
5V OR 12V
V
CC
PULL-UP TYP
<1k
OR
TOTEM POLE
TACH
OUTPUT
FAN SPEED
COUNTER
TACH
ADT7475
ZD1
ZENER*
FAN
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8
V
CC
R1
10k
Figure 38. Fan with Strong TACH Pull-Up to > V
CC
or Totem-Pole Output,
Clamped with Zener and Resistor
Alternatively, a resistive attenuator can be used, as shown in
Figure 39. R1 and R2 should be chosen such that
2 V < V
PULL-UP
R2/(R
PULL-UP
+ R1 + R2) < 3.6 V
The fan inputs have an input resistance of nominally 160 k to
ground, which should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than
1 k, suitable values for R1 and R2 would be 100 k and 47 k,
respectively. This gives a high input voltage of 3.83 V.
05381-042
12V
V
CC
<1k
TACH
OUTPUT
FAN SPEED
COUNTER
TACH
ADT7475
R2*
*SEE TEXT
R1*
Figure 39. Fan with Strong TACH Pull-Up to > V
CC
or Totem-Pole Output,
Attenuated with R1/R2
Fan Speed Measurement
The fan counter does not count the fan TACH output pulses
directly, because the fan speed could be less than 1,000 RPM
and it would take several seconds to accumulate a reasonably
large and accurate count. Instead, the period of the fan revolu-
tion is measured by gating an on-chip 90 kHz oscillator into the
input of a 16-bit counter for N periods of the fan TACH output
(Figure 40), so the accumulated count is actually proportional
to the fan tachometer period and inversely proportional to the
fan speed.
N, the number of pulses counted, is determined by the set-
tings of Register 0x7B (TACH pulses per revolution register).
This register contains two bits for each fan, allowing one, two
(default), three, or four TACH pulses to be counted.
05381-043
1
2
3
4
CLOCK
PWM
TACH
Figure 40. Fan Speed Measurement
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7475.
Reg. 0x28 TACH1 Low Byte = 0x00 default
Reg. 0x29 TACH1 High Byte = 0x00 default
Reg. 0x2A TACH2 Low Byte = 0x00 default
Reg. 0x2B TACH2 High Byte = 0x00 default
Reg. 0x2C TACH3 Low Byte = 0x00 default
Reg. 0x2D TACH3 High Byte = 0x00 default
Reg. 0x2E TACH4 Low Byte = 0x00 default
Reg. 0x2F TACH4 High Byte = 0x00 default
ADT7475
Rev. 0 | Page 29 of 64
Reading Fan Speed from the ADT7475
The measurement of fan speeds involves a 2-register read for
each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read, preventing erroneous TACH readings.
The fan tachometer reading registers report back the number of
11.11 s period clocks (90 kHz oscillator) gated to the fan speed
counter, from the rising edge of the first fan TACH pulse to the
rising edge of the third fan TACH pulse (assuming two pulses per
revolution are being counted). Because the device is essentially
measuring the fan TACH period, the higher the count value, the
slower the fan is actually running. A 16-bit fan tachometer read-
ing of 0xFFFF indicates either that the fan has stalled or is
running very slowly (<100 RPM).
High Limit: > Comparison Performed
Because the actual fan TACH period is being measured, falling
below a fan TACH limit by 1 sets the appropriate status bit and
can be used to generate an SMBALERT.
Fan TACH Limit Registers
The fan TACH limit registers are 16-bit values consisting of
two bytes.
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default
Reg. 0x55 TACH1 Minimum High Byte = 0xFF default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default
Reg. 0x57 TACH2 Minimum High Byte = 0xFF default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF default
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF default
Fan Speed Measurement Rate
The fan TACH readings are normally updated once every
second. The FAST bit (Bit 3) of Configuration Register 3
(Reg. 0x78), when set, updates the fan TACH readings
every 250 ms.
If any of the fans are not being driven by a PWM channel but
are powered directly from 5 V or 12 V, their associated dc bit
in Configuration Register 3 should be set. This allows TACH
readings to be taken on a continuous basis for fans connected
directly to a dc source. For optimal results, the associated dc bit
should always be set when using 4-wire fans.
Calculating Fan Speed
Assuming a fan with a two pulses per revolution (and two
pulses per revolution being measured) fan speed is calculated
by the following:
Fan Speed (RPM) = (90,000 60)/Fan TACH Reading
where Fan TACH Reading is the 16-bit fan tachometer reading.
Example
TACH1 High Byte (Reg. 0x29) = 0x17
TACH1 Low Byte (Reg. 0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 TACH Reading = 0x17FF = 6143 (decimal)
RPM = (f 60)/Fan 1 TACH Reading
RPM = (90000 60)/6143
Fan Speed = 879 RPM
Fan Pulses per Revolution
Different fan models can output either 1, 2, 3, or 4 TACH pulses
per revolution. Once the number of fan TACH pulses has been
determined, it can be programmed into the fan pulses per
revolution register (Reg. 0x7B) for each fan.
Alternatively, this register can be used to determine the number
or pulses per revolution output by a given fan. By plotting fan
speed measurements at 100% speed with different pulses per
revolution setting, the smoothest graph with the lowest ripple
determines the correct pulses per revolution value.
Fan Pulses per Revolution Register
<1:0>
Fan 1 default = 2 pulses per revolution.
<3:2>
Fan 2 default = 2 pulses per revolution.
<5:4>
Fan 3 default = 2 pulses per revolution.
<7:6>
Fan 4 default = 2 pulses per revolution.
00 = 1 pulse per revolution.
01 = 2 pulses per revolution.
10 = 3 pulses per revolution.
11 = 4 pulses per revolution.
ADT7475
Rev. 0 | Page 30 of 64
Fan Spin-Up
The ADT7475 has a unique fan spin-up function. It spins the fan
at 100% PWM duty cycle until two TACH pulses are detected on
the TACH input. Once two TACH pulses have been detected, the
PWM duty cycle goes to the expected running value, for example,
33%. The advantage is that fans have different spin-up charac-
teristics and take different times to overcome inertia. The
ADT7475 runs the fans just fast enough to overcome inertia
and is quieter on spin-up than fans programmed to spin up for
a given spin-up time.
Fan Startup Timeout
To prevent the generation of false interrupts as a fan spins up
(because it is below running speed), the ADT7475 includes a
fan startup timeout function. During this time, the ADT7475
looks for two TACH pulses. If two TACH pulses are not
detected, an interrupt is generated. Using Configuration
Register 4 (0x40) Bit 5 (FSPDIS), this functionality can be
changed (see the Disabling Fan Startup Timeout section).
PWM1, 2, 3 Configuration (Reg. 0x5C, 0x5D, 0x5E)
<2:0> SPIN
, startup timeout for PWM1=0x5C, PWM2=0x5D
and PWM3=0x5E.
000 = No startup timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
Disabling Fan Startup Timeout
Although fan startup makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up
times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1
(Reg. 0x40) disables the spin-up for two TACH pulses. Instead,
the fan spins up for the fixed time as selected in Reg. 0x5C to
Reg. 0x5E.
PWM Logic State
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or low for 100% duty cycle (inverted).
PWM1 Configuration (Reg. 0x5C)
<4> INV
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
PWM2 Configuration (Reg. 0x5D)
<4> INV
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
PWM3 Configuration (Reg. 0x5E)
<4> INV
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Reg. 0x5F to Reg. 0x61 configure the PWM frequency for
PWM1 to PWM3, respectively. In high frequency mode, the
PWM drive frequency is always 22.5 kHz.
High Frequency Mode PWM Drive
Setting Bit 3 of registers 0x5F, 0x60, 0x61 enables high
frequency mode for fan1, fan 2 and fan 3, respectively.
PWM1 Frequency Registers (Reg. 0x5F to Reg. 0x61)
<2:0> FREQ
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz default
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
Fan Speed Control
The ADT7475 controls fan speed using two modes: automatic
and manual, as follows:
In automatic fan speed control mode, fan speed is automatically
varied with temperature and without CPU intervention, once
initial parameters are set up. The advantage of this is, if the
system hangs, the user is guaranteed the system is protected
from overheating. For more information and how to program
the automatic fan speed control loop, see the Programming the
Automatic Fan Speed Control Loop section.
In manual fan speed control mode, the ADT7475 allows the
duty cycle of any PWM output to be manually adjusted. This
can be useful, if the user wants to change fan speed at the
software level, or adjust PWM duty cycle output for test
purposes. Bits <7:5> of Reg. 0x5C to Reg. 0x5E (PWM
Configuration) control the behavior of each PWM output.
ADT7475
Rev. 0 | Page 31 of 64
PWM Configuration Register (Reg. 0x5C to Reg. 0x5E)
<7:5> BHVR
111 = manual mode.
Once under manual control, each PWM output can be manu-
ally updated by writing to Reg. 0x30 to Reg. 0x32 (PWMx
current duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers, which
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
The value to be programmed into the PWM
MIN
register is
given by
Value (decimal) = PWM
MIN
/0.39
Example 1
: For a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2
: For a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
PWM Duty Cycle Registers
Reg. 0x30 PWM1 Duty Cycle = 0x00 (0% default)
Reg. 0x31 PWM2 Duty Cycle = 0x00 (0% default)
Reg. 0x32 PWM3 Duty Cycle = 0x00 (0% default)
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode. See the Programming the
Automatic Fan Speed Control Loop section for details.
OPERATING FROM 3.3 V STANDBY
The ADT7475 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states.
When monitoring THERM, the THERM timer should be
disabled during these states.
STANDBY MODE
The ADT7475 has been specifically designed to respond to the
STBY supply. In computers that support S3 and S5 states, the
core voltage of the processor is lowered in these states. When
monitoring THERM, the THERM timer should be disabled
during these states.
When the V
CCP
voltage drops below the V
CCP
low limit, the
following occurs:
1.
Status Bit 1 (V
CCP
) in Status Register 1 is set.
2.
SMBALERT is generated, if enabled.
3.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
Once the core voltage, V
CCP
, goes above the V
CCP
low limit,
everything is re-enabled and the system resumes normal
operation.
XNOR TREE TEST MODE
The ADT7475 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
Figure 41 shows the signals that are exercised in the XNOR
tree test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (Reg. 0x6F).
PWM1/XTO
PWM3
PWM2
TACH4
TACH3
TACH2
TACH1
05381-044
Figure 41. XNOR Tree Test
POWER-ON DEFAULT
When the ADT7475 is powered up, monitoring is off by default
and the PWM outputs go to 100%. All necessary registers then
need to be configured via the SMBus for the appropriate
functions to operate.
ADT7475
Rev. 0 | Page 32 of 64
PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP
To more efficiently understand the automatic fan speed control
loop, it is strongly recommended to use the ADT7475 evalua-
tion board and software while reading this section.
This section provides the system designer with an understanding
of the automatic fan control loop, and provides step-by-step
guidance on effectively evaluating and selecting critical system
parameters. To optimize the system characteristics, the designer
needs to give some thought to system configuration, including
the number of fans, where they are located, and what tempera-
tures are being measured in the particular system.
The mechanical or thermal engineer who is tasked with the
system thermal characterization should also be involved at
the beginning of this process.
AUTOMATIC FAN CONTROL OVERVIEW
The ADT7475 can automatically control the speed of fans based
upon the measured temperature. This is done independently of
CPU intervention once initial parameters are set up.
The ADT7475 has a local temperature sensor and two remote
temperature channels that can be connected to a CPU on-chip
thermal diode (available on Intel Pentium class and other
CPUs). These three temperature channels can be used as the
basis for automatic fan speed control to drive fans using pulse-
width modulation (PWM).
Automatic fan speed control reduces acoustic noise by
optimizing fan speed according to accurately measured
temperature. Reducing fan speed can also decrease system
current consumption.
The automatic fan speed control mode is very flexible owing to
the number of programmable parameters, including T
MIN
and
T
RANGE
. The T
MIN
and T
RANGE
values for a temperature channel,
and, therefore, for a given fan are critical because they define
the thermal characteristics of the system. The thermal vali-
dation of the system is one of the most important steps in the
design process, so select these values carefully.
Figure 42 gives a top-level overview of the automatic fan control
circuitry on the ADT7475. From a systems-level perspective,
up to three system temperatures can be monitored and used to
control three PWM outputs. The three PWM outputs can be used
to control up to four fans. The ADT7475 allows the speed of four
fans to be monitored. Each temperature channel has a thermal
calibration block, allowing the designer to individually configure
the thermal characteristics of each temperature channel.
For example, one can decide to run the CPU fan when CPU
temperature increases above 60C and a chassis fan when the
local temperature increases above 45C. At this stage, the
designer has not assigned these thermal calibration settings
to a particular fan drive (PWM) channel. The right side of
Figure 42 shows controls that are fan-specific. The designer
has individual control over parameters such as minimum
PWM duty cycle, fan speed failure thresholds, and even ramp
control of the PWM outputs. Automatic fan control, then,
ultimately allows graceful fan speed changes that are less
perceptible to the system user.
05381-046
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
REMOTE 1
TEMP
LOCAL
TEMP
REMOTE 2
TEMP
PWM
MIN
PWM1
TACH1
TACH2
TACH3
PWM
MIN
PWM2
PWM
MIN
PWM3
100%
PWM
GENERATOR
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
PWM
CONFIG
PWM
CONFIG
PWM
CONFIG
Figure 42. Automatic Fan Control Block Diagram
ADT7475
Rev. 0 | Page 33 of 64
STEP 1: HARDWARE CONFIGURATION
During system design, the motherboard sensing and control
capabilities should be addressed early in the design stages.
Decisions about how these capabilities are used should involve
the system thermal/mechanical engineer. Ask the following
questions:
1.
What ADT7475 functionality will be used?
PWM2 or SMBALERT?
TACH4 fan speed measurement or overtemperature
THERM function?
The ADT7475 offers multifunctional pins that can be
reconfigured to suit different system requirements and
physical layouts. These multifunction pins are software
programmable.
2.
How many fans will be supported in system, three or four?
This influences the choice of whether to use the TACH4
pin or to reconfigure it for the THERM function.
3.
Is the CPU fan to be controlled using the ADT7475 or will
it run at full speed 100% of the time?
If run at 100%, this frees up a PWM output, but the system
is louder.
4.
Where will the ADT7475 be physically located in the
system?
This influences the assignment of the temperature meas-
urement channels to particular system thermal zones.
For example, locating the ADT7475 close to the VRM
controller circuitry allows the VRM temperature to be
monitored using the local temperature channel.
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
REMOTE 1 =
AMBIENT TEMP
LOCAL =
VRM TEMP
REMOTE 2 =
CPU TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
PWM
MIN
PWM
MIN
PWM
MIN
100%
05381-047
PWM
GENERATOR
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
PWM
CONFIG
PWM
CONFIG
PWM
CONFIG
Figure 43. Hardware Configuration Example
ADT7475
Rev. 0 | Page 34 of 64
RECOMMENDED IMPLEMENTATION 1
Configuring the ADT7475 as in Figure 44 provides the system
designer with the following features:
1.
Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
2.
Three TACH fan speed measurement inputs.
3.
V
CC
measured internally through Pin 4.
4.
CPU core voltage measurement (V
CORE
).
5.
VRM temperature using local temperature sensor.
6.
CPU temperature measured using the Remote 1
temperature channel.
7.
Ambient temperature measured through the Remote 2
temperature channel.
8.
Bidirectional THERM pin allows the monitoring
of PROCHOT output from an Intel P4 processor,
for example, or can be used as an overtemperature
THERM output.
9.
SMBALERT system interrupt output.
05381-048
FRONT
CHASSIS
FAN
TACH2
ADT7475
PWM3
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
TACH3
D1+
D1
GND
PWM1
TACH1
D2+
D2
THERM
SMBALERT
SDA
SCL
PROCHOT
CPU FAN
CPU
ICH
Figure 44. Recommended Implementation 1
ADT7475
Rev. 0 | Page 35 of 64
RECOMMENDED IMPLEMENTATION 2
Configuring the ADT7475 as in Figure 45 provides the system
designer with the following features:
1.
Three PWM outputs for fan control of up to three fans.
(All three fans can be individually controlled.)
2.
Three TACH fan speed measurement inputs.
3.
V
CC
measured internally through Pin 4.
4.
CPU core voltage measurement (V
CORE
).
5.
CPU temperature measured using the Remote 1
temperature channel.
6.
Ambient temperature measured through the Remote 2
temperature channel.
7.
Bidirectional THERM pin allows the monitoring of
PROCHOT output from an Intel P4 processor, for
example, or can be used as an overtemperature THERM
output.
05381-049
FRONT
CHASSIS
FAN
TACH2
ADT7475
PWM3
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
TACH3
D1+
D1
GND
PWM1
TACH1
D2+
D2
THERM
SDA
SCL
PROCHOT
CPU FAN
CPU
ICH
Figure 45. Recommended Implementation 2
ADT7475
Rev. 0 | Page 36 of 64
STEP 2: CONFIGURING THE MUX
After the system hardware configuration is determined,
the fans can be assigned to particular temperature channels.
Not only can fans be assigned to individual channels, but the
behavior of the fans is also configurable. For example, fans can
be run under automatic fan control, can be run manually, under
software control, or can be run at the fastest speed calculated by
multiple temperature channels. The mux is the bridge between
temperature measurement channels and the three PWM
outputs.
Bits <7:5> (BHVR)
of Registers 0x5C, 0x5D, and 0x5E
(PWM configuration registers) control the behavior of the
fans connected to the PWM1, PWM2, and PWM3 outputs.
The values selected for these bits determine how the mux
connects a temperature measurement channel to a PWM
output.
Automatic Fan Control Mux Options
<7:5> (BHVR),
Registers 0x5c, 0x5d, 0x5e.
000 = Remote 1 temperature controls PWMx
001 = local temperature controls PWMx
010 = Remote 2 temperature controls PWMx
101 = Fastest speed calculated by local and Remote 2
temperature controls PWMx
110 = Fastest speed calculated by all three temperature
channels controls PWMx
The Fastest Speed Calculated options pertain to controlling
one PWM output based on multiple temperature channels.
The thermal characteristics of the three temperature zones
can be set to drive a single fan. An example would be the fan
turning on when Remote 1 temperature exceeds 60C, or if
the local temperature exceeds 45C.
Other Mux Options
<7:5> (BHVR),
Registers 0x5c, 0x5d, 0x5e.
011 = PWMx runs full speed
100 = PWMx disabled (default)
111 = manual mode. PWMx is running under soft-
ware control. In this mode, PWM duty cycle registers
(Registers 0x30 to 0x32) are writable and control the
PWM outputs.
MUX
05381-050
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
REMOTE 1 =
AMBIENT TEMP
LOCAL =
VRM TEMP
REMOTE 2 =
CPU TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
PWM
MIN
PWM
MIN
PWM
MIN
100%
PWM
GENERATOR
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
PWM
CONFIG
PWM
CONFIG
PWM
CONFIG
Figure 46. Assigning Temperature Channels to Fan Channels
ADT7475
Rev. 0 | Page 37 of 64
Mux Configuration Example
This is an example of how to configure the mux in a system
using the ADT7475 to control three fans. The CPU fan sink
is controlled by PWM1, the front chassis fan is controlled by
PWM 2, and the rear chassis fan is controlled by PWM3. The
mux is configured for the following fan control behavior:
PWM1 (CPU fan sink) is controlled by the fastest speed
calculated by the local (VRM temperature) and Remote 2
(processor) temperature. In this case, the CPU fan sink is
also being used to cool the VRM.
PWM2 (front chassis fan) is controlled by the Remote 1
temperature (ambient).
PWM3 (rear chassis fan) is controlled by the Remote 1
temperature (ambient).
Example Mux Settings
<7:5> (BHVR),
PWM1 Configuration Register 0x5c.
101 = Fastest speed calculated by local and Remote 2
temperature controls PWM1
<7:5> (BHVR),
PWM2 Configuration Register 0x5d.
000 = Remote 1 temperature controls PWM2
<7:5> (BHVR),
PWM3 Configuration Register 0x5e.
000 = Remote 1 temperature controls PWM3
These settings configure the mux, as shown in Figure 47.
05381-051
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
PWM
MIN
PWM
MIN
PWM
MIN
100%
MUX
PWM
GENERATOR
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
PWM
CONFIG
PWM
CONFIG
PWM
CONFIG
Figure 47. Mux Configuration Example
ADT7475
Rev. 0 | Page 38 of 64
STEP 3: T
MIN
SETTINGS FOR THERMAL
CALIBRATION CHANNELS
T
MIN
is the temperature at which the fans start to turn on under
automatic fan control. The speed at which the fan runs at T
MIN
is
programmed later in the process. The T
MIN
values chosen are
temperature channel specific, for example, 25C for ambient
channel, 30C for VRM temperature, and 40C for processor
temperature.
T
MIN
is an 8-bit value, either twos complement or Offset 64,
that can be programmed in 1C increments. There is a
T
MIN
register associated with each temperature measure-
ment channel: Remote 1 Local, and Remote 2 Temperature.
Once the T
MIN
value is exceeded, the fan turns on and runs at
the minimum PWM duty cycle. The fan turns off once the
temperature has dropped below T
MIN
- T
HYST
.
To overcome fan inertia, the fan is spun up until two valid
TACH rising edges are counted. See the Fan Startup Timeout
section for more details. In some cases, primarily for psycho-
acoustic reasons, it is desirable that the fan never switch off
below T
MIN
. Bits <7:5> of Enhanced Acoustics Register 1
(Reg. 0x62), when set, keep the fans running at the PWM
minimum duty cycle, if the temperature should fall below T
MIN
.
T
MIN
Registers
Reg. 0x67, Remote 1 Temperature T
MIN
= 0x9A (90C)
Reg. 0x68, Local Temperature T
MIN
= 0x9A (90C)
Reg. 0x69, Remote 2 Temperature T
MIN
= 0x9A (90C)
Enhance Acoustics Register 1 (Reg. 0x62)
Bit 7 (MIN3) = 0,
PWM3 is off (0% PWM duty cycle) when
temperature is below T
MIN
- T
HYST
.
Bit 7 (MIN3) = 1,
PWM3 runs at PWM3 minimum duty cycle
below T
MIN
- T
HYST
.
Bit 6 (MIN2) = 0,
PWM2 is off (0% PWM duty cycle) when
temperature is below T
MIN
- T
HYST
.
Bit 6 (MIN2) = 1,
PWM2 runs at PWM2 minimum duty cycle
below T
MIN
- T
HYST
.
Bit 5 (MIN1) = 0,
PWM1 is off (0% PWM duty cycle) when
temperature is below T
MIN
- T
HYST
.
Bit 5 (MIN1) = 1,
PWM1 runs at PWM1 minimum duty cycle
below T
MIN
- T
HYST
.
05381-
052
0%
100%
P
W
M
D
U
T
Y
C
Y
C
L
E
T
MIN
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
PWM
MIN
PWM
MIN
PWM
MIN
100%
PWM
GENERATOR
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
PWM
CONFIG
PWM
CONFIG
PWM
CONFIG
Figure 48. Understanding the T
MIN
Parameter
ADT7475
Rev. 0 | Page 39 of 64
STEP 4: PWM
MIN
FOR EACH PWM (FAN) OUTPUT
PWM
MIN
is the minimum PWM duty cycle at which each fan in
the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above T
MIN
.
For maximum system acoustic benefit, PWM
MIN
should be
as low as possible. Depending on the fan used, the PWM
MIN
setting is usually in the 20% to 33% duty cycle range.
This value can be found through fan validation.
TEMPERATURE
T
MIN
100%
PWM
MIN
0%
P
W
M DUTY
CY
CLE
05381-055
Figure 49. PWM
MIN
Determines Minimum PWM Duty Cycle
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, then the fan
characteristics can be set up differently. As a result, Fan 1
driven by PWM1 can have a different PWM
MIN
value than
that of Fan 2 connected to PWM2. Figure 50 illustrates this as
PWM1
MIN
(front fan) is turned on at a minimum duty cycle of
20%, while PWM2
MIN
(rear fan) turns on at a minimum of 40%
duty cycle. Note: Both fans turn on at exactly the same
temperature, defined by T
MIN
.
TEMPERATURE
T
MIN
100%
PWM1
MIN
0%
P
W
M DUTY
CY
CLE
PW
M1
PW
M2
PWM2
MIN
05381-056
Figure 50. Operating Two Different Fans from a Single Temperature Channel
Programming the PWM
MIN
Registers
The PWM
MIN
registers are 8-bit registers that allow the
minimum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWM
MIN
register is
given by
Value (decimal) = PWM
MIN
/0.39
Example 1:
For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2:
For a minimum PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal)l or 54 (hex)
PWM
MIN
Registers
Reg. 0x64, PWM1 Minimum Duty Cycle = 0x80 (50% default)
Reg. 0x65 PWM2 Minimum Duty Cycle = 0x80 (50% default)
Reg. 0x66, PWM3 Minimum Duty Cycle = 0x80 (50% default)
Note on Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan speed in
RPM. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %RPM generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in RPM approximates to
10
%
=
cycle
duty
PWM
fanspeed
STEP 5: PWM
MAX
FOR PWM (FAN) OUTPUTS
PWM
MAX
is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For maxi-
mum system acoustic benefit, PWM
MAX
should be as low as
possible, but should be capable of maintaining the processor
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to
100% for fail-safe cooling.
There is a PWM
MAX
limit for each fan channel. The default
value of this register is 0xFF and has no effect unless it is
programmed.
ADT7475
Rev. 0 | Page 40 of 64
TEMPERATURE
T
MIN
100%
PWM
MIN
0%
P
W
M DUTY
CY
CLE
PWM
MAX
05381-057
Figure 51. PWM
MAX
Determines Maximum PWM Duty Cycle below the THERM
Temperature Limit
Programming the PWM
MAX
Registers
The PWM
MAX
registers are 8-bit registers that allow the
maximum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the maximum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWM
MAX
register is
given by
Value (decimal) = PWM
MAX
/0.39
Example 1:
For a maximum PWM duty cycle of 50%,
Value (decimal) 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2:
For a minimum PWM duty cycle of 75%,
Value (decimal) = 75/0.39 = 85 (decimal)
Value = 192 (decimal) or C0 (hex)
PWM
MAX
Registers
Reg. 0x38, PWM1 Maximum Duty Cycle = 0xFF
(100% default)
Reg. 0x39, PWM2 Maximum Duty Cycle = 0xFF
(100% default)
Reg. 0x3A, PWM3 Maximum Duty Cycle = 0xFF
(100% default)
STEP 6: T
RANGE
FOR TEMPERATURE CHANNELS
T
RANGE
is the range of temperature over which automatic fan
control occurs once the programmed T
MIN
temperature has
been exceeded. T
RANGE
is the temperature range between PWM
MIN
and 100% PWM where the fan speed changes linearly. Otherwise
stated, it is the line drawn between the Tmin/PWMmin and
the (T
MIN
+ T
RANGE
)/PWM 100% intersection points.
TEMPERATURE
T
MIN
100%
PWM
MIN
0%
P
W
M DUTY
CY
CLE
T
RANGE
05381-058
Figure 52. T
RANGE
Parameter Affects Cooling Slope
The T
RANGE
is determined by the following procedure:
1.
Determine the maximum operating temperature for that
channel (for example, 70C).
2.
Determine experimentally the fan speed (PWM duty cycle
value) that does not exceed the temperature at the worst-
case operating points. (For example, 70C is reached when
the fans are running at 50% PWM duty cycle.)
3.
Determine the slope of the required control loop to meet
these requirements.
4.
Using the ADT7475 evaluation software, you can
graphically program and visualize this functionality.
Ask your local Analog Devices representative for details.
As PWM
MIN
is changed, the automatic fan control slope also
changes.
T
MIN
100%
33%
0%
P
W
M DUTY
CY
CLE
50%
30
C
05381-059
Figure 53. Adjusting PWM
MIN
Changes the Automatic Fan Control Slope
ADT7475
Rev. 0 | Page 41 of 64
As T
RANGE
is changed, the slope also changes. As T
RANGE
gets smaller, the fans will reach 100% speed with a smaller
temperature change.
05381-060
T
MIN
T
MINHYST
100%
0%
P
W
M DUTY
CY
CLE
30
C
40
C
10%
45
C
54
C
Figure 54. Increasing T
RANGE
Changes the AFC Slope
05381-061
100%
MAX
PWM
0%
P
W
M DUTY
CY
CLE
T
RANGE
10%
T
MINHYST
Figure 55. Changing PWM Max Does Not Change the AFC Slope
Selecting T
RANGE
The T
RANGE
value can be selected for each temperature channel:
Remote 1, local, and Remote 2 temperature. Bits <7:4> (T
RANGE
)
of Registers 0x5F to 0x61 define the T
RANGE
value for each
temperature channel.
Table 13. Selecting a T
RANGE
Value
Bits <7:4>
1
T
RANGE
(C)
0000 2
0001 2.5
0010 3.33
0011 4
0100 5
0101 6.67
0110 8
0111 10
1000 13.33
1001 16
1010 20
1011 26.67
1100 32
(default)
1101 40
1110 53.33
1111 80
1
Register 0x5F configures Remote 1 T
RANGE
; Register 0x60 configures Local
T
RANGE
; Register 0x61 configures Remote 2 T
RANGE
.
Actual Changes in PWM Output (Advanced
Acoustics Settings)
While the automatic fan control algorithm describes the general
response of the PWM output, the enhanced acoustics registers
(0x62 and 0x63) can be used to set/clamp the maximum rate of
change of PWM output for a given temperature zone. This means
if T
RANGE
is programmed with a steep AFC slope, a relatively small
change in temperature can cause a large change in PWM output
and an audible change in fan speed, which may be noticeable/
annoying to end users. Decreasing the PWM output's maximum
rate of change, by programming the smoothing on the appropri-
ate temperature channels (Registers 0x62 and 0x63), will, in the
event of a temperature spike, clamp the fan speed's maximum rate
of change. Slowly the PWM duty cycle will increase, until the
PWM duty cycle reaches the appropriate duty cycle as defined by
the AFC curve.
Figure 56 shows PWM duty cycle versus temperature for each
T
RANGE
setting. The lower graph shows how each T
RANGE
setting
affects fan speed versus temperature. As can be seen from the
graph, the effect on fan speed is nonlinear.
ADT7475
Rev. 0 | Page 42 of 64
TEMPERATURE ABOVE T
MIN
0
20
40
60
80
100
120
0
FAN SPEED (% OF MAX)
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE T
MIN
(B)
(A)
0
20
40
60
80
100
120
0
PWM DUTY CYCLE (%)
10
20
30
40
50
60
70
80
90
100
05381-062
2C
80C
53.3C
40C
32C
26.6C
20C
16C
13.3C
10C
8C
6.67C
5C
4C
3.33C
2.5C
2C
80C
53.3C
40C
32C
26.6C
20C
16C
13.3C
10C
8C
6.67C
5C
4C
3.33C
2.5C
TEMPERATURE ABOVE T
MIN
0
20
40
60
80
100
120
0
P
W
M DUTY
CY
CLE
(%)
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE T
MIN
(A)
(B)
0
20
40
60
80
100
120
0
FA
N
SPEED
(
%
OF M
A
X)
10
20
30
40
50
60
70
80
90
100
05381-063
2C
80C
53.3C
40C
32C
26.6C
20C
16C
13.3C
10C
8C
6.67C
5C
4C
3.33C
2.5C
2C
80C
53.3C
40C
32C
26.6C
20C
16C
13.3C
10C
8C
6.67C
5C
4C
3.33C
2.5C
Figure 56. T
RANGE
vs. Actual Fan Speed (not PWM drive) Profile
Figure 57. T
RANGE
and % Fan Speed Slopes with PWM
MIN
= 20%
The graphs in Figure 56 assume the fan starts from 0% PWM
duty cycle. Clearly, the minimum PWM duty cycle, PWM
MIN
,
needs to be factored in to see how the loop actually performs
in the system. Figure 57 shows how T
RANGE
is affected when
the PWM
MIN
value is set to 20%. It can be seen that the fan
actually runs at about 45% fan speed when the temperature
exceeds T
MIN
.
Example: Determining T
RANGE
for Each Temperature
Channel
The following example shows how the different T
MIN
and T
RANGE
settings can be applied to three different thermal zones. In this
example, the following T
RANGE
values apply:
T
RANGE
= 80C for ambient temperature
T
RANGE
= 53.33C for CPU temperature
T
RANGE
= 40C for VRM temperature
This example uses the mux configuration described in Step 2,
with the ADT7475 connected as shown in Figure 47. Both CPU
temperature and VRM temperature drive the CPU fan con-
nected to PWM1. Ambient temperature drives the front chassis
fan and rear chassis fan connected to PWM2 and PWM3. The
front chassis fan is configured to run at PWM
MIN
= 20%. The
rear chassis fan is configured to run at PWM
MIN
= 30%. The
CPU fan is configured to run at PWM
MIN
= 10%.
Note: The control range for 4-wire fans is much wider than that
of 3-wire fans. In many cases, 4-wire fans can start with a PWM
drive of as little as 20% or less. In extreme cases some 3-wire
fans will not run unless a PWM drive of 60% or more is applied.
ADT7475
Rev. 0 | Page 43 of 64
TEMPERATURE ABOVE T
MIN
0
10
20
30
40
100
50
60
70
80
90
0
P
W
M DUTY
CY
CLE
(%)
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE T
MIN
0
FA
N
SPEED
(
%
M
A
X R
P
M
)
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
100
50
60
70
80
90
05381-064
VRM TEMPERATURE
AMBIENT TEMPERATURE
CPU TEMPERATURE
VRM TEMPERATURE
CPU TEMPERATURE
AMBIENT TEMPERATURE
Figure 58. T
RANGE
and % Fan Speed Slopes for VRM, Ambient, and
CPU Temperature Channels
STEP 7: T
THERM
FOR TEMPERATURE CHANNELS
T
THERM
is the absolute maximum temperature allowed on a
temperature channel. Above this temperature, a component
such as the CPU or VRM might be operating beyond its safe
operating limit. When the temperature measured exceeds
T
THERM
all fans are driven at 100% PWM duty cycle (full speed)
to provide critical system cooling.
The fans remain running at 100% until the temperature drops
below T
THERM
minus hysteresis, where hysteresis is the number
programmed into the Hysteresis Registers 0x6D and 0x6E.
The default hysteresis value is 4C.
The T
THERM
limit should be considered the maximum worst-case
operating temperature of the system. Because exceeding any
T
THERM
limit runs all fans at 100%, it has very negative acoustic
effects. Ultimately, this limit should be set up as a fail-safe, and
one should ensure that it is not exceeded under normal system
operating conditions.
Note: T
THERM
limits are nonmaskable and affect the fan speed no
matter how automatic fan control settings are configured. This
allows some flexibility, because a T
RANGE
value can be selected
based on its slope, while a hard limit (such as 70C) can be
programmed as T
MAX
(the temperature at which the fan reaches
full speed) by setting T
THERM
to that limit (for example, 70C).
THERM Registers
Reg. 0x6A, Remote 1 THERM limit = 0x64 (100C default)
Reg. 0x6B, Local THERM limit = 0x64 (100C default)
Reg. 0x6C, Remote 2 THERM limit = 0x64 (100C default)
THERM Hysteresis
THERM hysteresis on a particular channel is configured via the
hysteresis settings below (0x6D and 0x6E). For example, setting
hysteresis on the remote 1 channel also sets the hysteresis on
remote 1 THERM.
Hysteresis Registers
Reg. 0x6D, Remote 1, Local Hysteresis Register
<7:4>,
Remote 1 Temperature hysteresis (4C default).
<3:0>,
Local Temperature hysteresis (4C default).
Reg. 0x6E, Remote 2 Temperature Hysteresis Register
<7:4>,
Remote 2 Temperature hysteresis (4C default).
Because each hysteresis setting is four bits, hysteresis values are
programmable from 1C to 15C. It is not recommended that
hysteresis values ever be programmed to 0C, because this dis-
ables hysteresis. In effect, this causes the fans to cycle (during a
THERM event) between normal speed and 100% speed, or,
while operating close to T
MIN
, between normal speed and off,
creating unsettling acoustic noise.
ADT7475
Rev. 0 | Page 44 of 64
05381-
065
T
MIN
P
W
M
D
U
T
Y
C
Y
C
L
E
0%
100%
T
THERM
T
RANGE
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
PWM
MIN
PWM
GENERATOR
PWM
MIN
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
MIN
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
PWM
CONFIG
PWM
CONFIG
PWM
CONFIG
Figure 59. How T
THERM
Relates to Automatic Fan Control
STEP 8: T
HYST
FOR TEMPERATURE CHANNELS
T
HYST
is the amount of extra cooling a fan provides after the
temperature measured has dropped back below T
MIN
before the
fan turns off. The premise for temperature hysteresis (T
HYST
) is
that, without it, the fan would merely chatter, or cycle on and
off regularly, whenever the temperature is hovering at about the
T
MIN
setting.
The T
HYST
value chosen determines the amount of time needed
for the system to cool down or heat up as the fan is turning on
and off. Values of hysteresis are programmable in the range 1C
to 15C. Larger values of T
HYST
prevent the fans from chattering
on and off. The T
HYST
default value is set at 4C.
The T
HYST
setting applies not only to the temperature hysteresis
for fan on/off, but the same setting is used for the T
THERM
hys-
teresis value, described in Step 6. Therefore, programming
Registers 0x6D and 0x6E sets the hysteresis for both fan
on/off and the THERM function.
In some applications, it is required that fans not turn off below
T
MIN
, but remain running at PWM
MIN
. Bits <7:5> of Enhanced
Acoustics Register 1 (Reg. 0x62) allow the fans to be turned off
or to be kept spinning below T
MIN
. If the fans are always on, the
T
HYST
value has no effect on the fan when the temperature drops
below T
MIN
.
THERM Hysteresis
Any hysteresis programmed via registers 0x6D and 0x6E will
also apply hysteresis on the appropriate THERM channel.
ADT7475
Rev. 0 | Page 45 of 64
05381-
066
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION
100%
0%
T
MIN
T
RANGE
PWM
MIN
PWM
MIN
PWM
MIN
100%
T
MIN
P
W
M
D
U
T
Y
C
Y
C
L
E
0%
100%
T
RANGE
T
THERM
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
PWM
GENERATOR
PWM
CONFIG
PWM
CONFIG
PWM
CONFIG
Figure 60. The T
HYST
Value Applies to Fan On/Off Hysteresis and THERM Hysteresis
Enhance Acoustics Register 1 (Reg. 0x62)
Bit 7 (MIN3) = 0,
PWM3 is off (0% PWM duty cycle) when
temperature is below T
MIN
- T
HYST
.
Bit 7 (MIN3) = 1,
PWM3 runs at PWM3 minimum duty cycle
below T
MIN
- T
HYST
.
Bit 6 (MIN2) = 0,
PWM2 is off (0% PWM duty cycle) when
temperature is below T
MIN
- T
HYST
.
Bit 6 (MIN2) = 1,
PWM2 runs at PWM2 minimum duty cycle
below T
MIN
- T
HYST
.
Bit 5 (MIN1) = 0,
PWM1 is off (0% PWM duty cycle) when
temperature is below T
MIN
- T
HYST
.
Bit 5 (MIN1) = 1,
PWM1 runs at PWM1 minimum duty cycle
below T
MIN
- T
HYST
.
Configuration Register 6 (Reg. 0x10)
<0> SLOW,
1 slows the ramp rate for PWM changes associated
with the Remote 1 temperature channel by 4. Configuration
Register 6(Reg. 0x10)
<1> SLOW,
1 slows the ramp rate for PWM changes associated
with the Local temperature channel by 4.
Configuration Register 6(Reg. 0x10)
<2> SLOW,
1 slows the ramp rate for PWM changes associated
with the Remote 2 temperature channel by 4.
Configuration Register 6 (Reg. 0x10)
<7> ExtraSlow,
1 slows the ramp rate for all fans by a factor
of 39.2%.
The following sections list the ramp-up times when the SLOW
bit is set for each temperature monitoring channel.
Enhanced Acoustics Register 1 (Reg. 0x62)
<2:0> ACOU,
selects the ramp rate for PWM outputs associated
with the Remote Temp 1 input.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
ADT7475
Rev. 0 | Page 46 of 64
Enhance Acoustics Register 2 (Reg. 0x63)
<2:0> ACOU3,
selects the ramp rate for PWM outputs
associated with the Local temperature channel.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
<6:4> ACOU2,
selects the ramp rate for PWM outputs
associated with the Remote Temperature 2 input.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
When Bit 7 of configuration register 6 (0x10) =1, then the above
ramp rates change to the values below.
000=52.2 sec
001=26.1 sec
010=17.4 sec
011=10.4 sec
100=6.5 sec
101=4.4 sec
110=2.2 sec
111=1.1 sec
Setting the appropriate slow bit <2:0> of configuration register 6
(0x10) will slow the ramp rate further by a factor of 4.
ADT7475
Rev. 0 | Page 47 of 64
REGISTER TABLES
Table 14. ADT7475 Registers
Address R/W Description
Bit
7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lockable
0x10 R/W
Configuration
6
ExtraSlow VccpLow RES
RES
THERM
in
Manual
SLOW
Remote 2
SLOW
Local
SLOW
Remote 1
0x00
0x11 R
Configuration
7
RES RES RES
RES
RES RES RES
DisTHERMHys
0x00
0x21 R V
CCP
Reading
9
8
7
6
5
4
3
2
0x00
0x22 R V
CC
Reading
9
8
7
6
5
4
3
2
0x00
0x25 R Remote
1
Temperature
9 8 7
6
5 4 3
2
0x80
0x26 R Local
Temperature
9 8 7
6
5 4 3
2
0x80
0x27 R Remote
2
Temperature
9 8 7
6
5 4 3
2
0x80
0x28 R TACH
1
Low
Byte
7 6 5
4
3 2 1
0
0x00
0x29 R TACH
1
High
Byte
15 14 13
12
11 10 9 8
0x00
0x2A R TACH
2
Low
Byte
7 6 5
4
3 2 1
0
0x00
0x2B R TACH
2
High
Byte
15 14 13
12
11 10 9 8
0x00
0x2C R TACH
3
Low
Byte
7 6 5
4
3 2 1
0
0x00
0x2D R TACH
3
High
Byte
15 14 13
12
11 10 9 8
0x00
0x2E R TACH
4
Low
Byte
7 6 5
4
3 2 1
0
0x00
0x2F R TACH
4
High
Byte
15 14 13
12
11 10 9 8
0x00
0x30 R/W
PWM1
Current
Duty Cycle
7 6 5
4
3 2 1
0
0xFF
0x31 R/W
PWM2
Current
Duty Cycle
7 6 5
4
3 2 1
0
0xFF
0x32 R/W
PWM3
Current
Duty Cycle
7 6 5
4
3 2 1
0
0xFF
0x38
R/W
Max PWM 1
Duty Cycle
7 6 5
4
3 2 1
0
0xFF
0x39
R/W
Max PWM 2
Duty Cycle
7 6 5
4
3 2 1
0
0xFF
0x3A
R/W
Max PWM 3
Duty Cycle
7 6 5
4
3 2 1
0
0xFF
0x3D R Device
ID
Register
7 6 5
4
3 2 1
0
0x75
0x3E R Company
ID
Number
7 6 5
4
3 2 1
0
0x41
0x3F R Revision
Number
VER VER VER
VER
STP STP STP
STP
0x69
0x40 R/W
Configuration
Register 1
RES TODIS
FSPDIS
Vx1
FSPD
RDY LOCK
STRT
0x04
Yes
0x41 R
Interrupt
Status
Register 1
OOL R2T LT R1T
RES V
CC
V
CCP
RES
0x00
0x42 R Interrupt
Status
Register 2
D2 D1 F4P
FAN3
FAN2 FAN1 OVT RES
0x00
0x46 R/W
V
CCP
Low Limit
7
6
5
4
3
2
1
0
0x00
0x47 R/W
V
CCP
High
Limit
7 6 5
4
3 2 1
0
0xFF
0x48 R/W
V
CC
Low Limit
7
6
5
4
3
2
1
0
0x00
ADT7475
Rev. 0 | Page 48 of 64
Address R/W Description
Bit
7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lockable
0x49 R/W
V
CC
High Limit
7
6
5
4
3
2
1
0
0xFF
0x4E R/W
Remote
1
Temp Low
Limit
7 6 5
4
3 2 1
0
0x81
0x4F R/W
Remote
1
Temp High
Limit
7 6 5
4
3 2 1
0
0x7F
0x50 R/W
Local
Temp
Low Limit
7 6 5
4
3 2 1
0
0x81
0x51
R/W
Local Temp
High Limit
7 6 5
4
3 2 1
0
0x7F
0x52 R/W
Remote
2
Temp Low
Limit
7 6 5
4
3 2 1
0
0x81
0x53 R/W
Remote
2
Temp High
Limit
7 6 5
4
3 2 1
0
0x7F
0x54 R/W
TACH1
Minimum Low
Byte
7 6 5
4
3 2 1
0
0xFF
0x55 R/W
TACH1
Minimum
High Byte
15 14 13
12
11 10 9 8
0xFF
0x56 R/W
TACH2
Minimum Low
Byte
7 6 5
4
3 2 1
0
0xFF
0x57 R/W
TACH2
Minimum
High Byte
15 14 13
12
11 10 9 8
0xFF
0x58 R/W
TACH3
Minimum Low
Byte
7 6 5
4
3 2 1
0
0xFF
0x59 R/W
TACH3
Minimum
High Byte
15 14 13
12
11 10 9 8
0xFF
0x5A R/W
TACH4
Minimum Low
Byte
7 6 5
4
3 2 1
0
0xFF
0x5B R/W
TACH4
Minimum
High Byte
15 14 13
12
11 10 9 8
0xFF
0x5C R/W
PWM1
Configuration
Register
BHVR BHVR BHVR
INV RES SPIN SPIN SPIN
0x62 Yes
0x5D R/W
PWM2
Configuration
Register
BHVR BHVR BHVR
INV RES SPIN SPIN SPIN
0x62 Yes
0x5E R/W
PWM3
Configuration
Register
BHVR BHVR BHVR
INV RES SPIN SPIN SPIN
0x62 Yes
0x5F R/W
Remote
1
T
RANGE
/PWM 1
Frequency
RANGE RANGE RANGE
RANGE
HF/LF
FREQ FREQ
FREQ
0xC4 Yes
0x60 R/W
Local
T
RANGE
/PWM 2
Frequency
RANGE RANGE RANGE
RANGE
HF/LF
FREQ FREQ
FREQ
0xC4 Yes
0x61 R/W
Remote
2
T
RANGE
/PWM 3
Frequency
RANGE RANGE RANGE
RANGE
HF/LF
FREQ FREQ
FREQ
0xC4 Yes
0x62 R/W
Enhance
Acoustics
Reg 1
MIN3 MIN2 MIN1
SYNC
EN1 ACOU ACOU
ACOU
0x00 Yes
0x63 R/W
Enhance
Acoustics
Reg 2
EN2 ACOU2
ACOU2
ACOU2
EN3 ACOU3
ACOU3
ACOU3 0x00 Yes
ADT7475
Rev. 0 | Page 49 of 64
Address R/W Description
Bit
7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lockable
0x64 R/W
PWM1
Min
Duty Cycle
7 6 5
4
3 2 1
0
0x80
Yes
0x65 R/W
PWM2
Min
Duty Cycle
7 6 5
4
3 2 1
0
0x80
Yes
0x66 R/W
PWM3
Min
Duty Cycle
7 6 5
4
3 2 1
0
0x80
Yes
0x67 R/W
Remote
1
Temp T
MIN
7 6 5
4
3 2 1
0
0x5A
Yes
0x68 R/W
Local
Temp
T
MIN
7 6 5
4
3 2 1
0
0x5A
Yes
0x69 R/W
Remote
2
Temp T
MIN
7 6 5
4
3 2 1
0
0x5A
Yes
0x6A R/W
Remote
1
THERM Temp
Limit
7 6 5
4
3 2 1
0
0x64
Yes
0x6B R/W
Local THERM
Temp Limit
7 6 5
4
3 2 1
0
0x64
Yes
0x6C R/W
Remote
2
THERM Temp
Limit
7 6 5
4
3 2 1
0
0x64
Yes
0x6D
R/W
Remote 1 and
Local
Temp/T
MIN
Hysteresis
HYSR1 HYSR1 HYSR1
HYSR1
HYSL HYSL HYSL HYSL
0x44 Yes
0x6E R/W
Remote
2
Temp/T
MIN
Hysteresis
HYSR2 HYSR2 HYSR2
HYRS RES
RES
RES RES
0x40 Yes
0x6F R/W
XNOR
Tree
Test Enable
RES RES RES
RES
RES RES RES
XEN
0x00
Yes
0x70 R/W
Remote
1
Temperature
Offset
7 6 5
4
3 2 1
0
0x00
Yes
0x71 R/W
Local
Temperature
Offset
7 6 5
4
3 2 1
0
0x00
Yes
0x72 R/W
Remote
2
Temperature
Offset
7 6 5
4
3 2 1
0
0x00
Yes
0x73 R/W
Configuration
Register 2
SHDN
CONV ATTN AVG RES
RES
RES
RES
0x00 Yes
0x74 R/W
Interrupt
Mask
1 Register
OOL R2T LT RIT RES V
CC
V
CCP
RES 0x00
0x75 R/W
Interrupt
Mask
2 Register
D2 D1 F4P
FAN3
FAN2 FAN1 OVT RES
0x00
0x76 R/W
Extended
Resolution 1
RES RES V
CC
V
CC
V
CCP
V
CCP
RES RES
0x00
0x77 R/W
Extended
Resolution 2
TDM2 TDM2 LTMP LTMP
TDM1 TDM1 RES RES
0x00
0x78 R/W
Configuration
Register 3
DC4 DC3 DC2
DC1
FAST
BOOST
THERM
ALERT
Enable
0x00 Yes
0x79 R THERM Timer
Status
Register
TMR TMR TMR
TMR
TMR TMR TMR
ASRT/TMRO
0x00
0x7A R/W
THERM Timer
Limit Register
LIMT LIMT LIMT
LIMT
LIMT LIMT LIMT
LIMT
0x00
0x7B R/W
TACH
Pulses
per
Revolution
FAN4 FAN4 FAN3
FAN3 FAN2 FAN2 FAN1 FAN1
0x55
ADT7475
Rev. 0 | Page 50 of 64
Address R/W Description
Bit
7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lockable
0x7C R/W
Configuration
Register 5
R2
THERM
O/P Only
Local
THERM
O/P Only
R1
THERM
O/P
Only
RES GPIOP
GPIOD
Temp
Offset
TWOS
COMPL
0x01 Yes
0x7D R/W
Configuration
Register 4
RES RES BpAtt
V
CCP
RES Max/Full
on
THERM
THERM
Disable
Pin 9
Func
Pin 9 Func
0x00
Yes
0x7E
R
Test Register 1
DO NOT WRITE TO THESE REGISTERS
0x00
Yes
0x7F
R
Test Register 2
DO NOT WRITE TO THESE REGISTERS
0x00
Yes
Table 15. Register 0x11--Configuration Register 7 (Power-On Default = 0x00)
Bit Name
R/W
Description
<0>
DisTHERMHys
Read/write
Setting this bit to 1 disables
THERM
hysteresis.
<7:1>
Reserved
N/A
Reserved. Do not write to these bits.
Table 16. Register 0x10--Configuration Register 6 (Power-On Default = 0x00)
1, 2
Bit Name
R/W
Description
<0>
SlowFan Remote 1
Read/write
When this bit is set, Fan 1 smoothing times are multiplied 4 for Remote 1
Temperature channel (as defined in Register 0x62).
<1>
SlowFan Local
Read/write
When this bit is set, Fan 2 smoothing times are multiplied 4 for Local Temperature
channel (as defined in Register 0x63).
<2>
SlowFan Remote 3
Read/write
When this bit is set, Fan 3 smoothing times are multiplied 4 for Remote 2
Temperature channel (as defined in Register 0x63).
<3>
THERM in Manual
Read/write
When this bit is set,
THERM
is enabled in manual mode.
1
<5:4>
Reserved
N/A
Reserved. Do not write to these bits.
<6> V
CCP
Low Read/write
V
CCP
LO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage
(V
CCP
) drops below its V
CCP
low limit value (Reg. 0x46), the following occurs:
Status Bit 1 in Status Register 1 is set.
SMBALERT is generated, if enabled.
PROCHOT monitoring is disabled.
Everything is re-enabled once V
CCP
increases above the V
CCP
low limit.
When V
CCP
increases above the low limit:
PROCHOT monitoring is enabled.
Fans return to their programmed state after a spin-up cycle.
<7>
ExtraSlow
Read/write
When this bit is set, all fan smoothing times are increased by a further 39.2%.
1
A THERM event will always override any fan setting (even when fans are disabled).
2
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 17. Register 0x11--Configuration Register 7 (Power-On Default = 0x00)
1
Bit Name
R/W
Description
<0>
DisTHERMHys
Read/write
Setting this bit to 1 disables
THERM
hysteresis.
<7:1>
Reserved
N/A
Reserved. Do not write to these bits
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 18. Voltage Reading Registers (Power-On Default = 0x00)
1, 2
Register Address
R/W
Description
0x21
Read-only
Reflects the voltage measurement
1
at the V
CCP
input on Pin 14 (8 MSBs of reading).
0x22
Read-only
Reflects the voltage measurement
2
at the VB
CCB
input on Pin 3 (8 MSBs of reading).
1
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers
are frozen.
2
V
CC
(Pin 3) is the supply voltage for the ADT7475.
ADT7475
Rev. 0 | Page 51 of 64
Table 19. Temperature Reading Registers (Power-On Default = 0x80)
1, 2
Register Address
R/W
Description
0x25
Read-only
Remote 1 temperature reading
3, 4
(8 MSB of reading).
0x26
Read-only
Local temperature reading (8 MSB of reading).
0x27
Read-only
Remote 2 temperature reading (8 MSB of reading).
1
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).
2
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, all associated MSB reading registers get frozen until read. Both the extended resolution registers and the MSB registers are frozen.
3
In twos complement mode, a temperature reading of -128C (0x80) indicates a diode fault (open or short) on that channel.
4
In Offset 64 mode, a temperature reading of -64C (0x00) indicates a diode fault (open or short) on that channel.
Table 20. Fan Tachometer Reading Registers (Power-On Default = 0x00)
1
Register Address
R/W
Description
0x28
Read-only
TACH1 low byte.
0x29
Read-only
TACH1 high byte.
0x2A
Read-only
TACH2 low byte.
0x2B
Read-only
TACH2 high byte.
0x2C
Read-only
TACH3 low byte.
0x2D
Read-only
TACH3 high byte.
0x2E
Read-only
TACH4 low byte.
0x2F
Read-only
TACH4 high byte.
1
These registers count the number of 11.11 s periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately
measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until
read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts
from occurring while the fans are spinning up.
A count of 0xFFFF indicates that a fan is one of the following:
Stalled or blocked (object jamming the fan).
Failed (internal circuitry destroyed).
Not populated. (The ADT7475 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be
set to 0xFFFF.)
Alternate function, for example, TACH4 reconfigured as a THERM pin.
Table 21. Current PWM Duty Cycle Registers (Power-On Default = 0xFF)
1
Register Address
R/W
Description
0x30
Read/write
PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
0x31
Read/write
PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
0x32
Read/write
PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
1
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7475 reports the PWM duty cycles
back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers
report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 22. Maximim PWM Duty Cycle (Power-On Default = 0xFF)
1,
2
Register Address
R/W
2
Description
0x38
Read/write
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
0x39
Read/write
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
0x3A
Read/Write
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
2
These registers set the maximum PWM duty cycle of the PWM output.
ADT7475
Rev. 0 | Page 52 of 64
Table 23. Register 0x40--Configuration Register 1 (Power-On Default = 0x04)
Bit Name R/W
Description
<0> STRT
1, 2
Read/write
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default power-up limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default
settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) has been set.
<1> LOCK
Write once
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-
only and cannot be modified until the ADT7475 is powered down and powered up again. This prevents
rogue programs such as viruses from modifying critical system limit settings. (Lockable.)
<2> RDY
Read-only This bit is set to 1 by the ADT7475 to indicate only that the device is fully powered up and ready to begin
system monitoring.
<3> FSPD
Read/write When set to 1, this bit runs all fans at full speed. Power-on default = 0. This bit does not get locked at
any time.
<4> VxI
Read/write BIOS should set this bit to a 1 when the ADT7475 is configured to measure current from an ADI ADOPT
VRM controller and to measure the CPU's core voltage. This bit allows monitoring software to display CPU
watts usage. (Lockable.)
<5> FSPDIS Read/write Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spin-
up timeout selected.
<6> TODIS Read/write When this bit is set to 1, the SMBus timeout feature is enabled. This allows the ADT7475 to be used with
SMBus controllers that cannot handle SMBus timeouts. (Lockable.)
<7> RES
Reserved.
1
Bit 0 (STRT) of 0x40, Configuration register 1 remains writable after lock bit is set.
2
When monitoring is disabled, PWM outputs will always go to 100% for thermal protection.
Table 24. Register 0x41--Interrupt Status Register 1 (Power-On Default = 0x00)
Bit Name R/W
Description
<1> V
CCP
Read-only
V
CCP
= 1 indicates that the V
CCP
high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
<2> V
CC
Read-only
V
CC
= 1 indicates that the V
CC
high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
<4> RIT
Read-only RIT = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a read
of the status register only if the error condition has subsided.
<5> LT
Read-only LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<6> R2T
Read-only
R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read
of the status register only if the error condition has subsided.
<7> OOL
Read-only OOL = 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR of all
status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage,
temperature, or fan speed readings represented by Status Register 2 are out-of-limit, which saves the need to
read Status Register 2 every interrupt or polling cycle.
ADT7475
Rev. 0 | Page 53 of 64
Table 25. Register 0x42--Interrupt Status Register 2 (Power-On Default = 0x00)
Bit
Name R/W
Description
<1> OVT
Read-only
OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a
read of the status register when the temperature drops below THERM T
HYST
.
<2> FAN1
Read-only
FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the
PWM1 output is off.
<3> FAN2
Read-only
FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the
PWM2 output is off.
<4> FAN3
Read-only
FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the
PWM3 output is off.
<5> F4P
Read-only
F4P = 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the
PWM3 output is off.
Read/write
When Pin 9 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO.
Read-only
If Pin 9 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM
assertion time exceeds the limit programmed in the THERM limit register (Reg. 0x7A).
<6>
D1
Read-only
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
<7> D2
Read-only
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 26. Voltage Limit Registers
1
Register Address
R/W
Description
2
Power-On Default
0x46
Read/write
V
CCP
low limit.
0x00
0x47
Read/write
V
CCP
high limit.
0xFF
0x48
Read/write
V
CC
low limit.
0x00
0x49
Read/write
V
CC
high limit.
0xFF
1
Setting the Configuration Register 1 lock bit has no effect on these registers.
2
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit ( comparison).
Table 27. Temperature Limit Registers
1
Register Address
R/W
Description
2
Power-On Default
0x4E
Read/write
Remote 1 temperature low limit.
0x81
0x4F
Read/write
Remote 1 temperature high limit.
0x7F
0x50
Read/write
Local temperature low limit.
0x81
0x51
Read/write
Local temperature high limit.
0x7F
0x52
Read/write
Remote 2 temperature low limit.
0x81
0x53
Read/write
Remote 2 temperature high limit.
0x7F
1
Exceeding any of these temperature limits by 1C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock
bit has no effect on these registers.
2
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit ( comparison).
Table 28. Fan Tachometer Limit Registers
1
Register Address
R/W
Description
Power-On Default
0x54
Read/write
TACH1 minimum low byte.
0xFF
0x55
Read/write
TACH1 minimum high byte/single channel ADC
channel select.
0xFF
0x56
Read/write
TACH2 minimum low byte.
0xFF
0x57
Read/write
TACH2 minimum high byte.
0xFF
0x58
Read/write
TACH3 minimum low byte.
0xFF
0x59
Read/write
TACH3 minimum high byte.
0xFF
0x5A
Read/write
TACH4 minimum low byte.
0xFF
0x5B
Read/write
TACH4 minimum high byte.
0xFF
1
Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2
to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
ADT7475
Rev. 0 | Page 54 of 64
Table 29. Register 0x55--TACH 1 Minimum High Byte (Power-On Default = 0xFF)
Bits
Name
R/W
Description
<4:0> Reserved Read-only
These bits are reserved when Bit 6 of Config 2 Register (0x73) is set (single channel ADC mode).
Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte.
<7:5> SCADC
Read/write
When Bit 6 of Config 2 Register (0x73) is set (single channel ADC mode), these bits are used to select the
only channel from which the ADC makes measurements. Otherwise, these bits represent Bits <7:5> of
the TACH1 minimum high byte.
Table 30. PWM Configuration Registers
Register Address
R/W
1
Description
Power-On Default
0x5C
Read/write
PWM1 configuration.
0x62
0x5D
Read/write
PWM2
configuration.
0x62
0x5E
Read/write
PWM3
configuration.
0x62
Bit
Name
R/W
Description
<2:0>
SPIN
Read/write
These bits control the startup timeout for PWMx. The PWM output stays high until two
valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the
fan TACH measurement directly after the fan startup timeout period, then the TACH
measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH
minimum high and low bytes contain 0xFFFF or 0x0000, then the status register 2 bit is
not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
<4>
INV
Read/write
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output
for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle
corresponds to a logic low output.
<7:5>
BHVR
Read/write
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (default).
101 = fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = fastest speed calculated by all three temperature channel controls PWMx.
111 = manual mode. PWM duty cycle registers (Reg. 0x30 to Reg. 0x32) become writable.
1
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
ADT7475
Rev. 0 | Page 55 of 64
Table 31. TEMP T
RANGE
/PWM Frequency Registers
Register Address
R/W
1
Description
Power-On Default
0x5F
Read/write
Remote 1 T
RANGE
/PWM1 frequency.
0xC4
0x60
Read/write
Local
temperature
T
RANGE
/PWM2 frequency.
0xC4
0x61
Read/write
Remote
2
T
RANGE
/PWM3 frequency.
0xC4
Bit
Name
R/W
Description
<2:0>
FREQ
Read/write
These bits control the PWMx frequency.
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
<3>
HF/LF
Read/write
HF/LF =1, enables high frequency PWM output for 4-wire fans. Once enabled, 3-wire
fan-specific settings have no effect (this means, pulse stretching).
<7:4>
RANGE
Read/write
These bits determine the PWM duty cycle vs. the temperature slope for automatic fan
control.
0000 = 2C
0001 = 2.5C
0010 = 3.33C
0011 = 4C
0100 = 5C
0101 = 6.67C
0110 = 8C
0111 = 10C
1000 = 13.33C
1001 = 16C
1010 = 20C
1011 = 26.67C
1100 = 32C (default)
1101 = 40C
1110 = 53.33C
1111 = 80C
1
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
ADT7475
Rev. 0 | Page 56 of 64
Table 32. Register 0x62--Enhanced Acoustics Register 1 (Power-On Default = 0x00)
Bit
Name
R/W
1
Description
<2:0> ACOU1 Read/write Assuming that PWMx is associated with the Remote 1 temperature channel, these bits define the
maximum rate of change of the PWMx output for Remote 1 Temperature related changes. Instead of
the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate
determined by these bits. This feature ultimately enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
<3>
EN1
Read/write When this bit is 1, smoothing is enabled on Remote 1 temperature channel.
<4>
SYNC
Read/write SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to
three fans to be driven from PWM3 output and their speeds to be measured.
SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output.
<5>
MIN1
Read/write When the ADT7475 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle)
or at PWM1 minimum duty cycle when the controlling temperature is below its T
MIN
hysteresis value.
0 = 0% duty cycle below T
MIN
hysteresis.
1 = PWM1 minimum duty cycle below T
MIN
hysteresis.
<6>
MIN2
Read/write When the ADT7475 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty
cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its T
MIN
hysteresis
value.
0 = 0% duty cycle below T
MIN
hysteresis.
1 = PWM 2 minimum duty cycle below T
MIN
hysteresis.
<7>
MIN3
Read/write When the ADT7475 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty
cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its T
MIN
hysteresis
value.
0 = 0% duty cycle below T
MIN
hysteresis.
1 = PWM3 minimum duty cycle below T
MIN
hysteresis.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
ADT7475
Rev. 0 | Page 57 of 64
Table 33. Register 0x63--Enhanced Acoustics Register 2 (Power-On Default = 0x00)
Bit
Name
R/W
1
Description
<2:0>
ACOU3
Read/write
Assuming that PWMx is associated with the Local temperature channel, these bits define the maximum
rate of change of the PWMx output for Local Temperature related changes. Instead of the fan speed
jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by
these bits. This feature ultimately y enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
< 3 >
EN3
Read/write
When this bit is 1, smoothing is enabled on the Local temperature channel.
<6:4>
ACOU2
Read/write
Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the
maximum rate of change of the PWMx output for Remote 2 Temperature related changes. Instead of
the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate
determined by these bits. This feature ultimately enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
<7>
EN2
Read/write
When this bit is 1, smoothing is enabled on the Remote 2 temperature channel.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
ADT7475
Rev. 0 | Page 58 of 64
Table 34. PWM Minimum Duty Cycle Registers
Register Address
R/W
1
Description
Power-On Default
0x64
Read/write
PWM1 minimum duty cycle.
0x80 (50% duty cycle)
0x65
Read/write
PWM2 minimum duty cycle.
0x80 (50% duty cycle)
0x66
Read/write
PWM3 minimum duty cycle.
0x80 (50% duty cycle)
Bit
Name
R/W
1
Description
<7:0>
PWM duty cycle
Read/write
These bits define the PWM
MIN
duty cycle for PWMx.
0x00 = 0% duty cycle (fan off ).
0x40 = 25% duty cycle.
0x80 = 50% duty cycle.
0xFF = 100% duty cycle (fan full speed).
1
These registers become read-only when the ADT7475 is in automatic fan control mode.
Table 35. T
MIN
Registers
1
Register Address
R/W
2
Description
Power-On Default
0x67
Read/write
Remote 1 temperature T
MIN
.
0x5A (90C)
0x68
Read/write
Local temperatue T
MIN
.
0x5A (90C)
0x69
Read/write
Remote 2 temperature T
MIN
.
0x5A (90C)
1
These are the T
MIN
registers for each temperature channel. When the temperature measured exceeds T
MIN
, the appropriate fan runs at minimum speed and increases
with temperature according to T
RANGE
.
2
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
Table 36. THERM Limit Registers
1
Register Address
R/W
2
Description
Power-On Default
0x6A
Read/write
Remote 1 THERM limit.
0x64 (100C)
0x6B
Read/write
Local THERM limit.
0x64 (100C)
0x6C
Read/write
Remote 2 THERM limit.
0x64 (100C)
1
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the
system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output remains at 100% until the temperature drops below a THERM Limit - Hysteresis. If the THERM pin is programmed as an output, then
exceeding these limits by 0.25C can cause the THERM pin to assert low as an output.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
Table 37. Temperature/T
MIN
Hysteresis Registers
1
Register Address
R/W
2
Description
Power-On Default
0x6D
Read/write
Remote 1 and local temperature hysteresis.
0x44
<3:0> HYSL
Local temperature hyseresis. 0C to 15C of
hysteresis can be applied to the local temperature
and AFC loops.
<7:4> HYSR1
Remote 1 temperature hyseresis. 0C to 15C of
hysteresis can be applied to the Remote 1
temperature and AFC loops.
0x6E
Read/write
Remote 2 temperature hysteresis.
0x40
<7:4> HYSR2
Local temperature hyseresis. 0C to 15C of
hysteresis can be applied to the local temperature
and AFC loops.
1
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its
T
MIN
value, the fan remains running at PWM
MIN
duty cycle until the temperature = T
MIN
- hysteresis. Up to 15C of hysteresis can be assigned to any temperature
channel. The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the
THERM limit is exceeded and remains at 100% until the temperature drops below THERM - hysteresis. For acoustic reasons, it is recommended that the hysteresis
value not be programmed less than 4C. Setting the hysteresis value lower than 4C causes the fan to switch on and off regularly when the temperature is close to T
MIN
.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
ADT7475
Rev. 0 | Page 59 of 64
Table 38. XNOR Tree Test Enable
Register Address
R/W
1
Description Power-On
Default
0x6F
Read/write
XNOR tree test enable register.
0x00
<0> XEN
If the XEN bit is set to 1, the device enters the XNOR
tree test mode. Clearing the bit removes the device
from the XNOR tree test mode.
<7:1>
Reserved
Unused. Do not write to these bits.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 39. Remote 1 Temperature Offset
Register Address
R/W
1
Description Power-On
Default
0x70
Read/write
Remote 1 temperature offset.
0x00
<7:0> Read/write
Allows a twos complement offset value to be
automatically added to or subtracted from the
Remote 1 temperature reading. This is to
compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.5C.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 40. Local Temperature Offset
Register Address
R/W
1
Description Power-On
Default
0x71
Read/write
Local temperature offset.
0x00
<7:0> Read/write
Allows a twos complement offset value to be
automatically added to or subtracted from the local
temperature reading. LSB value = 0.5C.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 41. Remote 2 Temperature Offset
Register Address
R/W
1
Description Power-On
Default
0x72
Read/write
Remote 2 temperature offset.
0x00
<7:0> Read/write
Allows a twos complement offset value to be
automatically added to or subtracted from the
Remote 2 temperature reading. This is to
compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.5C.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
ADT7475
Rev. 0 | Page 60 of 64
Table 42. Register 0x73--Configuration Register 2 (Power-On Default = 0x00)
Bit
Name
R/W
1
Description
<0:3> RES
Reserved.
4
AVG
Read/write
AVG = 1, averaging on the temperature and voltage measurements is turned off.
This allows measurements on each channel to be made much faster.
5
ATTN
Read/write
ATTN = 1, the ADT7475 removes the attenuators from the V
CCP
input. The V
CCP
input
can be used for other functions such as connecting up external sensors.
6
CONV
Read/write
CONV = 1, the ADT7475 is put into a single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read continuously from one input only, for
example, Remote 1 temperature. The appropriate ADC channel is selected by
writing to bits <7:5> of TACH1 minimum high byte register (0x55).
Bits <7:5> Reg. 0x55
000 Reserved
001 V
CCP
010 V
CC
(3.3 V)
011 Reserved
100 Reserved
101
Remote 1 temperature
110 Local
temperature
111
Remote 2 temperature
7
SHDN
Read/write
SHDN = 1, ADT7475 goes into shutdown mode. All PWM outputs assert low (or
high depending on state of INV bit) to switch off all fans. The PWM current duty
cycle registers read 0x00 to indicate that the fans are not being driven.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 43. Register 0x74--Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)
Bit
Name
R/W
Description
1
V
CCP
Read/write
V
CCP
= 1, masks SMBALERT for out-of-limit conditions on the V
CCP
channel.
2
V
CC
Read/write
V
CC
= 1, masks SMBALERT for out-of-limit conditions on the V
CC
channel.
4
RIT
Read/write
RIT = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
5
LT
Read/write
LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.
6
R2T
Read/write
R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
7
OOL
Read/write
OOL = 1, masks SMBALERT for any out-of-limit condition in Status Register 2.
Table 44. Register 0x75--Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)
Bit
Name
R/W
Description
1
OVT
Read only
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
2
FAN1
Read/write
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
3
FAN2
Read/write
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
4
FAN3
Read/write
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
5.
F4P
Read/write
F4P = 1, masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM input,
this bit masks SMBALERT for a THERM timer event.
6
D1
Read/write
D1 = 1, masks SMBALERT for a diode open or short on a Remote 1 channel.
7 D2 Read/write
D2 = 1, masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 45. Register 0x76--Extended Resolution Register 1
1
Bit
Name
R/W
Description
<3:2> V
CCP
Read-only
V
CCP
LSBs. Holds the 2 LSBs of the 10-bit V
CCP
measurement.
<5:4> V
CC
Read-only
V
CC
LSBs. Holds the 2 LSBs of the 10-bit V
CC
measurement.
1
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
ADT7475
Rev. 0 | Page 61 of 64
Table 46. Register 0x77--Extended Resolution Register 2
1
Bit
Name
R/W
Description
<3:2>
TDM1
Read-only
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.
<5:4>
LTMP
Read-only
Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.
<7:6>
TDM2
Read-only
Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
1
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 47. Register 0x78--Configuration Register 3 (Power-On Default = 0x00)
Bit
Name
R/W
1
Description
<0>
ALERT
Read/write
ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate
out-of-limit error conditions.
<1>
THERM
Read/write
THERM Enable = 1 enables THERM timer monitoring functionality on Pin 9. Also determined by Bits
0 and 1 (PIN9FUNC) of Configuration Register 4. When THERM is asserted, if the fans are running
and the boost bit is set, the fans run at full speed. Alternatively, THERM can be programmed so that
a timer is triggered to time how long THERM has been asserted.
<2>
BOOST
Read/write
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum
programmed duty cycle for fail-safe cooling.
<3>
FAST
Read/write
FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement
rate from once per second to once every 250 ms (4 ).
<4>
DC1
Read/write
DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<5>
DC2
Read/write
DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<6>
DC3
Read/write
DC3 = 1, enables TACH measurements to be continuously made on TACH3. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<7>
DC4
Read/write
DC4 = 1, enables TACH measurements to be continuously made on TACH4. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 48. Register 0x79--THERM Timer Status Register (Power-On Default = 0x00)
Bit
Name
R/W
Description
<7:1> TMR
Read-only
Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time
exceeds 45.52 ms.
<0>
ASRT/
TMR0
Read-only
This bit is set high on the assertion of the THERM input, and is cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading.
This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution
of 22.76 ms.
Table 49. Register 0x7A--THERM Timer Limit Register (Power-On Default = 0x00)
Bit
Name
R/W
Description
<7:0> LIMT
Read/write
Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit
limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be
programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status
Register 2 (Reg. 0x42) is set. If the limit value is 0x00, then an interrupt is generated immediately
on the assertion of the THERM input.
ADT7475
Rev. 0 | Page 62 of 64
Table 50. Register 0x7B--TACH Pulses per Revolution Register (Power-On Default = 0x55)
Bit
Name
R/W
Description
<1:0> FAN1
Read/write
Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses
Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
<3:2> FAN2
Read/write
Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses
Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
<5:4> FAN3
Read/write
Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses
Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
<7:6> FAN4
Read/write
Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses
Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Table 51. Register 0x7C--Configuration Register 5 (Power-On Default = 0x00)
Bit
Name
R/W
1
Description
<0>
2sC
Read/write
Twos complement = 1, sets the temperature range to twos complement temperature range.
Twos complement = 0, changes the temperature range to Offset 64. When this bit is changed, the
ADT7475 interprets all relevant temperature register values as defined by this bit.
<1>
TempOffset
TempOffset = 0, sets offset range to -63C to +64C with 0.5C resolution.
TempOffset = 1, sets offset range to -63C to +127C with 1C resolution.
These settings apply to registers 0x70, 0x71, and 0x72 (remote 1, internal, and Remote 2 temperature
offset registers.
<2> GPIOD
GPIO direction. When GPIO function is enabled, this determines whether the GPIO is an input (0) or an
output (1).
<3> GPIOP
GPIO polarity. When the GPIO function is enabled and is programmed as an output, this bit
determines whether the GPIO is active low (0) or high (1).
<4> RES
Reserved
<5>
R1 THERM
Read/write
R1 THERM = 0 , THERM temperature limit functionality enabled for Remote 1 temperature channel.
THERM can also be disabled on any channel by the following:
In offset 64 mode, writing -64C to the appropriate THERM temperature limit.
In twos complement mode, writing -128C to the appropriate THERM temperature limit.
ADT7475
Rev. 0 | Page 63 of 64
Bit
Name
R/W
1
Description
<6>
Local
THERM
Read/write
Local THERM = 0, THERM temperature limit functionality enabled for local temperature channel.
THERM can also be disabled on any channel by the following:
In Offset 64 mode, writing -64C to the appropriate THERM temperature limit.
In twos complement mode, writing -128C to the appropriate THERM temperature limit.
<7>
R2 THERM
Read/write
R2 THERM = 0, THERM temperature limit functionality enabled for Remote 2 temperature channel.
THERM can also be disabled on any channel by the following:
In offset 64 mode, writing -64C to the appropriate THERM temperature limit.
In twos complement mode, writing -128C to the appropriate THERM temperature limit.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 52. Register 0x7D--Configuration Register 4 (Power-On Default = 0x00)
Bit
Name
R/W
1
Description
<1:0> Pin9FUNC
Read/write
These bits set the functionality of Pin 9:
00 = TACH4 (default)
01 = Bidirectional THERM
10 = SMBALERT
11 = GPIO
<2>
THERM
Disable
Read/write
THERM Disable = 0, THERM overtemperature output is enabled assuming THERM is correctly
configured (registers 0x78, 0x7C, 0x7D).
THERM Disable = 1, THERM overtemperature output is disabled on all channels.
THERM can also be disabled on any channel by the following:
In offset 64 mode, writing -64C to the appropriate THERM temperature limit
In twos complement mode, writing -128C to the appropriate THERM temperature limit
<3>
Max/Full
on THERM
Read/write
Max/Full on THERM = 0. When THERM limit is exceeded, fans will go to full speed.
Max/Full on THERM = 1. When THERM limit is exceeded, fans will go to max speed as defined in
Register 0x38, Register 0x39, and Register 0x3A.
<4:7> RES
Unused.
<5>
BpAttV
CCP
Read/write
Bypass V
CCP
attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.2965 V (0xFF) .
<6:7> RES
Unused.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 53. Register 0x7E--Manufacturer's Test Register 1 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<7:0> Reserved
Read-only
Manufacturer's test register. These bits are reserved for manufacturer's test purposes and should not
be written to under normal operation.
Table 54. Register 0x7F--Manufacturer's Test Register 2 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<7:0> Reserved
Read-only
Manufacturer's test register. These bits are reserved for manufacturer's test purposes and should not
be written to under normal operation.
ADT7475
Rev. 0 | Page 64 of 64
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-137-AB
16
9
8
1
PIN 1
SEATING
PLANE
0.010
0.004
0.012
0.008
0.025
BSC
0.010
0.006
0.050
0.016
8
0
COPLANARITY
0.004
0.065
0.049
0.069
0.053
0.154
BSC
0.236
BSC
0.193
BSC
Figure 61. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADT7475ARQZ
1
40C to +125C
16-Lead QSOP
RQ-16
ADT7475ARQZ-REEL
1
40C to +125C
16-Lead QSOP
RQ-16
ADT7475ARQZ-REEL7
1
40C to +125C
16-Lead QSOP
RQ-16
1
Z = Pb-free part.
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05381-0-7/05(0)
Document Outline
- FEATURES
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
-
-
- SMBALERT Interrupt Behavior
- Handling SMBALERT Interrupts
-
-
-
- Enabling the SMBALERT Interrupt Output
- Assigning THERM Functionality to a Pin
- THERM as an Input
- THERM TIMER
- Generating SMBALERT Interrupts from THERM Timer Events
- Configuring the THERM Behavior
- Configuring the THERM Pin as an Output
- Enabling and Disabling THERM on Individual Channels
- THERM Hysteresis
- THERM Operation in Manual mode
-
-
-
-
-
-
-
-
-
-
-
- STEP 3: TMIN SETTINGS FOR THERMAL CALIBRATION CHANNELS
-
-
-
- STEP 7: TTHERM FOR TEMPERATURE CHANNELS
- THERM Registers
- THERM Hysteresis
-
-
-
-
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