Document Outline
- Overview
- Features
- Table of Contents
- Functional Description
- Transmitter Section
- Receiver Section
- Lock to Reference
- Byte Alignment
- Parallel Output Port
- Loopback Mode Operation
- Powerup Sequence
- Macrocell Reset
- Sleep Mode
- Block Diagrams
- Input/Output Information
- Electrical Specifications
- Timing Characteristics
- Serial Timing
- Receiver Section Timing
- Receiver Port Timing
- Transmitter Section Timing
- Application Information
- Test Modes
- List of Tables
- Table 1. Receiver Circuit Operating Modes*
- Table 2. Definition of Bit Transmission/Reception Order
- Table 3a. I/O Channel Interface
- Table 3b. I/O Control/PLL Interface Connections
- Table 3c. Power Connections
- Table 4. Reference Clock Specifications (REFCLK and REFCLKN)
- Table 5. PLL Specifications
- Table 6. Output Jitter at 1.0 Gbits/s1.25 Gbits/s
- Table 7. Receiver Input Data Rate
- Table 8. Data Lock Characteristics
- Table 9. Power Dissipation*
- Table 10. dc Electrical Specifications
- Table 11. Absolute Maximum Ratings
- Table 12. Serial Output Timing Levels
- Table 13. Serial Input Interface Timing
- Table 14. Receiver Parallel Port Timing
- Table 15. Transmitter Timing at Parallel Interface
- Table 16. External Resistor Value vs. Differential Output Level Viewing
- Table 17. Test Modes
- List of Figures
- Figure 1. Quad Gigabit Ethernet Transceiver Block Diagram
- Figure 2. DNC5X3125 Single-Channel Transceiver Functional Block Diagram
- Figure 3. Serial Interface Timing
- Figure 4. Receiver Section Timing
- Figure 5. Receiver Port Timing
- Figure 6. Parallel Interface Transmit Timing
- Figure 7. Reference Clock Connections with Single-Ended Source
- Figure 8. Typical Termination for a Single-Channel, High-Speed Serial Transmit-and-Receive Port in a 50 WW Backplane Application
- Figure 9. Typical Termination for a Single-Channel, High-Speed Serial Transmit Port Interfacing a 5 V GBIC Transceiver
- Contact Us
Advance Data Sheet
March 2000
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Overview
The DNC5X3125 is a low-cost, low-power transceiver
macrocell. It is used for data transmission over fiber
or coaxial media in conformance with
IEEE*
802.3z
Gigabit Ethernet specification and Fibre Channel
ANSI
X3T11 at 1.0 Gbits/s and 1.25 Gbits/s.
The transmitter section accepts parallel 10-bit
8b/10b encoded data that is latched on the rising
edge of TBC. It also accepts the low-speed, TTL
compatible system clock, REFCLK, and uses this
clock to synthesize the internal high-speed serial bit
clock. The serialized data is then available at the dif-
ferential PECL outputs, terminated in 50
or 75
to
drive either an optical transmitter or coaxial media.
The receive section receives high-speed serial data
at its differential PECL input port. This data is fed to
the digital clock recovery section, which generates a
recovered clock and retimes the data. The retimed
data is deserialized and presented as 10-bit parallel
data on the output port. A divided-down version of
the recovered clock, synchronous with parallel data
bytes, is also available as a TTL compatible output.
The receive section recognizes the comma character
and aligns the comma-containing byte on the word
boundary, when ENCDET = 1.
Features
s
Designed to operate in Ethernet, fibre channel,
FireWire
or backplane applications.
s
Operationally compliant to
IEEE
802.3z Gigabit
Ethernet specification.
s
Operationally compliant to Fibre Channel
ANSI
X3T11. Provides FC-0 services at 1.0 Gbits/s--
1.25 Gbits/s (10-bit encoded data rate).
s
100 MHz--125 MHz differential or single-ended
reference clock.
s
10-bit parallel interface.
s
8b/10b encoded data.
s
High-speed comma character recognition (K28.1,
K28.5, K28.7) for latency-sensitive applications
and alignment to word boundary.
s
Two 50.0 MHz--62.5 MHz receive-byte clocks.
s
Single analog PLL design requires no external
components for the frequency synthesizer.
s
Novel digital data lock in receiver avoids the need
for multiple analog PLLs.
s
Expandable beyond single-channel SERDES.
s
PECL high-speed interface I/O for use with optical
transceiver or coaxial copper media.
s
Requires one external resistor for PECL output ref-
erence level definition.
s
Low-power digital 0.25 m CMOS technology.
s
3.3 V 5% power supply.
s
0 C--70 C ambient temperature.
*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
ANSI
is a registered trademark of American National Standards
Institute.
FireWire
is a registered trademark of Apple Computer, Inc.
2
Table of Contents
Lucent Technologies Inc.
Contents
Page
Table
Page
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Overview .....................................................................1
Features.......................................................................1
Functional Description ................................................3
Transmitter Section.................................................. 3
Receiver Section..................................................... 3
Lock to Reference ....................................................3
Byte Alignment .........................................................4
Parallel Output Port ................................................. 4
Loopback Mode Operation ......................................4
Powerup Sequence .................................................5
Macrocell Reset .......................................................5
Sleep Mode ..............................................................5
Block Diagrams ........................................................6
Input/Output Information .............................................8
Electrical Specifications ..............................................9
Transmitter ...............................................................9
Receiver .................................................................10
Timing Characteristics ..............................................11
Serial Timing ..........................................................11
Receiver Section Timing ........................................12
Receiver Port Timing ..............................................12
Transmitter Section Timing.................................... 13
Application Information ............................................. 14
Test Modes ...............................................................16
Figure
Page
Figure 1. Quad Gigabit Ethernet Transceiver
Block Diagram.............................................. 6
Figure 2. DNC5X3125 Single-Channel Transceiver
Functional Block Diagram ........................... 7
Figure 3. Serial Interface Timing ............................... 11
Figure 4. Receiver Section Timing ............................ 12
Figure 5. Receiver Port Timing ................................ 12
Figure 6. Parallel Interface Transmit Timing ............. 13
Figure 7. Reference Clock Connections with
Single-Ended Source ................................. 14
Figure 8. Typical Termination for a Single-Channel,
High-Speed, Serial Transmit and Receive
Port in a 50
Backplane Application ........ 14
Figure 9. Typical Termination for a Single-Channel,
High-Speed Serial Transmit/Receive Port
Interfacing a 5 V GBIC Transceiver............ 15
Table 1. Receive Circuit Operating Modes .................. 3
Table 2. Definition of Bit Transmission/
Reception Order ............................................ 4
Table 3a. I/O Channel Interface .................................. 8
Table 3b. I/O Control/PLL Interface Connections ....... 8
Table 3c. Power Connections ..................................... 9
Table 4. Reference Clock Specifications (REFCLK
and REFCLKN) ............................................. 9
Table 5. PLL Specifications ........................................ 9
Table 6. Output Jitter at 1.0 Gbits/s--1.25 Gbits/s ..... 9
Table 7. Receive Input Data Rate ............................. 10
Table 8. Data Lock Characteristics ........................... 10
Table 9. Power Dissipation ....................................... 10
Table 10. dc Electrical Specifications ....................... 10
Table 11. Absolute Maximum Ratings ...................... 10
Table 12. Serial Output Timing Levels ...................... 11
Table 13. Serial Input Interface Timing ..................... 11
Table 14. Receiver Parallel Port Timing ................... 12
Table 15. Transmitter Timing at Parallel Interface ..... 13
Table 16. External Resistor Value vs. Differential
Output Level Viewing ................................ 15
Table 17. Test Modes ............................................... 16
3
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Functional Description
The DNC5X3125 transceiver provides for data trans-
mission over fiber or coaxial media at 1.0 Gbits/s to
1.25 Gbits/s. The block diagram of the macrocell used
as a quad-channel transceiver is shown in Figure 1 and
the single-channel macrocell design is shown in
Figure 2. The input/output designations are given in
Table 3.
Transmitter Section
The typical transmit and receive, high-speed I/O inter-
facing for single-channel applications is shown in
Figures 8 and 9.
The transmitter brings in 8b/10b encoded bits in 10-bit
parallel form for up to 1.25 Gbits/s transmission and
converts the data to serial format. The serial nonreturn
to zero (NRZ) bits are then shifted out of the device at a
maximum rate of 1.25 Gbits/s. Internally, the device
uses two parallel shift registers that operate at half rate
(i.e., a maximum of 625 MHz) for reduced power con-
sumption. The two shift registers drive the PECL output
buffer in an interleaved manner to construct the
1.25 Gbit/s output data stream.
The transmit shift register and other circuits are driven
with clocks generated from a 625 MHz internal clock.
This internal clock is sourced from a voltage controlled
oscillator (VCO) that is locked to the external reference
of 100 MHz--125 MHz. The internal transmit phase-
lock loop multiplies the frequency of the input reference
clock by a factor of 5, and controls the transmit jitter
bandwidth with appropriate design of the jitter transfer
function. The transmit phase-lock loop generates multi-
ple clock phases that are all used by each of the four
receiver circuits. The clock phases are derived from the
transmit VCO.
Receiver Section
The receiver circuit extracts clock from and retimes the
serial input data. The data are input to the receiver on
differential PECL buffers. External termination resistors
are supplied by the user in accordance with
ANSI
stan-
dard, X3T11. The serial differential inputs, HDINP and
HDINN, are ac-coupled to the device and internally
biased to the PECL input common-mode range center.
The receiver data-retiming circuit uses a digital timing
recovery loop that compares the phase of the input
data to multiple phases of the on-device VCO in the
transmit section. One of the phases is chosen to retime
the receive data. A digital low-pass filter is used in the
timing recovery loop to reject jitter from the data input.
A novel phase interpolation circuit permits the retiming
clock's phase to be stepped with fine resolution for pre-
cise alignment of the sampling clock within the data
eye. Use of this digital data-locking scheme for each
receiver advantageously avoids the use of multiple
analog phase-lock loops on-device that can potentially
injection lock to one another. Additionally, the digital
data-locking loop maintains precise loop dynamics,
hence the jitter transfer function is process and temper-
ature independent.
Lock to Reference
The receive circuit has two modes of operation, lock to
reference, and lock to data with retiming. When no data
or invalid data is present on the HDINP and HDINN
input nodes, the user can program the device to ignore
the input data by setting LCKREFN equal to logic 0. In
this mode, neither the PECL input buffer nor the RX
parallel data bus toggles. In normal operations, LCK-
REFN is a logic 1 and the receiver attempts to lock to
the incoming data. If the input data is invalid or outside
the nominal frequency range, the receive digital PLL
will simply ramp the phase of the output clock until it
locks to data.
Table 1. Receiver Circuit Operating Modes*
* REFCLK requirements are given in Table 4.
Mode
Lock to Reference
Lock to Receive Data
LCKREFN = 1 (normal operation) Not applicable
Continually attempts to lock to data.
LCKREFN = 0
Lock to clock, output data does not
toggle. Disable PECL input buffer.
Not applicable.
4
4
Lucent Technologies Inc.
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Functional Description
(continued)
Byte Alignment
When ENCDET = 1, the DNC5X3125 recognizes the
comma character and aligns this 10-bit character to the
word boundary, bits RX[0:9].
COMDET = 1 when the parallel output word contains a
byte-aligned comma character. The COMDET flag will
continue to pulse a logic 1 whenever a byte aligned
comma character is at the parallel output port, indepen-
dent of ENCDET. When ENCDET = 0, there are two
possible scenarios depending upon when the comma
character is received:
1. If byte-alignment had been previously achieved
when ENCDET had been a logic 1, the COMDET
flag will continue to pulse a logic 1 whenever a byte-
aligned comma character is at the parallel output
port. If a comma character occurs that is not on the
word boundary, no attempt will be made to align this
comma character, and the COMDET flag will remain
at a logic 0.
2. If byte-alignment had not been previously achieved
when ENCDET had been a logic 1, then the first
(and only the first) comma character received will be
aligned to the word boundary. COMDET will pulse
when the comma character is aligned to the word
boundary.
Parallel Output Port
Timing for the parallel output data and the 50 MHz to
62.5 MHz receive-byte clock is given in Table 14.
Two low data-rate, receive-byte clocks are available as
outputs during use of the parallel output port in 10-bit
mode. RXCLK1 is the receive-byte clock used by the
protocol device to register bytes 0 and 2. RXCLK0 is
the receive-byte clock used by the protocol device to
register bytes 1 and 3, and it is 180 degrees out of
phase with RXCLK1. Both RXCLK1 and RXCLK0 can
be stretched during byte alignment but not truncated or
slivered. The maximum allowable frequency of these
two clocks under all circumstances, excluding start-up,
will not exceed 80 MHz. The start-up time is specified
as 1 ms.
Loopback Mode Operation
A control signal input, EWRAP, selects between two
possible sets of inputs: normal data (HDINP, HDINN) or
internal loopback data. When EWRAP = 1, the serial
output ports, HDOUTP and HDOUTN, remain active.
The serial transmit data prior to the PECL output driver
is directed to the data recovery circuit, where the clock
is recovered and data is resynchronized to the recov-
ered clock. Retimed data and clock then go to the
serial-to-parallel converter.
Table 2. Definition of Bit Transmission/Reception Order
Serial Transmit/Receive Rate
TX[9:0]
RX[9:0]
1.0 Gbits/s to 1.25 Gbits/s
TX[0] bit serially transmitted first at
HDOUTP, HDOUTN
RX[0] bit received first at serial inputs,
HDINP, HDINN
5
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Functional Description
(continued)
Powerup Sequence
An appropriate powerup reset (PUR) standard cell must be placed in the ASIC to hold the transceiver in reset until
full power is supplied to the macrocell. REFCLK must be active at the time the PUR output goes low and must stay
active while powered up, unless in Reset.
When PUR and signals RESET, BYPPLL, and LPWR are all low, the following start-up sequence occurs:
1. 0 s--32 s, the analog PLL is held at minimum frequency to allow dc bias to settle.
2. 32 s--262 s, the analog PLL has locked in and receiver analog circuits start to lock in.
3. 262 s--326 s, the receiver analog circuits are locked; receiver starts to lock onto incoming data.
4. After 358 s, receiver is locked onto incoming data and can be viewed at the parallel output ports. The comma
detect circuit is enabled at this point allowing byte alignment if ENCDET = 1.
If LCKREFN goes low after the 358 s, the receiver will sit idle. When LCKREFN goes high, the receiver will be
locked onto data after 2 s.
Macrocell Reset
The RESET input to the macrocell is an active-high. When activated with a pulse duration of 1 s, the RESET sig-
nal globally resets the macrocell and the following is performed:
1. The single analog PLL is forced to operate at the minimum frequency possible for its VCO. The PLL will not be
locked in this condition.
2. The high-speed serial output HDOUTP is forced to a PECL logic 0, HDOUTN to logic 1.
3. The deserializer clocks are reset, input data at HDINP, HDINN is ignored and the RX[9:0] signals remain in their
previous state.
4. The phase interpolation/selection circuits are deactivated and the selected phase is reset.
5. The receiver digital low-pass filter in the DPLL is reset. Normally, a reset is not necessary for correct operation,
although a reset can aid rapid lock-in of the internal PLL circuitry.
Sleep Mode
The DNC5X3125 has a sleep mode that is activated by enabling LPWR. In this mode, a divided-down version of
the REFCLK is used to refresh the dynamic circuits within the transceiver. The PLL is powered down in this mode
also. LCKREFN can also be activated to reduce the power even further. Note that complete power down for IDDQ
testing is not supported due to the dynamic logic used in the high-speed sections of the transceiver. The lock-in
sequence timing is needed when coming out of sleep mode.
6
Lucent Technologies Inc.
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Functional Description
(continued)
Block Diagrams
Figure 1. Quad Gigabit Ethernet Transceiver Block Diagram
LPWR
RESET
TBC[A:D]
EN
CDET[
A
:
D
]
CO
MD
ET
[A
:D]
EW
RA
P[
A:
D]
LCK
REFN[A:
D
]
OLREF
OLRVS
RXA[9:0]
TXA[9:0]
RXB[9:0]
TXB[9:0]
TEST[5:1]
LDST[A:D]
BYPPLL
RXCLK0[A:D]
RXCLK1[A:D]
RXC[9:0]
TXC[9:0]
RXD[9:0]
TXD[9:0]
TEST CIRCUITS
TRANSCEIVER A
TRANSCEIVER B
ANALOG PLL
TRANSCEIVER C
TRANSCEIVER D
HDINDP
HDINDN
HDOUTDP
HDOUTDN
HDOUTCN
HDOUTCP
HDINCN
HDINCP
REFCLKN
REFCLK
HDOUTBN
HDOUTBP
HDINBN
HDINBP
HDOUTAN
HDOUTAP
HDINAN
HDINAP
2
2
2
2
2
2
2
2
2
5-8808(F)
7
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Functional Description
(continued)
Block Diagrams
(continued)
* These signals brought to I/O pads for SERDES integration.
Synchronous with REFCLKN.
Figure 2. DNC5X3125 Single-Channel Transceiver Functional Block Diagram
DATA IN
LOAD
SERIALIZER
SERIAL DATA
OUT
PECL
HDOUTP*
HDOUTN*
TEST[5:1] / LDST
BYPPLL
RESET
LPWR
PUR
ENPLLO
HDINP*
HDINN*
PECL
GLOBAL
CONTROL
PHASE SELECT/
INTERPOLATION
DESERIALIZER
ANALOG PLL
TX[9:0]
TBC
REFCLK*
REFCLKN*
PLLFB
RX[9:0]
RXCLK0
RXCLK1
DATA-RETIMING, SERIAL-TO-PARALLEL
CONVERSION AND COMMA DETECTION
SERIAL
DATA
IN
LOW-PASS FILTER
DIGITAL
PHASE
DETECTOR
COMDET
EWRAP
5-8809(F)
OLREF* OLRVS*
8
Lucent Technologies Inc.
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Input/Output Information
Table 3a. I/O Channel Interface
Table 3b. I/O Control/PLL Interface Connections
Name
I/O
Level
Description
TX[9:0]
Input
CMOS
Transmit Data [9:0]. Parallel input bits [9:0], one 10-bit, 8b/
10b encoded data byte, clocked-in on the rising edge of TBC.
TX0 is the least significant bit.
RX[9:0]
Output
CMOS
Receive Data [9:0]. Parallel output bits [9:0], one 10-bit data
type, clocked-out on the alternate rising edges of RXCLK0,
RXCLK1. RX0 is the least significant bit.
TBC
Input
TTL/CMOS
Transmit Byte Clock (100 MHz--125 MHz). Synchronous
with REFCLKN.
RXCLK0
Output
CMOS
Receive Byte Clock 0.
RXCLK1
Output
CMOS
Receive Byte Clock 1.
ENCDET
Input
CMOS
Enable Comma Detection.
COMDET
Output
CMOS
Byte-Aligned Comma Detect.
EWRAP
Input
CMOS
Loopback at Serial I/O.
LCKREFN
Input
CMOS
Lock Receiver to Clock.
HDINP, HDINN
Input
PECL
Differential Serial Inputs.
HDOUTP, HDOUTN
Output
PECL
Differential Serial Outputs.
LDST
Input
CMOS
Load TEST[5:1] Inputs.
Name
I/O
Level
Description
OLREF
Input/Output
Analog
PECL Level Set Resistor Terminal 1.
OLRVS
Input/Output
Analog
PECL Level Set Resistor Terminal 2.
LPWR
Input
CMOS
Macrocell Low-Power Mode.
RESET
Input
CMOS
Macrocell Reset (Active-High).
TEST5
Input
CMOS
Global Test Control Input.
TEST4
Input
CMOS
Local Test Control Input.
TEST3
Input
CMOS
Local Test Control Input.
TEST2
Input
CMOS
Local Test Control Input.
TEST1
Input
CMOS
Local Test Control Input.
BYPPLL
Input
CMOS
Test Control--PLL Bypass Mode.
REFCLK, REFCLKN
Input
PECL or TTL/
CMOS
Reference Clock Input (100 MHz--125 MHz).
PUR
Input
CMOS
Powerup Reset.
PLLFB
Output
CMOS
PLL Feedback Clock.
ENPLLO
Output
CMOS
Enable PLL Feedback.
9
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Input/Output Information
(continued)
Table 3c. Power Connections
Electrical Specifications
Transmitter
Table 4. Reference Clock Specifications (REFCLK and REFCLKN)
* Measured at 50% amplitude point.
Table 5. PLL Specifications
Table 6. Output Jitter
at 1.0 Gbits/s--1.25 Gbits/s
Name
Description
V
DD
G
Global Digital Power.
V
DD
R
High-Speed Receive Power.
V
DD
T
High-Speed Transmit Power.
V
DD
P
PLL Power.
V
DD
Power.
V
SS
G
Global Digital Ground.
V
SS
R
High-Speed Receive Ground.
V
SS
T
High-Speed Transmit Ground
V
SS
P
PLL Ground.
V
SS
Ground.
Parameter
Minimum
Maximum
Unit
Frequency Range
100
125
MHz
Frequency Tolerance
100
100
ppm
Duty Cycle*
40
60
%
Rise Time (PECL)
--
0.8
ns
Fall Time (PECL)
--
0.8
ns
Rise Time (TTL/CMOS)
--
1.5
ns
Fall Time (TTL/CMOS)
--
1.5
ns
In-band Jitter 1 Gbits/s--1.25 Gbits/s
--
30
ps p-p
Out-of-Band Jitter
--
50
ps p-p
Parameter
Minimum
Typical
Maximum
Unit
Bandwidth
--
1.5 --
MHz
Jitter Peaking
--
0.5
--
dB
Lock Time
--
--
230
s
Parameter
Minimum
Maximum
Unit
Deterministic
--
0.08
UI p-p
Random
--
0.12
UI p-p
Total
--
0.2
UI p-p
10
Lucent Technologies Inc.
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Electrical Specifications
(continued)
Receiver
Table 7. Receiver Input Data Rate
Table 8. Data Lock Characteristics
*
Data pattern: 111110000 . . .
Data pattern: 101010 . . .
Table 9. Power Dissipation*
* Depending on application (PCB layout, etc.)
Table 10. dc Electrical Specifications
Table 11. Absolute Maximum Ratings
Parameter
Minimum
Maximum
Unit
Data Rate
1.0
1.25
Gbits/s
Frequency Tolerance with REFCLK
100
100
ppm
Parameter
Minimum
Typical
Maximum
Unit
Bandwidth 0.3
*
--
1
MHz
Jitter Peaking
--
0.5
--
dB
Lock time*
--
--
2
s
Parameter
Minimum
Maximum
Unit
Power --
750
mW
Sleep Mode
--
TBD
mW
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Unit
Supply Voltage
V
DD
,V
DD
A
--
3.135
3.3
3.465
V
Diff. PECL Output
--
Load, as in Figure 8
800
--
--
mV
Diff. PECL Input
--
Source configuration,
as in Figure 8
400
--
1600
mV
Parameter
Minimum Maximum
Unit
Supply Voltage
3.135
3.465
V
TTL High Input Voltage
3.0
3.6
V
PECL Output Current
--
16
mA
Junction Operating Temperature
0
125
C
Storage Temperature
65
150
C
11
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Timing Characteristics
Serial Timing
Table 12. Serial Output Timing Levels
Figure 3. Serial Interface Timing
Table 13. Serial Input Interface Timing
.
Description
Minimum
Typical
Maximum
Unit
Rise Time 20%--80%
0.17
0.2
0.22
ns
Fall Time 80%--20%
0.17
0.2
0.22
ns
Common Mode
V
DD
/2 0.1
V
DD
/2
V
DD
/2 + 0.1
V
Differential Swing
0.8
--
1.6
V p-p
Load (See Table 16.)
50
--
75
Description
Minimum
Maximum
Unit
Rise Time (t
R
)
150
225
ps
Fall Time (t
F
)
150
225
ps
Differential Swing (V
DIFF
)
0.4
1.6
V p-p
Source Impedance
50
75
Data Eye Opening (D
WIN)
320
--
ps
V
DIFF
D
WIN
tF/tR
5-8812(F)
12
Lucent Technologies Inc.
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Timing Characteristics
(continued)
Receiver Section Timing
Figure 4. Receiver Section Timing
Receiver Port Timing
Figure 5. Receiver Port Timing
Table 14. Receiver Parallel Port Timing
* 1.25 Gbits/s.
0.5 pF load.
Symbol
Parameter
Min
Max
Unit
--
RXCLK[1:0] Frequency*
--
62.5
MHz
--
RXCLK[1:0] Low
7.0
9.0
ns
--
RXCLK[1:0] High
7.0
9.0
ns
t
R/F
RXCLK[1:0] (0.4 V to 2.6 V)
0.2
0.5
ns
t
R/F
Data Output (0.4 V to 2.6 V)
0.2
0.5
ns
t
S
Setup Time
3.0
--
ns
t
H
Hold Time
2.0
--
ns
t
SKEW
Skew
--
1.0
ns
RX[9:0]
D7.2
HDNIP
RECOVERED CLOCK
RXCLK1
RXCLK0
COMDET
(INTERNAL)
K28.5
K28.5
D7.2
D0.0
D1.0
RXCLK1
RXCLK0
RX
RX0
RX1
RX2
RX3
RXCLK1 HIGH
RXCLK1 LOW
RXCLK PERIOD
tSKEW
tS
tH
tS
tH
5-8813(F)
5-8814(F)
13
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Timing Characteristics
(continued)
Transmitter Section Timing
* Synchronous with REFCLKN.
Figure 6. Parallel Interface Transmit Timing
Table 15. Transmitter Timing at Parallel Interface
Description
Minimum
Maximum
Unit
Conditions
Data Setup
2
--
ns
With Positive Edge TBC
Data Hold
2
--
ns
With Positive Edge TBC
Rise Time
--
1
ns
--
Fall Time
--
1
ns
--
SYNTHESIZED CLOCK
SERIALIZED DATA
TX[9:0]
TBC*
155
126
375
34A
155
126
375
5-8815(F)
14
Lucent Technologies Inc.
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Application Information
Figure 7. Reference Clock Connections with Single-Ended Source
* External resistor connected between OLREF and OLRVS
.
See Table 16 for external resistor value required for differential output swing.
Damping resistor, maximum = 10
.
Figure 8. Typical Termination for a Single-Channel, High-Speed Serial
Transmit-and-Receive Port in a 50
Backplane Application
CLOCK
SOURCE
REFCLK
REFCLKN
BIAS
BIAS
INTERNAL
CLOCK
DNC5X3125
5-8010(F)(F
HDINP
HDINN
HDOUTP
HDOUTN
0.01
F
10
50
50
100
0.01
F
TRANSMIT
DNC5X3125
RECEIVE
DNC5X3125
RXCLK1
RXCLK0
RX[9:0]
OLREF
OLRVS
TXA[9:0]
TBC
10
0.1
F
*
Z
O
= 50
Z
O
= 50
5-8811(F).c
15
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Application Information
(continued)
* External resistor connected between OLREF and OLRVS
.
See Table 16 for resistor value vs. termination impedance and output swing.
Damping resistor, maximum = 10
.
Figure 9. Typical Termination for a Single-Channel, High-Speed Serial
Transmit Port Interfacing a 5 V GBIC Transceiver
Table 16. External Resistor Value vs. Differential Output Level Viewing
Resistor Value (
)
Termination Impedance (
)
Differential Output Voltage (V)
7.5 K/11.25 K
50/75
0.8
5 K/7.5 K
1.2
4 K/6 K
1.6
TX (+)
TX ()
HDOUTP
HDOUTN
0.01
F
10
50
50
191
0.01
F
TRANSMIT
LU5X31FT
TRANSMIT
GBIC
OLREF
OLVRVS
TXA[9:0]
TBC
10
0.1
F
*
Z
O
= 50
68
191
Z
O
= 50
68
5 V
5 V
5-8811(F)b
16
Lucent Technologies Inc.
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
Test Modes
Note: Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be
modified or eliminated without prior notice.
The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test
input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized
mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular
channel.
For example, if LDST = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once LDST = 0,
the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four channels (A, B,
C, D) via level sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test node used for both
injection of signals as well as for monitoring points within the device.
Table 17. Test Modes
Global
Local Test Configuration
Global
Operation
BYPPLL
Test1
Test2
Test3
Test4
Test5
0
1
1
1
1
X
Normal operation.
0
1
1
1
0
Output
Analog PLL feedback signal viewed at
TEST5.
0
1
1
0
1
X
Transceiver operates normally except
RX[9:0] output is from digital filter, not
the serial data.
0
1
1
0
0
Output
Transceiver operates normally except
RX[9:0] output is from digital filter and
the analog PLL feedback signal is
viewed at TEST5.
0
1
0
1
P
P
Digital filter forced to count. Pulses
applied at TEST4 increments accumu-
lator, pulses at TEST5 decrements
accumulator.
0
1
0
0
P
P
RX[9:0] output is from digital filter, not
the serial data. Digital filter forced to
count. Pulses applied at TEST4 incre-
ments accumulator, pulses at TEST5
decrements accumulator.
0
0
1
1
1
X
Parallel loopback. TX[9:0] = RX[9:0].
RX[9:0] remains active.
0
0
1
1
0
Output
Parallel loopback. TX[9:0] = RX[9:0]
and analog PLL feedback signal viewed
at TEST5. RX[9:0] remains active.
0
0
1
0
1
X
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
0
0
1
0
0
Output
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
Analog PLL feedback signal viewed at
TEST5.
0
0
0
1
1
X
Transmitter is held in reset. BYPPLL
overrides this reset.
17
Lucent Technologies Inc.
Advance Data Sheet
DNC5X3125
March 2000
Gigabit Ethernet Transceiver Macrocell
Test Modes
(continued)
Table 17. Test Modes (continued)
Global
Local Test Configuration
Global
Operation
BYPPLL
Test1
Test2
Test3
Test4
Test5
0
0
0
1
0
Output
Transmitter is held in reset. BYPPLL
overrides this reset. Analog PLL feed-
back signal viewed at TEST5.
0
0
0
0
1
X
Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data.
0
0
0
0
0
Output
Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data. Analog PLL
feedback signal viewed at TEST5.
1
X
X
1
C-0
C-90
Analog PLL is bypassed for low speed
functional test. A low speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5 x REFCLK, but here REF-
CLK is lowered to about 1 MHz.
1
X
X
0
C-0
C-90
Analog PLL is bypassed for low speed
functional test. A low speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5 x REFCLK, but here REF-
CLK is lowered to about 1 MHz.
RX[9:0] output is from digital filter, not
the serial data.
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET:
http://www.lucent.com/micro
E-MAIL:
docmaster@micro.lucent.com
N. AMERICA:
Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
JAPAN:
Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright 2000 Lucent Technologies Inc.
All Rights Reserved
March 2000
DS99-398LAN
DNC5X3125
Advance Data Sheet
Gigabit Ethernet Transceiver Macrocell
March 2000
PDF 
ZIP