Agilent ATF-531P8 High Linearity
Enhancement Mode
[1]
Pseudomorphic HEMT in
2x2 mm
2
LPCC
[3]
Package
Data Sheet
Description
Agilent Technologies's
ATF-531P8 is a single-voltage
high linearity, low noise
E-pHEMT housed in an 8-lead
JEDEC-standard leadless
plastic chip carrier (LPCC
[3]
)
package. The device is ideal as
a high linearity, low-noise,
medium-power amplifier. Its
operating frequency range is
from 50 MHz to 6 GHz.
The thermally efficient package
measures only 2 mm x 2 mm x
0.75 mm. Its backside
metalization provides excellent
thermal dissipation as well as
visual evidence of solder reflow.
The device has a Point MTTF of
over 300 years at a mounting
temperature of +85
C. All
devices are 100% RF & DC tested.
Features
Single voltage operation
High linearity and gain
Low noise figure
Excellent uniformity in product
specifications
Small package size:
2.0 x 2.0 x 0.75 mm
Point MTTF > 300 years
[2]
MSL-1 and lead-free
Tape-and-reel packaging option
available
Specifications
2 GHz; 4V, 135 mA (Typ.)
38 dBm output IP3
0.6 dB noise figure
20 dB gain
10.7 dB LFOM
[4]
24.5 dBm output power at 1 dB gain
compression
Applications
Front-end LNA Q1 and Q2 driver or
pre-driver amplifier for Cellular/
PCS and WCDMA wireless
infrastructure
Driver amplifier for WLAN,
WLL/RLL and MMDS applications
General purpose discrete E-pHEMT
for other high linearity applications
Pin Connections and
Package Marking
Note:
Package marking provides orientation and
identification:
"3P" = Device Code
"x" = Date code indicates the month of
manufacture.
Note:
1. Enhancement mode technology employs a
single positive V
gs
, eliminating the need of
negative gate voltage associated with
conventional depletion mode devices.
2. Refer to reliability datasheet for detailed
MTTF data.
3. Conforms to JEDEC reference outline MO229
for DRP-N
4. Linearity Figure of Merit (LFOM) is essentially
OIP3 divided by DC bias power.
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
3Px
Top View
Pin 8
Source
(Thermal/RF Gnd)
Pin 7 (Drain)
Pin 6
Pin 5
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Bottom View
2
ATF-531P8 Absolute Maximum Ratings
[1]
Absolute
Symbol
Parameter
Units
Maximum
V
DS
DrainSource Voltage
[2]
V
7
V
GS
GateSource Voltage
[2]
V
-5 to 1
V
GD
Gate Drain Voltage
[2]
V
-5 to 1
I
DS
Drain Current
[2]
mA
300
I
GS
Gate Current
mA
20
P
diss
Total Power Dissipation
[3]
W
1
P
in max.
RF Input Power
dBm
+24
T
CH
Channel Temperature
C
150
T
STG
Storage Temperature
C
-65 to 150
ch_b
Thermal Resistance
[4]
C/W
63
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureT
B
is 25
C.
Derate 16 mW/
C for T
B
> 87
C.
4. Thermal resistance measured using
150
C Liquid Crystal Measurement method.
5. Device can safely handle +24 dBm RF Input
Power provided IGS is limited to 20mA. IGS
at P1dB drive level is bias circuit dependent.
Product Consistency Distribution Charts at 2 GHz, 4V, 135 mA
[5,6]
NF (dB)
Figure 2. NF
Nominal = 0.6, USL = 1.0.
0
0.6
0.3
0.9
1.2
180
150
120
90
60
30
0
Cpk = 1.0
Stdev = 0.14
+3 Std
-3 Std
OIP3 (dBm)
Figure 3. OIP3
LSL = 35.5, Nominal = 38.1.
35
38
36
37
40
39
41
160
120
80
40
0
Cpk = 1.2
Stdev = 0.71
+3 Std
-3 Std
GAIN (dB)
Figure 4. Small Signal Gain
LSL = 18.5, Nominal = 20.2 dB, USL = 21.5.
18.5
19.5
20.5
21.5
300
250
200
150
100
50
0
Cpk = 2.0
Stdev = 0.21
+3 Std
-3 Std
Notes:
5. Distribution data sample size is 500 samples taken from 5 different wafers and 3 different lots.
Future wafers allocated to this product may have nominal values anywhere between the upper and
lower limits.
6. Measurements are made on production test board, which represents a trade-off between optimal
OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.
Figure 1. Typical I-V Curves
(Vgs = 0.1 per step).
V
DS
(V)
400
300
200
100
0
0
2
4
5
6
7
3
1
I
DS
(mA)
0.9 V
0.8 V
0.7 V
0.5 V
0.6 V
P1dB (dBm)
Figure 5. P1dB
Nominal = 24.6.
24.2
24.8
24.4
24.6
25
25.2
240
200
160
120
80
40
0
Stdev = 0.12
+3 Std
-3 Std
3
ATF-531P8 Electrical Specifications
T
A
= 25
C, DC bias for RF parameters is Vds = 4V and Ids = 135 mA unless otherwise specified.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Vgs
Operational Gate Voltage
Vds = 4V, Ids = 135 mA
V
--
0.68
--
Vth
Threshold Voltage
Vds = 4V, Ids = 8 mA
V
--
0.3
--
Idss
Saturated Drain Current
Vds = 4V, Vgs = 0V
A
--
3.7
--
Gm
Transconductance
Vds = 4.5V, Gm =
Idss/Vgs;
mmho
--
650
--
?Vgs = Vgs1 - Vgs2
Vgs1 = 0.6V, Vgs2 = 0.55V
Igss
Gate Leakage Current
Vds = 0V, Vgs = -4V
A
-10
-0.34
--
NF
Noise Figure
[1]
f = 2 GHz
dB
--
0.6
1
f = 900 MHz
dB
--
0.6
--
G
Gain
[1]
f = 2 GHz
dB
18.5
20
21.5
f = 900 MHz
dB
--
25
--
OIP3
Output 3
rd
Order
f = 2 GHz
dBm
35.5
38
--
Intercept Point
[1,2]
f = 900 MHz
dBm
--
37
--
P1dB
Output 1dB
f = 2 GHz
dBm
--
24.5
--
Compressed
[1]
f = 900 MHz
dBm
--
23
--
PAE
Power Added Efficiency
f = 2 GHz
%
--
57
--
f = 900 MHz
%
--
45
--
ACLR
Adjacent Channel Leakage
Offset BW = 5 MHz
dBc
--
-68
--
Power Ratio
[1,3]
Offset BW = 10 MHz
dBc
--
-64
--
Notes:
1. Measurements obtained using production test board described in Figure 6.
2. F1 = 2.00 GHz, F2 = 2.01 GHz and Pin = -10 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
Test Model 1
Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
Freq = 2140 MHz
Pin = -5 dBm
Chan Integ Bw = 3.84 MHz
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
_mag = 0.66
_ang = -165
(1.8 dB loss)
Output
Matching Circuit
_mag = 0.09
_ang = 118
(1.1 dB loss)
DUT
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a
trade-off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.
4
Gamma Load and Source at Optimum OIP3 Tuning Conditions
The device's optimum OIP3 measurements were determined using a Maury load pull system at 4V, 135 mA
quiesent bias. The gamma load and source over frequency are shown in the table below:
Figure 7. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in
gate supply. Transmission line tapers, tee intersections, bias lines and parasitic values are not shown.
RF Input
3.3 pF
4.7 pF
RF Output
50 Ohm
.02
110 Ohm
.03
110 Ohm
.03
50 Ohm
.02
DUT
2.2 pF
22 nH
15 Ohm
100 pF
Gate
DC Supply
12 nH
2.2
F
Drain
DC Supply
Freq
Gamma Source
Gamma Load
OIP3
Gain
P1dB
PAE
(GHz)
Mag
Ang
Mag
Ang
(dBm)
(dB)
(dBm)
(%)
0.9
0.616
-37.1
0.249
130.0
40.3
16.5
23.4
43.2
2.0
0.310
34.5
0.285
168.3
41.5
13.4
24.8
51.9
3.9
0.421
167.5
0.437
-161.6
41.5
10.5
24.7
42.8
5.8
0.402
-162.8
0.418
-134.1
41.0
7.9
24.7
36.6
5
ATF-531P8 Typical Performance Curves (at 25
C unless specified otherwise)
Tuned for Optimal OIP3
Note:
Bias current for the above charts are quiescent
conditions. Actual level may increase or
decrease depending on amount of RF drive. The
objective of load pull is to optimize OIP3 and
therefore may trade-off Small Signal Gain, P1dB
and VSWR.
Figure 8. OIP3 vs. I
ds
and V
ds
at 900 MHz.
3V
4V
5V
Ids (mA)
45
40
35
30
25
20
75
180
105
90
135
150
165
120
OIP3 (dBm)
Figure 9. OIP3 vs. I
ds
and V
ds
at 2 GHz.
3V
4V
5V
Ids (mA)
45
40
35
30
25
20
75
180
105
90
135
150
165
120
OIP3 (dBm)
Figure 10. OIP3 vs. I
ds
and V
ds
at 3.9 GHz.
3V
4V
5V
Ids (mA)
45
40
35
30
25
20
75
180
105
90
135
150
165
120
OIP3 (dBm)
Figure 11. Small Signal Gain vs. I
ds
and V
ds
at 900 MHz.
3V
4V
5V
Ids (mA)
17
16
15
14
13
12
11
10
75
180
105
90
135
150
165
120
GAIN (dB)
Figure 12. Small Signal Gain vs. I
ds
and V
ds
at 2 GHz.
3V
4V
5V
Ids (mA)
17
16
15
14
13
12
11
10
75
180
105
90
135
150
165
120
GAIN (dB)
Figure 13. Small Signal Gain vs. I
ds
and V
ds
at 3.9 GHz.
3V
4V
5V
Ids (mA)
12
10
8
6
4
2
0
75
180
105
90
135
150
165
120
GAIN (dB)
Figure 14. P1dB vs. I
dq
and V
ds
at 900 MHz.
3V
4V
5V
Idq (mA)
30
25
20
15
10
75
180
105
90
135
150
165
120
P1dB (dBM)
Figure 15. P1dB vs. I
dq
and V
ds
at 2 GHz.
3V
4V
5V
Idq (mA)
30
25
20
15
10
75
180
105
90
135
150
165
120
P1dB (dBM)
Figure 16. P1dB vs. I
dq
and V
ds
at 3.9 GHz.
3V
4V
5V
Idq (mA)
30
25
20
15
10
75
180
105
90
135
150
165
120
P1dB (dBM)
PDF 
ZIP