December 2002
Copyright Alliance Semiconductor. All rights reserved.
AS7C33128PFS16A
AS7C33128PFS18A
3.3V 128K
16/18 pipeline burst synchronous SRAM
12/2/02, v.1.5
Alliance Semiconductor
P. 1 of 11
Features
Organization: 131,072words 16 or 18 bits
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/4.0/5.0 ns
Fast OE access time: 3.5/4.0/5.0 ns
Fully synchronous register-to-register operation
Flow-through mode
Single-cycle deselect
Asynchronous output enable control
Economical 100-pin TQFP package
Byte write enables
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power in power-down mode
Selection guide
166
133
100
Units
Minimum cycle time
6
7.5
10
ns
Maximum pipelined clock frequency
166
133
100
MHz
Maximum pipelined clock access time
3.5
4
5
ns
Maximum operating current
475
425
325
mA
Maximum standby current
130
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
mA
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
17
15
17
A[16:0]
17
Address
D
Q
CS
CLK
register
128K 16/18
Memory
array
16/18
16/18
DQb
CLK
D
Q
Byte Write
registers
DQa
CLK
D
Q
Byte Write
registers
Enable
CLK
D
Q
register
Enable
CLK
D
Q
delay
register
CE
Output
registers
Input
registers
Power
down
2
CE0
CE1
CE2
BW
b
BW
a
OE
ZZ
OE
FT
CLK
CLK
BWE
GWE
16/18
DQ [a,b]
Pin arrangement
LB
O
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
NC
NC
BWb
BW
a
CE2
V
DD
V
SS
CLK
GW
E
BWE
OE
AD
SC
AD
SP
AD
V
A8
A9
NC
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A16
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
VSS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
V
DD
TQFP 14 20mm
Note: pins 24, 74 are NC for 16.
AS7C33128PFS16A
AS7C33128PFS18A
12/2/02, v.1.5
Alliance Semiconductor
P. 2 of 11
Functional description
The AS7C33128PFS16A and AS7C33128PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072words 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Fast cycle times of 6.0/7.5/10 ns with clock access times (t
CD
) of 3.5/4.0/5.0 ns enable 166, 133, and 100 MHz bus frequencies. Three chip
enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the
processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, is carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high.
Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With
LBO driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled low regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally
to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33128PFS16A and AS7C33128PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 1420 mm TQFP packaging.
Key: X = don't care. L = low. H = high. T = true. F = false. * = valid read. n = a or b.
WE or WEn
= internal write signal.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
Address and control pins
V
IN
= 0V
5
pF
I/O capacitance
C
I/O
I/O pins
V
IN
= V
OUT
= 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
L
X
X
T
H
L
L
T
H
H
X
F*
H
L
H
F*
Burst order
Interleaved burst order
LBO = 1
Linear burst rrder
LBO = 0
Starting address
00
01
10
11
Starting address
00
01
10
11
First increment
01
00
11
10
First increment
01
10
11
00
Second increment
10
11
00
01
Second increment
10
11
00
01
Third increment
11
10
01
00
Third increment
11
00
01
10
12/2/02, v.1.5
Alliance Semiconductor
P. 3 of 11
AS7C33128PFS16A
AS7C33128PFS18A
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
Signal descriptions
Signal
I/O
Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE,
FT
, ZZ,
LBO
are synchronous to this clock.
A0A16
I
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0
is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active high and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe (processor). Asserted low to load a new address or to enter standby
mode.
ADSC
I
SYNC
Address strobe (controller). Asserted low to load a new address or to enter standby
mode.
ADV
I
SYNC
Burst advance. Asserted low to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted low to write all 16/18 bits. When high, BWE and
BW[a,b] control write enable.
BWE
I
SYNC
Byte write enable. Asserted low with GWE = high to enable effect of BW[a,b] inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = high and BWE
= low. If any of BW[a,b] is active with GWE = high and BWE = low the cycle is a
write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in
read mode.
LBO
I
STATIC default =
high
Count mode. When driven high, count sequence follows Intel XOR convention.
When driven low, count sequence follows linear convention. This signal is internally
pulled high.
FT
I
STATIC
Flow-through mode.When low, enables single register flow-through mode. Connect
to V
DD
if unused or for pipelined operation.
ZZ
I
ASYNC
Sleep. Places device in low power mode. Data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
V
DD
, V
DDQ
0.5
+4.6
V
Input voltage relative to GND (input pins)
V
IN
0.5
V
DD
+ 0.5
V
Input voltage relative to GND (I/O pins)
V
IN
0.5
V
DDQ
+ 0.5
V
Power dissipation
P
D
1.8
W
DC output current
I
OUT
50
mA
Storage temperature (plastic)
T
stg
65
+150
C
Temperature under bias
T
bias
65 +135
C
AS7C33128PFS16A
AS7C33128PFS18A
12/2/02, v.1.5
Alliance Semiconductor
P. 4 of 11
Key: X = don't care, L = low, H = high.
1
See "Write enable truth table" on page 2 for more information.
2
Q in flow-through mode
3
For write operation following a READ,
OE
must be high before the input data setup time and held high throughout the input hold time.
Synchronous truth table
CE0
CE1
CE2
ADSP
ADSC
ADV
WEn
1
OE
Address accessed
CLK
Operation
DQ
H
X
X
X
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
L
X
L
X
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
L
X
H
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
X
H
L
X
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
X
H
H
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
H
L
L
X
X
X
L
External
L to H
Begin read
Hi
-
Z
2
L
H
L
L
X
X
X
H
External
L to H
Begin read
Hi
-
Z
L
H
L
H
L
X
F
L
External
L to H
Begin read
Hi
-
Z
2
L
H
L
H
L
X
F
H
External
L to H
Begin read
Hi
-
Z
X
X
X
H
H
L
F
L
Next
L to H
Cont. read
Q
X
X
X
H
H
L
F
H
Next
L to H
Cont. read
Hi
-
Z
X
X
X
H
H
H
F
L
Current
L to H
Suspend read
Q
X
X
X
H
H
H
F
H
Current
L to H
Suspend read
Hi
-
Z
H
X
X
X
H
L
F
L
Next
L to H
Cont. read
Q
H
X
X
X
H
L
F
H
Next
L to H
Cont. read
Hi
-
Z
H
X
X
X
H
H
F
L
Current
L to H
Suspend read
Q
H
X
X
X
H
H
F
H
Current
L to H
Suspend read
Hi
-
Z
L
H
L
H
L
X
T
X
External
L to H
Begin write
D
3
X
X
X
H
H
L
T
X
Next
L to H
Cont. write
D
H
X
X
X
H
L
T
X
Next
L to H
Cont. write
D
X
X
X
H
H
H
T
X
Current
L to H
Suspend write
D
H
X
X
X
H
H
T
X
Current
L to H
Suspend write
D
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
DD
3.135
3.3
3.6
V
V
SS
0.0
0.0
0.0
3.3V I/O supply voltage
V
DDQ
3.135
3.3
3.6
V
V
SSQ
0.0
0.0
0.0
2.5V I/O supply voltage
V
DDQ
2.35
2.5
2.9
V
V
SSQ
0.0
0.0
0.0
Input voltages
1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
Address and
control pins
V
IH
2.0
V
DD
+ 0.3
V
V
IL
0.5
2
2 V
IL
min. = 2.0V for pulse width less than 0.2 t
RC
.
0.8
I/O pins
V
IH
2.0
V
DDQ
+ 0.3
V
V
IL
0.5
2
0.8
Ambient operating temperature
T
A
0
70
C
12/2/02, v.1.5
Alliance Semiconductor
P. 5 of 11
AS7C33128PFS16A
AS7C33128PFS18A
TQFP thermal resistance
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)
1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
JA
46
C/W
Thermal resistance
(junction to top of case)
1
JC
2.8
C/W
1 This parameter is sampled.
DC electrical characteristics
Parameter
Symbol
Test conditions
166
133
100
Unit
Min
Max
Min
Max
Min
Max
Input leakage
current
1
|I
LI
|
V
DD
= Max, V
IN
= GND to
V
DD
2
2
2
A
Output leakage
current
|I
LO
|
OE
V
IH
, V
DD
= Max,
V
OUT
= GND to V
DD
2
2
2
A
Operating
power supply
current
I
CC
2
CE0 = V
IL
, CE1 = V
IH
, CE2
= V
IL
,
f = f
Max
, I
OUT
= 0 mA
475
425
325
mA
Standby power
supply current
I
SB
Deselected, f = f
Max
, ZZ
V
IL
130
100
90
mA
I
SB1
Deselected, f = 0, ZZ
0.2V
all V
IN
0.2V or
V
DD
0.2V
30
30
30
I
SB2
Deselected, f = f
Max
, ZZ
V
DD
0.2V
All V
IN
V
IL
or
V
IH
30
30
30
Output voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 3.465V
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
DDQ
=
3.135V
2.4
2.4
2.4
1 LBO pin has an internal pull-up, and input leakage = 10
a.
2 I
CC
give with no output loading. I
CC
increases with faster cycle times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
Parameter
Symbol
Test conditions
166
133
100
Unit
Min
Max
Min
Max
Min
Max
Output leakage
current
|I
LO
|
OE
V
IH
, V
DD
= Max,
V
OUT
= GND to V
DD
1
1
1
1
1
1
A
Output voltage
V
OL
I
OL
= 2 mA, V
DDQ
= 2.65V
0.7
0.7
0.7
V
V
OH
I
OH
= 2 mA, V
DDQ
= 2.35V
1.7
1.7
1.7
AS7C33128PFS16A
AS7C33128PFS18A
12/2/02, v.1.5
Alliance Semiconductor
P. 6 of 11
Timing characteristics over operating range
Parameter
Sym
166
133
100
Unit Notes
1
Min
Max
Min
Max
Min
Max
Clock frequency
f
Max
166
133
100
MHz
Cycle time (pipelined mode)
t
CYC
6
7.5
10
ns
Cycle time (flow-through mode)
t
CYCF
10
12
12
ns
Clock access time (pipelined mode)
t
CD
3.5
4.0
5.0
ns
Clock access time (flow-through mode)
t
CDF
9
10
12
ns
Output enable low to data valid
t
OE
3.5
4.0
5.0
ns
Clock high to output low Z
t
LZC
0
0
0
ns
2,3,4
Data output invalid from clock high
t
OH
1.5
1.5
1.5
ns
2
Output enable low to output low Z
t
LZOE
0
0
0
ns
2,3,4
Output enable high to output high Z
t
HZOE
3.5
4.0
4.5
ns
2,3,4
Clock high to output high Z
t
HZC
3.5
4.0
5.0
ns
2,3,4
Output enable high to invalid output
t
OHOE
0
0
0
ns
Clock high pulse width
t
CH
2.4
2.5
3.5
ns
5
Clock low pulse width
t
CL
2.2
2.5
3.5
ns
5
Address setup to clock high
t
AS
1.5
1.5
2.0
ns
6
Data setup to clock high
t
DS
1.5
1.5
2.0
ns
6
Write setup to clock high
t
WS
1.5
1.5
2.0
ns
6,7
Chip select setup to clock high
t
CSS
1.5
1.5
2.0
ns
6,8
Address hold from clock high
t
AH
0.5
0.5
0.5
ns
6
Data hold from clock high
t
DH
0.5
0.5
0.5
ns
6
Write hold from clock high
t
WH
0.5
0.5
0.5
ns
6,7
Chip select hold from clock high
t
CSH
0.5
0.5
0.5
ns
6,8
ADV setup to clock high
t
ADVS
1.5
1.5
2.0
ns
6
ADSP setup to clock high
t
ADSPS
1.5
1.5
2.0
ns
6
ADSC setup to clock high
t
ADSCS
1.5
1.5
2.0
ns
6
ADV hold from clock high
t
ADVH
0.5
0.5
0.5
ns
6
ADSP hold from clock high
t
ADSPH
0.5
0.5
0.5
ns
6
ADSC hold from clock high
t
ADSCH
0.5
0.5
0.5
ns
6
1
Refer to "notes" on page 10
12/2/02, v.1.5
Alliance Semiconductor
P. 7 of 11
AS7C33128PFS16A
AS7C33128PFS18A
Key to switching waveforms
Timing waveform of read cycle
Note: = XOR when
LBO
= high/noconnect. = ADD when
LBO
= low.
BW[a:b] is don't care.
Undefined/don't care
Falling input
Rising input
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
D
OUT
t
CSS
t
CSH
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV INSERTS WAIT STATES
Q(A210)
Q(A211)
Q(A3)
Q(A2)
Q(A201)
Q(A301)
Q(A310)
Q(A1)
A2
A1
A3
CE1
(pipelined mode)
D
OUT
Q(A210)
Q(A211)
Q(A3)
Q(A201)
Q(A301)
Q(A310)
Q(A311)
Q(A1)
(flow-through mode)
t
HZC
t
OE
t
LZOE
AS7C33128PFS16A
AS7C33128PFS18A
12/2/02, v.1.5
Alliance Semiconductor
P. 8 of 11
Timing waveform of write cycle
Note: = XOR when
LBO
= high/no connect. = ADD when
LBO
= low.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Data In
t
CSH
t
ADVH
D(A201)
D(A210)
D(A3)
D(A2)
D(A201)
D(A301)
D(A310)
D(A1)
D(A211)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1
A2
A3
t
CH
CE1
BWa,b
12/2/02, v.1.5
Alliance Semiconductor
P. 9 of 11
AS7C33128PFS16A
AS7C33128PFS18A
Timing waveform of read/write cycle
Note: = XOR when
LBO
= high/no connect. = ADD when
LBO
= low.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
D
IN
D
OUT
t
LZC
t
ADVH
t
LZOE
t
OE
t
CD
Q(A1)
Q(A301)
D(A2)
Q(A3)
Q(A310)
Q(A311)
A1
A2
A3
CE1
t
HZOE
(pipeline mode)
D
OUT
Q(A1)
Q(A301)
Q(A310)
(flow-through mode)
t
CDF
Q(A311)
AS7C33128PFS16A
AS7C33128PFS18A
12/2/02, v.1.5
Alliance Semiconductor
P. 10 of 11
AC test conditions
Package dimensions100-pin quad flat pack (TQFP)
Z
0
= 50
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Output load: see Figure B, except for t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O,
= V
DDQ
/2
for 2.5V I/O
Notes
1
For test conditions, see AC Test Conditions, Figures A, B, C.
2
This parameter measured with output load condition in Figure C.
3
This parameter is sampled, but not 100% tested.
4
t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given temperature and voltage.
5
tCH measured as high above VIH, and tCL measured as low below VIL.
6
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
Write refers to
GWE, BWE, and BW[a:b].
8
Chip select refers to
CE0, CE1, and CE2
353
/ 1538
5 pF*
319
/ 1667
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O,
+2.5V for 2.5V I/O
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
0.65 nominal
Hd
15.90
16.10
He
21.90
22.10
L
0.45
0.75
L1
1.00 nominal
0
7
Dimensions in millimeters
A1 A2
L1
L
c
He
E
Hd
D
b
e
12/2/02, v.1.5
Alliance Semiconductor
P. 11 of 11
AS7C33128PFS16A
AS7C33128PFS18A
Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product
names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no
responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change
or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data
sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance
does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of
Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does
not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33 = 3.3V
3.Organization: 128 = 128K
4.Pipelined or flow-through (each device works in both modes)
5.Deselect: S = single cycle deselect
6.Organization: 16 = x16, 18 = x18
7.Production version: A = first production version
8.Clock speed (MHz)
9.Package type: TQ = TQFP
10.Operating temperature: C = commercial (0
C to 70
C), I = industrial (-40
C to 85
C)
Ordering information
Package
Width
166 MHz
133 MHz
100 MHz
TQFP
x16
AS7C33128PFS16A-166TQC
AS7C33128PFS16A-133TQC
AS7C33128PFS16A-100TQC
TQFP
x16
AS7C33128PFS16A-166TQI
AS7C33128PFS16A-133TQI
AS7C33128PFS16A-100TQI
TQFP
x18
AS7C33128PFS18A-166TQC
AS7C33128PFS18A-133TQC
AS7C33128PFS18A-100TQC
TQFP
x18
AS7C33128PFS18A-166TQI
AS7C33128PFS18A-133TQI
AS7C33128PFS18A-100TQI
Part numbering guide
AS7C
33
128
PF
S
16/18
A
XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
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