AT28LV010
1 Megabit
(128K x 8)
Low Voltage
Paged CMOS
E
2
PROM
Features
Single 3.3V
10% Supply
Fast Read Access Time - 200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 128-Bytes
Internal Control Timer
Fast Write Cycle Time
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Operation
Low Power Dissipation
15 mA Active Current
20
A CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 100,000K Cycles
Data Retention: 10 Years
JEDEC Approved Byte-Wide Pinout
Commercial and Industrial Temperature Ranges
Description
The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Program-
mable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words
by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the
device offers access times to 200 ns with power dissipation of just 54 mW. When the
device is deselected, the CMOS standby current is less than 20
A.
(continued)
PDIP
Top View
Pin Name
Function
A0 - A16
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data
Inputs/Outputs
NC
No Connect
DC
Don't Connect
Pin Configurations
TSOP
Top View
PLCC
Top View
0395A
AT28LV010
2-155
Block Diagram
Temperature Under Bias................. -55C to +125C
Storage Temperature...................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
The AT28LV010 is accessed like a Static RAM for the
read or write cycle without the need for external compo-
nents. The device contains a 128-byte page register to al-
low writing of up to 128-bytes simultaneously. During a
write cycle, the address and 1 to 128-bytes of data are
internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle,
the device will automatically write the latched data using
an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a read or write
can begin.
Atmel's 28LV010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. Software data protection is
implemented to guard against inadvertent writes. The de-
vice also includes an extra 128-bytes of E
2
PROM for de-
vice identification or tracking.
Description (Continued)
2-156
AT28LV010
Device Operation
READ: The AT28LV010 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
WRITE: The write operation of the AT28LV010 allows 1 to
128-bytes of data to be written into the device during a
single internal programming period. Each write operation
must be preceded by the software data protection (SDP)
command sequence. This sequence is a series of three
unique write command operations that enable the internal
write circuitry. The command sequence and the data to be
written must conform to the software protected write cycle
timing. Addresses are latched on the falling edge of WE or
CE, whichever occurs last and data is latched on the rising
edge of WE or CE, whichever occurs first. Each succes-
sive byte must be written within 150
s (t
BLC
) of the pre-
vious byte. If the t
BLC
limit is exceeded the AT28LV010 will
cease accepting data and commence the interal program-
ming operation. If more than one data byte is to be written
during a single programming operation, they must reside
on the same page as defined by the state of the A7 - A16
inputs. For each WE high to low transition during the page
write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28LV010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
TOGGLE BIT: In addition to DATA Polling the AT28LV010
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28LV010 in the follow-
ing ways: (a) V
CC
power-on delay - once V
CC
has reached
2.0V (typical) the device will automatically time out 5 ms
(typical) before allowing a write: (b) write inhibit - holding
any one of OE low, CE high or WE high inhibits write cy-
cles; (c) noise filter - pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: The AT28LV010 in-
corporates the industry standard software data protection
(SDP) function. Unlike standard 5-volt only E
2
PROM's,
the AT28LV010 has SDP enabled at all times. Therefore,
all write operations must be preceded by the SDP com-
mand sequence.
The data in the 3-byte command sequence is not written
to the device; the addresses in the command sequence
can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte se-
quence will start the internal timers. No data will be written
to the device. However, for the duration of t
WC
, read op-
erations will effectively be polling operations.
AT28LV010
2-157
Mode
CE
OE
WE
I/O
Read
V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
High Z
Write Inhibit
X
X
V
IH
Write Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
Operating Modes
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
1
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
1
A
I
SB
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
+ 1V
Com.
20
A
Ind.
50
A
I
CC
V
CC
Active Current
f = 5 MHz; I
OUT
= 0 mA; V
CC
= 3.6V
15
mA
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 1.6 mA; V
CC
= 3.0V
.45
V
V
OH
Output High Voltage
I
OH
= -100
A; V
CC
= 3.0V
2.4
V
DC Characteristics
AT28LV010-20
AT28LV010-25
Operating
Temperature (Case)
Com.
0C - 70C
0C - 70C
Ind.
-40C - 85C
-40C - 85C
V
CC
Power Supply
3.3V
5%
3.3V
10%
DC and AC Operating Range
2-158
AT28LV010
AT28LV010-20
AT28LV010-25
Symbol
Parameter
Min
Max
Min
Max
Units
t
ACC
Address to Output Delay
200
250
ns
t
CE
(1)
CE to Output Delay
200
250
ns
t
OE
(2)
OE to Output Delay
0
80
0
100
ns
t
DF
(3, 4)
CE or OE to Output Float
0
55
0
60
ns
t
OH
Output Hold from OE, CE or
Address, whichever occurred
first
0
0
ns
AC Read Characteristics
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first
(C
L
= 5pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
t
R
, t
F
< 5 ns
Input Test Waveforms and
Measurement Level
Output Test Load
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Pin Capacitance (f = 1 MHz, T = 25C)
(1)
Note: 1. This parameter is characterized and is not 100% tested.
AT28LV010
2-159
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