AT28LV64B
64K (8K x 8)
Low Voltage
CMOS
E
2
PROM with
Page Write and
Software Data
Protection
Features
Single 3.3V
10% Supply
3-Volt-Only Read and Write Operation
Software-Protected Programming
Low Power Dissipation
15 mA Active Current
20
A CMOS Standby Current
Fast Read Access Time
-
200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1 to 64-Byte Page Write Operation
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 10,000 Cycles
Data Retention: 10 Years
JEDEC Approved Byte-Wide Pinout
Commercial and Industrial Temperature Ranges
PDIP, SOIC
Top View
Pin Name
Function
A0 - A12
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don't Connect
Pin Configurations
TSOP
Top View
Description
The AT28LV64B is a high-performance electrically erasable programmable read only
memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manu-
factured with Atmel's advanced nonvolatile CMOS technology, the device offers ac-
cess times to 200 ns with power dissipation of just 54 mW. When the device is dese-
lected, the CMOS standby current is less than 20
A.
The AT28LV64B is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
(continued)
Note: PLCC package pins 1 and
17 are DON'T CONNECT.
PLCC
Top View
0299C
AT28LV64B
2-135
Block Diagram
writing of up to 64-bytes simultaneously. During a write cy-
cle, the addresses and 1 to 64-bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA polling of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
Atmel's 28LV64B has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. A software data protection
mechanism guards against inadvertent writes. The device
also includes an extra 64-bytes of E
2
PROM for device
identification or tracking.
Description (Continued)
Temperature Under Bias................. -55C to +125C
Storage Temperature...................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
2-136
AT28LV64B
Device Operation
READ: The AT28LV64B is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their systems.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write has been
started, it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
WC
, a read operation will effectively be a poll-
ing operation.
PAGE WRITE: T h e p a g e w r i t e o p e r a t i o n o f t h e
AT28LV64B allows 1 to 64-bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1
to 63 additional bytes. Each successive byte must be writ-
ten within 100
s (t
BLC
) of the previous byte. If the t
BLC
limit is exceeded, the AT28LV64B will cease accepting
data and commence the internal programming operation.
All bytes during a page write operation must reside on the
same page as defined by the state of the A6 to A12 inputs.
For each WE high to low transition during the page write
operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page
are to be written. The bytes may be loaded in any order
and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnec-
essary cycling of other bytes within the page does not oc-
cur.
DATA POLLING: The AT28LV64B features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
TOGGLE BIT: I n a d d i t i o n t o DATA P o l l i n g , t h e
AT28LV64B provides another method for determining the
end of a write cycle. During the write operation, succes-
sive attempts to read data from the device will result in
I/O6 toggling between one and zero. Once the write has
completed, I/O6 will stop toggling and valid data will be
read. Reading the toggle bit may begin at any time during
the write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28LV64B in the follow-
ing ways: (a) V
CC
power-on delay
-
once V
CC
has reached
1.8V (typical) the device will automatically time out 10 ms
(typical) before allowing a write; (b) write inhibit
holding
any one of OE low, CE high or WE high inhibits write cy-
cles; (c) noise filter
pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software-control-
led data protection feature has been implemented on the
AT28LV64B. Software data protection (SDP) helps pre-
vent inadvertent writes from corrupting the data in the de-
vice. SDP can prevent inadvertent writes during power-up
and power-down as well as any other potential periods of
system instability.
The AT28LV64B can only be written using the software
data protection feature
. A series of three write commands
to specific addresses with specific data must be presented
to the device before writing in the byte or page mode. The
same three write commands must begin each write opera-
tion. All software write commands must obey the page
mode write timing specifications. The data in the 3-byte
command sequence is not written to the device; the ad-
dresses in the command sequence can be utilized just like
any other location in the device.
Any attempt to write to the device without the 3-byte se-
quence will start the internal write timers. No data will be
written to the device; however, for the duration of t
WC
,
read operations will effectively be polling operations.
DEVICE IDENTIFICATION: A n e x t r a 6 4 - b y t e s o f
E
2
PROM memory are available to the user for device
identification. By raising A9 to 12V
0.5V and using ad-
dress locations 7FC0H to 7FFFH, the additional bytes
may be written to or read from in the same manner as the
regular memory array.
AT28LV64B
2-137
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
+ 1V
10
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
10
A
I
SB
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
+ 1V
Com.
20
A
Ind.
50
A
I
CC
V
CC
Active Current
f = 5 MHz; I
OUT
= 0 mA
15
mA
V
IL
Input Low Voltage
0.6
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 1.6 mA
0.45
V
V
OH
Output High Voltage
I
OH
= -100
A
2.0
V
DC Characteristics
AT28LV64B-20
AT28LV64B-25
Operating
Temperature (Case)
Com.
0C - 70C
0C - 70C
Ind.
-40C - 85C
-40C - 85C
V
CC
Power Supply
3.3V
10%
3.3V
10%
DC and AC Operating Range
Mode
CE
OE
WE
I/O
Read
V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
High Z
Write Inhibit
X
X
V
IH
Write Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Chip Erase
V
IL
V
H
(3)
V
IL
High
Z
3. V
H
= 12.0V
0.5V.
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
Operating Modes
2-138
AT28LV64B
AT28LV64B-20
AT28LV64B-25
Symbol
Parameter
Min
Max
Min
Max
Units
t
ACC
Address to Output Delay
200
250
ns
t
CE
(1)
CE to Output Delay
200
250
ns
t
OE
(2)
OE to Output Delay
0
80
0
100
ns
t
DF
(3, 4)
CE or OE to Output Float
0
55
0
60
ns
t
OH
Output Hold from OE, CE or Address,
whichever occurred first
0
0
ns
AC Read Characteristics
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE, whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
Output Test Load
Input Test Waveforms and
Measurement Level
t
R
, t
F
< 20 ns
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Pin Capacitance (f = 1 MHz, T = 25C)
(1)
Note: 1. This parameter is characterized and is not 100% tested.
AT28LV64B
2-139
PDF 
ZIP