Features

Single Voltage Operation

5V Read
5V Reprogramming

Fast Read Access Time - 90 ns

Internal Program Control and Timer

16K bytes Boot Block With Lockout

Fast Erase Cycle Time - 10 seconds

Byte-By-Byte Programming - 10

s/Byte Typical

Hardware Data Protection

DATA Polling For End Of Program Detection

Low Power Dissipation

50 mA Active Current
100

A CMOS Standby Current

Typical 10,000 Write Cycles

Description

The AT49F080 is a 5-volt-only in-system Flash Memory device. Its 8-megabits of
memory is organized as 1,024,576 words by 8-bits. Manufactured with Atmel's
advanced nonvolatile CMOS technology, the device offers access times to 90 ns with
power dissipation of just 275 mW over the commercial temperature range. When the
device is deselected, the CMOS standby current is less than 100

The device contains a user-enabled "boot block" protection feature. Two versions of
the feature are available: the AT49F080 locates the boot block at lowest order
addresses ("bottom boot"); the AT49F080T locates it at highest order addresses ("top
boot").

8-Megabit
(1M x 8)
5-volt Only
Flash
Memory

AT49F080
AT49F080T
AT49F080/080T

0584B-A8/97

Pin Configurations

Pin Name

Function

A0 - A19

Addresses

Chip Enable

Output Enable

Write Enable

RESET

Reset

RDY/BUSY

Ready/Busy Output

I/O0 - I/O7

Data Inputs/Outputs

No Connect

CBGA Top View

I/O1

I/O0

A11

A10

RST

I/O3

I/O2

VCC

GND

A12

A13

A14

I/O4

I/O6

I/O5

A15

A16

I/O7

RY/BY

A17

A18

A19

(continued)

SOIC

RESET

A11

A10

I/O0

I/O1

I/O2

I/O3

GND

VCC

A12

A13

A14

A15

A16

A17

A18

A19

RDY/BUSY

I/O7

I/O6

I/O5

I/O4

VCC

TSOP Top VIew

Type 1

A17

A16

A14

A15

A12

A13

A10

RESET

A11

VCC

I/O2

I/O3

I/O1

I/O0

VCC

I/O4

GND

I/O6

I/O5

RDY/BUSY

I/O7

A19

A18

AT49F080/080T

To allow for simple in-system reprogrammability, the
AT49F080 does not require high input voltages for pro-
gramming. 5-volt-only commands determine the read and
programming operation of the device. Reading data out of
the device is similar to reading from an EPROM. Repro-
gramming the AT49F080 is performed by erasing the entire
8 megabits of memory and then programming on a byte-by-
byte basis. The typical byte programming time is a fast 10

s. The end of a program cycle can be optionally detected

by the DATA polling feature. Once the end of a byte pro-

gram cycle has been detected, a new access for a read or
program can begin. The typical number of program and
erase cycles is in excess of 10,000 cycles

The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.

Block Diagram

Device Operation

READ: The AT49F080 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention.

ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical "1". The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t

. If the boot block lockout feature has

been enabled, the data in the boot sector will not be
erased.

BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical "0") on a

byte-by-byte basis. Please note that a data "0" cannot be
programmed back to a "1"; only erase operations can con-
vert "0"s to "1"s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.

The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t

cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

INPUT/OUTPUT

BUFFERS

DATA LATCH

Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(1008K BYTES)

ADDRESS

INPUTS

GND

DATA INPUTS/OUTPUTS

I/O7 - I/O0

03FFFH

00000H

INPUT/OUTPUT

BUFFERS

DATA LATCH

Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(1008K BYTES)

FC000H

00000H

AT49F080T

AT49F080

DATA INPUTS/OUTPUTS

I/O7 - I/O0

FFFFFH

AT49F080/080T

optional to the user. The address range of the AT49F080
boot block is 00000H to 03FFFH while the address range of
the AT49F080T boot block is FC000H to FFFFFH.

To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVER-
RIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12V

0.5V. By doing

this, protected boot block data can be altered through a
chip erase, or byte programming. When the RESET pin is
brought back to TTL levels, the boot block programming
lockout feature is again active.

PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT49F080 features DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA polling, the AT49F080
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.

RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain

connection allows for OR - tying of several devices to the
same RDY/BUSY line.

RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program
or erase operation, the operation may not be successfully
completed and the operation will have to be repeated after
a high level is applied to the RESET pin. When a high level
is reasserted on the RESET pin, the device returns to the
read or standby mode, depending upon the state of the
control inputs. By applying a 12V

0.5V input signal to the

RESET pin, the boot block array can be reprogrammed
even if the boot block lockout feature has been enabled
(see Boot Block Programming Lockout Override section).

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F080 in
the following ways: (a) V

sense: if V

is below 3.8V

(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.

AT49F080/080T

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

*NOTICE:

Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages
with Respect to Ground ............................ -0.6V to V

+ 0.6V

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

Notes:

1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F080 and FC000H to FFFFFH for the

AT49F080T.

2. Either one of the Product ID Exit commands can be used.

Command Definition (in Hex)

Command
Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

Addr

OUT

Chip Erase

5555

2AAA

5555

2AAA

5555

Byte Program

5555

2AAA

5555

Addr

Boot Block Lockout

(1)

5555

2AAA

5555

2AAA

5555

Product ID Entry

5555

2AAA

5555

Product ID Exit

(2)

5555

2AAA

5555

Product ID Exit

(2)

XXXX

AT49F080/080T

Notes:

1. X can be V

or V

2. Refer to AC Programming Waveforms.

3. V

= 12.0V

0.5V

4. Manufacturer Code: 1FH

Device Code: 23H (AT49F080), 27H (AT49F080T)

5. See details under Software Product Identification Entry/Exit..

Note:

1. I

in the erase mode is 90 mA.

DC and AC Operating Range

AT49F080-90

AT49F080-12

AT49F080-15

Operating
Temperature (Case)

Com.

0°C - 70°C

Ind.

-40°C - 85°C

Power Supply

10%

Operating Modes

Mode

RESET

I/O

RDY/BUSY

Read

OUT

Program

(2)

Standby/Write
Inhibit

(1)

High Z

Program Inhibit

Output Disable

High Z

RESET

High Z

Product Identification

Hardware

A1 - A19 = V

, A9 = V

(3)

A0 = V

Manufacturer Code

(4)

A1 - A19 = V

, A9 = V

(3)

A0 = V

Device Code

(4)

Software

(5)

A0 = V

, A1 - A19 = V

Manufacturer Code

(4)

A0 = V

, A1 - A19 = V

Device Code

(4)

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

Input Load Current

= 0V to V

Output Leakage Current

I/O

= 0V to V

SB1

Standby Current CMOS

CE = V

- 0.3V to V

Com.

100

Ind.

300

SB2

Standby Current TTL

CE = 2.0V to V

(1)

Active Current

f = 5 MHz; I

OUT

= 0 mA

Input Low Voltage

0.8

Input High Voltage

2.0

Output Low Voltage

= 2.1 mA

0.45

OH1

Output High Voltage

= -400

2.4

OH2

Output High Voltage CMOS

= -100

A; V

= 4.5V

4.2

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