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Электронный компонент: AT75C140

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1
Features
ARM7TDMI
ARM
Thumb
Processor
Core
High-performance
32-bit
RISC
Architecture
Embedded
ICE
(In-circuit
Emulation)
On-chip
SDRAM
Controller
for
Embedded
ARM7TDMI
Multi-layer
AMBA
TM
Architecture
Dual
Ethernet
10/100
Mbps
MAC
Interface
Two
USARTs
with
Modem
Control
Lines
Industry-standard
Serial
Peripheral
Interface
(SPI)
Flexible
External
Bus
Interface
with
Programmable
Chip
Selects
Multi-level
Priority,
Individually-maskable,
Vectored
Interrupt
Controller
Three
16-bit
Timer/Counters
Additional
Watchdog
Timer
Up
to
48
General-purpose
I/O
Pins
JTAG
Debug
Interface
Software
Development
Tools
Available
for
ARM7TDMI
Supported
by
a
Wide
Range
of
Ready-to-use
Application
Software,
Including
Multi-
tasking
Operating
System
and
Networking
Functions
2.5V
Power
Supply
for
the
Core
and
PLL
Pins,
3.3V
for
Other
I/O
Pins
Available
in
208-lead
PQFP
and
in
256-ball
PBGA
Packages
Supports
Commercial
and
Industrial
Temperature
Range
Description
The
AT75C140
Smart
Internet
Appliance
Processor
(SIAP
TM
)
is
a
high-performance
processor
specially
designed
for
network-enabling
consumer
and
industrial
applica-
tions,
such
as
printers,
fax
machines,
industrial
automation,
data
acquisition
equipment
and
test
equipment.
The
AT75C140
is
built
around
an
ARM7TDMI
microcontroller
core
running
at
40
MHz
with
a
dual
Ethernet
10/100
Mbps
MAC
interface.
The
specific
architecture
of
the
AT75C140
delivers
unmatched
performance
for
low
power
consumption.
On
top
of
the
AT75C140
hardware
platform,
Atmel
provides
a
special
port
of
the
Linux
kernel
as
the
proposed
operating
system
with
device
drivers
for
the
peripherals.
Smart
Internet
Appliance
Processor
(SIAP
TM
)
AT75C140
Advance
Information
Rev.
2659AINTAP09/02
2
AT75C140
2659AINTAP09/02
AT75C140
Pin
Configuration
Note:
NC:
Not
connected
Table
1.
AT75C140
Pinout
in
208-lead
PQFP
Package
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
GND
43
MB_TXCLK
85
D4
127
NCE0
169
PA11
2
GND
44
MB_RXD0
86
VDD3V3
128
NCE1
170
PA10
3
VDD3V3
45
MB_RXD1
87
D5
129
NCE2
171
PA9
4
GND
46
MB_RXD2
88
D6
130
VDD3V3
172
PA8
5
NC
47
MB_RXD3
89
D7
131
NCE3
173
PA7
6
GND
48
MB_RXER
90
D8
132
NWE0
174
PA6
7
NTRST
49
MB_RXCLK
91
D9
133
NWE1
175
VDD3V3
8
MA_COL
50
MB_RXDV
92
D10
134
NWE2
176
NC
9
MA_CRS
51
MB_MDC
93
D11
135
VDD3V3
177
PA5
10
MA_TXER
52
VDD3V3
94
D12
136
GND
178
PA4
11
MA_TXD0
53
GND
95
D13
137
NWE3
179
PA3
12
MA_TXD1
54
MB_MDIO
96
D14
138
NWR
180
PA2
13
MA_TXD2
55
MB_LINK
97
VDD2V5
139
NSOE
181
PA1
14
MA_TXD3
56
A0
98
GND
140
GND
182
PA0
15
MA_TXEN
57
A1
99
D15
141
VDD2V5
183
GND
16
VDD3V3
58
A2
100
VDD3V3
142
NWAIT
184
RXDA
17
MA_TXCLK
59
A3
101
GND
143
MISO
185
TXDA
18
GND
60
A4
102
NREQ
144
MOSI
186
NRTSA
19
MA_RXD0
61
A5
103
NGNT
145
SPCK
187
NCTSA
20
MA_RXD1
62
A6
104
VDD3V3
146
NPCSS
188
NDTRA
21
MA_RXD2
63
A7
105
GND
147
VDD3V3
189
NDSRA
22
MA_RXD3
64
A8
106
DCK
148
GND
190
NDCDA
23
MA_RXER
65
A9
107
NCS
149
NRESET
191
RXDB
24
MA_RXCLK
66
A10
108
A10
150
FIQ
192
TXDB
25
GND
67
A11
109
NRAS
151
IRQ0
193
GND
26
VDD2V5
68
A12
110
NCAS
152
TST
194
PB0
27
MA_RXDV
69
VDD3V3
111
NC
153
GND
195
PB1
28
MA_MDC
70
GND
112
NWE
154
VDD2V5
196
PB2
29
MA_MDIO
71
A13
113
DQM0
155
NC
197
PB3
30
MA_LINK
72
A14
114
DQM1
156
VDD3V3
198
PB4
31
MB_COL
73
A15
115
DQM2
157
GND
199
PB5
32
MB_CRS
74
A16
116
GND
158
VDD3V3
200
PB6
33
GND
75
A17
117
DQM3
159
TDO
201
PB7
34
VDD2V5
76
A18
118
VDD2V5
160
TDI
202
PB8
35
VDD3V3
77
A19
119
GND
161
TMS
203
PB9
36
MB_TXER
78
A20
120
PLL_VDD
162
TCK
204
VDD3V3
37
MB_TXD0
79
A21
121
XREF240
163
PA19
205
DBW32
38
MB_TXD1
80
D0
122
PLL_GND
164
VDD2V5
206
GND
39
MB_TXD2
81
D1
123
GND
165
GND
207
BO256
40
GND
82
D2
124
XTALOUT
166
PA12
208
VDD3V3
41
MB_TXD3
83
D3
125
XTALIN
167
GND
42
MB_TXEN
84
GND
126
VDD2V5
168
VDD3V3
3
AT75C140
2659AINTAP09/02
Table
2.
AT75C140
Pinout
in
256-ball
PBGA
Package
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A01
GND
C03
DBW32
E17
PA30
K19
NCE3
T01
MB_TXD2
A02
PB9
C04
PB6
E18
TST
K20
NCE2
T02
MB_TXCLK
A03
PB4
C05
PB2
E19
IRQ0
L01
MA_RXD1
T03
MB_RXD1
A04
PB1
C06
NRIB
E20
NC
L02
MA_RXD2
T04
MB_RXER
A05
NDSRB
C07
NCTSB
F01
PB13
L03
MA_RXD3
T17
D28
A06
NRTSB
C08
NRIA
F02
PB12
L04
MA_RXER
T18
D31
A07
RXDB
C09
NCTSA
F03
GND
L17
VDD3V3
T19
DCLK
A08
NDSRA
C10
PA0
F04
VDD3V3
L18
NCE0
T20
NCS
A09
TXDA
C11
PA4
F17
VDD3V3
L19
VDD2V5
U01
MB_RXD0
A10
PA2
C12
PA8
F18
FIQ
L20
NCE1
U02
MB_RXD2
A11
PA3
C13
PA12
F19
NC
M01
MA_RXCLK
U03
MB_RXCLK
A12
PA6
C14
PA14
F20
SPCK
M02
VDD3V3
U04
GND
A13
PA10
C15
PA18
G01
MA_COL
M03
MA_RXDV
U05
A1
A14
PA13
C16
PA21
G02
PB15
M04
MA_MDC
U06
VDD3V3
A15
PA15
C17
TCK
G03
PB14
M17
XREF240
U07
A8
A16
PA19
C18
NC
G04
NTRST
M18
PLL_GND
U08
GND
A17
PA22
C19
NC
G17
NRESET
M19
XTALOUT
U09
A17
A18
PA23
C20
PA31
G18
NPCSS
M20
XTALIN
U10
VDD3V3
A19
TDO
D01
PB11
G19
MOSI
N01
MA_MDIO
U11
D3
A20
NC
D02
PA27
G20
MISO
N02
MA_LINK
U12
D7
B01
BO256
D03
PA26
H01
MA_TXD0
N03
MB_COL
U13
GND
B02
PB8
D04
GND
H02
MA_TXER
N04
GND
U14
D16
B03
PB7
D05
PB5
H03
MA_CRS
N17
GND
U15
VDD3V3
B04
PB3
D06
VDD3V3
H04
GND
N18
DQM3
U16
D22
B05
PB0
D07
NDCDB
H17
GND
N19
VDD3V3
U17
GND
B06
NDTRB
D08
GND
H18
NWAIT
N20
PLL_VDD
U18
D27
B07
TXDB
D09
NDTRA
H19
VDD3V3
P01
MB_CRS
U19
NC
B08
NDCDA
D10
RXDA
H20
NSOE
P02
VDD2V5
U20
D30
B09
NRTSA
D11
VDD3V3
J01
MA_TXEN
P03
MB_TXD0
V01
MB_RXD3
B10
PA1
D12
PA9
J02
MA_TXD3
P04
MB_TXD3
V02
MB_RXDV
B11
PA5
D13
GND
J03
MA_TXD2
P17
NRAS
V03
NC
B12
PA7
D14
PA17
J04
MA_TXD1
P18
DQM0
V04
A0
B13
PA11
D15
VDD3V3
J17
NWR
P19
DQM1
V05
A4
B14
VDD3V3
D16
PA24
J18
NWE3
P20
DQM2
V06
A7
B15
PA16
D17
GND
J19
NC
R01
MB_TXER
V07
A11
B16
PA20
D18
PA29
J20
NWE2
R02
MB_TXD1
V08
A14
B17
TMS
D19
VDD3V3
K01
MA_RXD0
R03
MB_TXEN
V09
A18
B18
TDI
D20
IRQ1
K02
MA_TXCLK
R04
VDD3V3
V10
A22
B19
NC
E01
NC
K03
NC
R17
VDD3V3
V11
D2
B20
NC
E02
GND
K04
VDD3V3
R18
A10
V12
D6
C01
PB10
E03
GND
K17
NWE1
R19
NCAS
V13
D10
C02
PA28
E04
PA25
K18
NWE0
R20
NWE
V14
D14
4
AT75C140
2659AINTAP09/02
Note:
NC:
Not
connected
V15
NC
W05
A5
W15
VDD3V3
Y05
A6
Y15
D13
V16
D19
W06
A9
W16
D17
Y06
A10
Y16
D15
V17
D23
W07
A12
W17
D20
Y07
A13
Y17
D18
V18
D26
W08
A15
W18
D24
Y08
A16
Y18
D21
V19
NC
W09
A19
W19
NREQ
Y09
A20
Y19
D25
V20
D29
W10
A21
W20
NC
Y10
A23
Y20
NGNT
W01
MB_MDC
W11
D1
Y01
NC
Y11
D0
W02
NC
W12
D5
Y02
MB_MDIO
Y12
D4
W03
NC
W13
D9
Y03
A2
Y13
D8
W04
MB_LINK
W14
D12
Y04
A3
Y14
D11
Table
2.
AT75C140
Pinout
in
256-ball
PBGA
Package
(Continued)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Table
3.
AT75C140
Pin
Description
List
in
208-lead
PQFP
Package
and
256-ball
PBGA
Package
Block
Pin
Name
in
Package
Type
Function
Active
Level
Type
256-ball
PBGA
208-lead
PQFP
Common
Bus
A[23:0]
A[21:0]
Address
Bus
-
Output,
TS
(1)
D[31:0]
D[15:0]
Data
Bus
-
I/O
(2)
NREQ
NREQ
Bus
Request
Low
Input
NGNT
NGNT
Bus
Grant
Low
Output
Synchronous
Dynamic
Memory
Controller
DCLK
DCLK
SDRAM
Clock
-
Output
DQM[3:0]
DQM[1:0]
SDRAM
Byte
Masks
-
Output
NCS
NCS
SDRAM
Chip
Select
Low
Output
A10
A10
SDRAM
Auto
Precharge
-
Output
NRAS
NRAS
Row
Address
Strobes
Low
Output
NCAS
NCAS
Column
Address
Strobes
Low
Output
NWE
NWE
SDRAM
Write
Enable
Low
Output
Static
Memory
Controller
NCE[3:0]
NCE[3:0]
Chip
Select
Low
Output,
TS
NWE[3:0]
NWE[3:0]
Byte
Select/Write
Enable
Low
Output
NSOE
NSOE
Output
Enable
Low
Output,
TS
NWR
NWR
Memory
Block
Write
Enable
Low
Output
NWAIT
NWAIT
Enable
Wait
States
Low
Input
I/O
Port
A
PA[12:0]
PA[19]
PA[12:0]
PA[19]
General-purpose
I/O
lines.
Multiplexed
with
peripheral
I/Os
-
I/O
PA[18:13]
PA[31:20]
-
I/O,
PD
(3)
I/O
Port
B
PB[9:0]
PB[9:0]
General-purpose
I/O
lines.
Multiplexed
with
peripheral
I/Os
-
I/O
PB[15:10]
-
I/O,PD
5
AT75C140
2659AINTAP09/02
Timer/Counter
0
TCLK0
TCLK0
Timer
0
External
Clock
-
Input
TIOA0
TIOA0
Timer
0
Signal
A
-
I/O
TIOB0
TIOB0
Timer
0
Signal
B
-
I/O
Timer/Counter
1
TCLK1
TCLK1
Timer
1
External
Clock
-
Input
TIOA1
TIOA1
Timer
1
Signal
A
-
I/O
TIOB1
TIOB1
Timer
1
Signal
B
-
I/O
Watchdog
NWDOVF
NWDOVF
Watchdog
Overflow
Low
Output
Serial
Peripheral
Interface
MISO
MISO
Master
In/Slave
Out
-
I/O
MOSI
MOSI
Master
Out/Slave
In
-
I/O
SPCK
SPCK
Serial
Clock
-
I/O
NPCSS
NPCSS
Peripheral
Chip
Select/Slave
Select
Low
I/O
NPCS1
NPCS1
Optional
SPI
Chip
Select
1
Low
Output
USART
A
RXDA
RXDA
Receive
Data
-
Input
TXDA
TXDA
Transmit
Data
-
Output
NRTSA
NRTSA
Ready
to
Send
Low
Output
NCTSA
NCTSA
Clear
to
Send
Low
Input
NDTRA
NDTRA
Data
Terminal
Ready
Low
Output
NDSRA
NDSRA
Data
Set
Ready
Low
Input
NDCDA
NDCDA
Data
Carrier
Detect
Low
Input
NRIA
-
Ring
Indicator
Low
Input,
PU
(4)
USART
B
RXDB
RXDB
Receive
Data
-
Input
TXDB
TXDB
Transmit
Data
-
Output
NRTSB
-
Ready
to
Send
Low
Output
NCTSB
-
Clear
to
Send
Low
Input,
PU
NDTRB
-
Data
Terminal
Ready
Low
Output
NDSRB
-
Data
Set
Ready
Low
Input,
PU
NDCDB
-
Data
Carrier
Detect
Low
Input,
PU
NRIB
-
Ring
Indicator
Low
Input,
PU
JTAG
Interface
NTRST
NTRST
Test
Reset
Low
Input
TCK
TCK
Test
Clock
-
Input
TMS
TMS
Test
Mode
Select
-
Input
TDI
TDI
Test
Data
Input
-
Input
TDO
TDO
Test
Data
Output
-
Output
Table
3.
AT75C140
Pin
Description
List
in
208-lead
PQFP
Package
and
256-ball
PBGA
Package
(Continued)
Block
Pin
Name
in
Package
Type
Function
Active
Level
Type
256-ball
PBGA
208-lead
PQFP