1
Features
Compatible with MCS
51 Products
4K Bytes of Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
2.7V to 6V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
Two-level Program Memory Lock
128 x 8-bit Internal RAM
15 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Programmable Serial UART Channel
Direct LED Drive Outputs
On-chip Analog Comparator
Low-power Idle and Power-down Modes
Brown-out Detection
Description
The AT89C4051 is a low-voltage, high-performance CMOS 8-bit microcomputer with
4K bytes of Flash programmable and erasable read-only memory (PEROM). The
device is manufactured using Atmel's high-density nonvolatile memory technology and
is compatible with the industry-standard MCS-51 instruction set. By combining a ver-
satile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C4051 is a powerful
microcomputer which provides a highly-flexible and cost-effective solution to many
embedded control applications.
The AT89C4051 provides the following standard features: 4K bytes of Flash,
128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five-vector, two-level inter-
rupt architecture, a full duplex serial port, a precision analog comparator, on-chip
oscillator and clock circuitry. In addition, the AT89C4051 is designed with static logic
for operation down to zero frequency and supports two software-selectable power sav-
ing modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The power-down mode saves
the RAM contents but freezes the oscillator disabling all other chip functions until the
next hardware reset.
Pin Configuration
PDIP/SOIC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RST/VPP
(RXD) P3.0
(TXD) P3.1
XTAL2
XTAL1
(INT0) P3.2
(INT1) P3.3
(TO) P3.4
(T1) P3.5
GND
VCC
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1 (AIN1)
P1.0 (AIN0)
P3.7
Rev. 1001D06/01
8-bit
Microcontroller
with 4K Bytes
Flash
AT89C4051
2
AT89C4051
1001D06/01
Block Diagram
3
AT89C4051
1001D06/01
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 1
Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pullups.
P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input
(AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog com-
parator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7
are used as inputs and are externally pulled low, they will source current (I
IL
) because of
the internal pullups.
Port 1 also receives code data during Flash programming and verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pullups.
P3.6 is hard-wired as an input to the output of the on-chip comparator and is not acces-
sible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s
are written to Port 3 pins they are pulled high by the internal pullups and can be used as
inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I
IL
)
because of the pullups.
Port 3 also serves the functions of various special features of the AT89C4051 as listed
below:
Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin
high for two machine cycles while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Port Pin
Alternate Functions
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
P3.2
INT0 (external interrupt 0)
P3.3
INT1 (external interrupt 1)
P3.4
T0 (timer 0 external input)
P3.5
T1 (timer 1 external input)
4
AT89C4051
1001D06/01
Oscillator
Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which
can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external clock signal, since the input
to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and
maximum voltage high and low time specifications must be observed.
Figure 1. Oscillator Connections
Note:
C1, C2= 30 pF
10 pF for Crystals
= 40 pF
10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
5
AT89C4051
1001D06/01
Special Function
Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is
shown in the table below.
Note that not all of the addresses are occupied, and unoccupied addresses may not be
implemented on the chip. Read accesses to these addresses will in general return ran-
dom data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in
future products to invoke new features. In that case, the reset or inactive values of the
new bits will always be 0.
Table 1. AT89C4051 SFR Map and Reset Values
0F8H
0FFH
0F0H
B
00000000
0F7H
0E8H
0EFH
0E0H
ACC
00000000
0E7H
0D8H
0DFH
0D0H
PSW
00000000
0D7H
0C8H
0CFH
0C0H
0C7H
0B8H
IP
XXX00000
0BFH
0B0H
P3
11111111
0B7H
0A8H
IE
0XX00000
0AFH
0A0H
0A7H
98H
SCON
00000000
SBUF
XXXXXXXX
9FH
90H
P1
11111111
97H
88H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
8FH
80H
SP
00000111
DPL
00000000
DPH
00000000
PCON
0XXX0000
87H
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