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Электронный компонент: M44C090-V

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M44C090-V
Rev. A2, 21-Nov-01
1 (60)
Low-Current Microcontroller for Wireless Communication
The M44C090-V is a member of Atmel Wireless & Microcontrollers' family of 4-bit single-chip microcontrollers.
They offer highest integration for IR and RF data communication and remote-control applications. The M44C090-V
is suitable for the transmitter side. It contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction
timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and a sophisticated
on-chip clock generation with external clock input, integrated RC-, 32-kHz crystal- and 4-MHz crystal-oscillators.
Features / Benefits
D Extended temperature range for very high tempera-
ture up to 125
_C
D 2-Kbyte ROM, 256 x 4-bit RAM
D 12 bidirectional I/Os
D Up to 6 external / internal interrupt sources
D Multifunction timer/counter with
IR remote control carrier generator
Biphase-, Manchester- and pulse-width modulator
D Programmable system-clock with prescaler and five
different clock sources
D Supply voltage range (1.8 to 6.5 V)
D Very low sleep current (< 1 A)
D Synchronous serial interface (2-wire, I
2
C, 3-wire)
D Watchdog, POR and brown-out function
D Voltage monitoring incl. Lo_BAT detect
D Flash controller T48C893 available (SSO20)
Voltage monitor
External input
MARC4
UTCM
OSC1
OSC2
I/O bus
ROM
RAM
4-bit CPU core
256 x 4 bit
VDD
VSS
Data direction +
alternate function
Data direction +
interrupt control
Port 4
Port 5
Brown-out protect.
RESET
Clock management
Timer 1
watchdog timer
Timer 2
Serial interface
Port 2
Data direction
T2O
SD
SC
BP20/NTE
BP21
BP22
BP23
BP40
INT3
SC BP41
VMI
T2I
BP42
T2O BP43
INT3
SD
BP50
INT6
BP51
INT6
BP52
INT1
BP53
INT1
RC
oscillators
Crystal
oscillators
2 K x 8 bit
VMI
with modulator
SSI
External
clock input
interval- and
8/12-bit timer
T2I
Figure 1. Block diagram M44C090-V
M44C090-V
Rev. A2, 21-Nov-01
2 (60)
M44C090-V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
16
V
DD
BP40/INT3/SC
BP53/INT1
BP52/INT1
BP51/INT6
BP50/INT6
OSC1
OSC2
nc
nc
V
SS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
nc
nc
Figure 2. Pinning SSO20 package
Table 1 Pin description
Name
Type
Function
Alternate Function
Pin-No.
SSO20
Reset
State
V
DD
Supply voltage
1
NA
V
SS
Circuit ground
20
NA
nc
Not connected
10
nc
Not connected
11
BP20
I/O
Bidirectional I/O line of Port 2.0
NTEtest mode enable
13
Input
BP21
I/O
Bidirectional I/O line of Port 2.1
14
Input
BP22
I/O
Bidirectional I/O line of Port 2.2
15
Input
BP23
I/O
Bidirectional I/O line of Port 2.3
16
Input
BP40
I/O
Bidirectional I/O line of Port 4.0
SC-serial clock or INT3 external in-
terrupt input
2
Input
BP41
I/O
Bidirectional I/O line of Port 4.1
VMI voltage monitor input or T2I
external clock input Timer 2
17
Input
BP42
I/O
Bidirectional I/O line of Port 4.2
T2O Timer 2 output
18
Input
BP43
I/O
Bidirectional I/O line of Port 4.3
SD serial data I/O or INT3external
interrupt input
19
Input
BP50
I/O
Bidirectional I/O line of Port 5.0
INT6 external interrupt input
6
Input
BP51
I/O
Bidirectional I/O line of Port 5.1
INT6 external interrupt input
5
Input
BP52
I/O
Bidirectional I/O line of Port 5.2
INT1 external interrupt input
4
Input
BP53
I/O
Bidirectional I/O line of Port 5.3
INT1 external interrupt input
3
Input
nc
Not connected
9
nc
Not connected
12
OSC1
I
Oscillator input
4-MHz crystal input or 32-kHz crys-
tal input or external clock input or
external trimming resistor input
7
Input
OSC2
O
Oscillator output
4-MHz crystal output or 32-kHz
crystal output
8
NA
M44C090-V
Rev. A2, 21-Nov-01
3 (60)
Table of Contents
1
Introduction
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
MARC4 Architecture
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
General Description
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Components of MARC4 Core
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
ROM
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
RAM
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Registers
7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
ALU
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
I/O Bus
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
Instruction Set
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7
Interrupt Structure
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupts
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Interrupts
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Master Reset
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Power-on Reset and Brown-out Detection
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Watchdog Reset
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
External Clock Supervisor
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Voltage Monitor
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
Voltage Monitor Control / Status Register
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Clock Generation
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
Clock Module
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Oscillator Circuits and External Clock Input Stage
16
. . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 1 Fully Integrated
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 2 with External Trimming Resistor
16
. . . . . . . . . . . . . . . . . . . . . . . . .
4-MHz Oscillator
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Clock Management
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Management Register (CM)
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Configuration Register (SC)
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Power-Down Modes
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Peripheral Modules
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Addressing Peripherals
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Bidirectional Ports
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
Bidirectional Port 2
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Data Register (P2DAT)
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Control Register (P2CR)
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Bidirectional Port 5
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Bidirectional Port 4
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Universal Timer/Counter / Communication Module (UTCM)
25
. . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Timer 1
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 1 Control Register 1 (T1C1)
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M44C090-V
Rev. A2, 21-Nov-01
4 (60)
Table of Contents (continued)
Timer 1 Control Register 2 (T1C2)
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Control Register (WDC)
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
Timer 2
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Modes
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Output Modes
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Output Signals
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Registers
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Control Register (T2C)
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Mode Register 1 (T2M1)
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Mode Register 2 (T2M2)
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Compare and Compare Mode Registers
37
. . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Compare Mode Register (T2CM)
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 COmpare Register 1 (T2CO1)
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 COmpare Register 2 (T2CO2) Byte Write
37
. . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
Synchronous Serial Interface (SSI)
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSI Peripheral Configuration
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General SSI Operation
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit Synchronous Mode
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-bit Shift Mode (I2C compatible)
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit Pseudo I2C Mode
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Bus Protocol
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSI Interrupt
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulation
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Registers
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Control Register 1 (SIC1)
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Control Register 2 (SIC2)
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Status and Control Register (SISC)
46
. . . . . . . . . . . . . . . . . . . . . . .
Serial Transmit Buffer (STB) Byte Write
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Receive Buffer (SRB) Byte Read
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4
Combination Modes
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combination Mode Timer 2 and SSI
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Electrical Characteristics
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Absolute Maximum Ratings
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
DC Operating Characteristics
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
AC Characteristics
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Package Information
58
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Ordering Information
59
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M44C090-V
Rev. A2, 21-Nov-01
5 (60)
1
Introduction
The M44C090-V is a member of Atmel Wireless &
Microcontrollers's family of 4-bit single-chip micro-
controllers. They contain ROM, RAM, parallel I/O ports,
one 8-bit programmable multifunction timer/counter,
voltage supervisor, interval timer with watchdog function
and a sophisticated on-chip clock generation with inte-
grated RC-, 32-kHz crystal- and 4-MHz
crystal-oscillators.
Table 2 provides an overview of the available variants.
Table 2 Available variants of M4xCx9x
Version
Type
ROM
E
2
PROM Peripheral
Packages
Flash device
T48C893
4 Kbyte EEPROM
64 byte
SSO20
Production
M44C090-V
2 Kbyte mask ROM
64 byte
SSO20
2
MARC4 Architecture
2.1
General Description
The MARC4 microcontroller consists of an advanced
stack-based, 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with
physically separate program memory (ROM) and data
memory (RAM). Three independent buses, the
instruction bus, the memory bus and the I/O bus, are used
for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes both, an expression and a
return stack. This architecture enables high-level
language programming without any loss of efficiency or
code density.
Instruction
decoder
CCR
TOS
ALU
RAM
PC
RP
SP
X
Y
Program
256 x 4-bit
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
Onchip peripheral modules
94 8973
memory
Figure 3. MARC4 core