100-MHz Differential Buffer for PCI Express and SATA

CY28401

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07592 Rev. **

Revised November 24, 2003

Features

· CK409 or CK410 companion buffer
· Eight differential 0.7v clock pairs
· Individual OE controls
· Low CTC jitter (< 50 ps)
· Programmable bandwidth
· SRC_STOP# power management control
· SMBus Block/Byte/Word Read and Write support
· 3.3V operation
· PLL Bypass-configurable
· Divide by 2 programmable
· 48-pin SSOP package

Functional Description

The CY28401 is a differential buffer and serves as a

companion device to the CK409 or CK410 clock generator.

The device is capable of distributing the Serial Reference

Clock (SRC) in PCI Express and SATA implementations.

Block Diagram

Pin Configuration

Output

Buffer

Output

Control

PLL

DIV

SMBus

Controller

SRC_STOP#

PWRDWN#

SCLK

SDATA

SRC_DIV2#

PLL/BYPASS#

SRCT_IN

SRCC_IN

HIGH_BW#

OE_[0:7]

DIFT2

DIFC2

DIFT1

DIFC1

DIFT0

DIFC0

DIFT3

DIFC3

DIFT4

DIFC4

DIFT5

DIFC5

DIFT6

DIFC6

DIFT7

DIFC7

LOCK

48 SSOP

SRC_DIV2#

VDD

SRCT_IN

SRCC_IN

OE_0
OE_3

DIFT0

DIFCO

VSS

VDD

DIFT1

DIFC1

OE_1
OE_2

DIFT2

DIFC2

VSS

VDD

DIFT3

DIFC3

PLL/BYPASS#

SCLK

SDATA

VDD_A
VSS_A

DIFT5

OE_6
OE_5

DIFC6

VDD
DIFT6

VSS

DIFT7
DIFC7

OE_4

LOCK
OE_7

VDD

VSS

DIFT4

DIFC5

IREF

SRC_STOP#
PWRDWN#
VSS

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

CY284

VSS

DIFC4
HIGH_BW#

CY28401

Document #: 38-07592 Rev. **

Page 2 of 14

Serial Data Interface

To enhance the flexibility and function of the clock buffer, a

two-signal serial interface is provided. Through the Serial Data

Interface, various device functions, such as individual clock

output buffers, can be individually enabled or disabled. The

registers associated with the Serial Data Interface initializes to

their default setting upon power-up, and therefore use of this

interface is optional. Clock device register changes are

normally made upon system initialization, if any are required.

The interface cannot be used during system operation for

power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 1.
The block write and block read protocol is outlined in Table 2

while Table 3 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11011100 (DCh).

Pin Description

Pin

Name

Type

Description

4,5

SRCT_IN, SRCC_IN

I,DIF

0.7V Differential SRC inputs from the clock synthesizer

8,9,12,13,16,17,20,21,29,30,

33,34,37,38,41,42

DIFT/C(7:0)

O,DIF 0.7V Differential Clock Outputs

6,7,14,15,35,36,43,44

OE_(7:0)

I,SE

3.3V LVTTL active low input for three-stating differential

outputs

HIGH_BW#

I,SE

3.3V LVTTL input for selecting PLL bandwidth

LOCK

O,SE 3.3V LVTTL output, transitions high when PL lock is

achieved (latched output)

PWRDWN#

I,SE

3.3V LVTTL input for Power Down, active low

SRC_DIV/2#

I,SE

3.3V LVTTL input for selecting input frequency divided by

two, active low

SRC_STOP#

I,SE

3.3V LVTTL input for SRC_Stop#, active low

SCLK

I,SE

SMBus Slave Clock Input

SDATA

I/O,OC Open collector SMBus data

IREF

A precision resistor is attached to this pin to set the differ-

ential output current

PLL/BYPASS#

3.3V LVTTL input for selecting fan-out or PLL operation

VDD_A

3.3V

3.3V Power Supply for PLL

VSS_A

GND

Ground for PLL

3,10,18,25,32,40

VSS

Ground for outputs

2,11,19,31,39

VDD

3.3V power supply for outputs

Table 1. Command Code Definition

Bit

Description

0 = Block read or block write operation

1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave

CY28401

Document #: 38-07592 Rev. **

Page 3 of 14

11:18

Command Code 8 bits

'00000000' stands for block operation

11:18

Command Code 8 bits

'00000000' stands for block operation

Acknowledge from slave

20:27

Byte Count from master 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 0 from master 8 bits

Read = 1

Acknowledge from slave

38:45

Data byte 1 from master 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge from host

....

Data bytes from master/Acknowledge

39:46

Data byte 0 from slave 8 bits

....

Data Byte N 8 bits

Acknowledge from host

....

Acknowledge from slave

48:55

Data byte 1 from slave 8 bits

....

Stop

Acknowledge from host

....

Data bytes from slave/Acknowledge

....

Data byte N from slave 8 bits

....

Acknowledge from host

....

Stop

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave

11:18

Command Code 8 bits

'100xxxxx' stands for byte operation, bits[6:0] of the

command code represents the offset of the byte to be

accessed

11:18

Command Code 8 bits

'100xxxxx' stands for byte operation, bits[6:0]

of the command code represents the offset of

the byte to be accessed

Acknowledge from slave

20:27

Data byte from master 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

Stop

Read = 1

Acknowledge from slave

30:37

Data byte from slave 8 bits

Acknowledge from master

Stop

Byte 0: Control Register 0

Bit

@pup

Name

Description

PWRDWN# drive mode

o = Driven when stopped, 1 = Three-state

SRC_STOP# drive mode

o = Driven when stopped, 1 = Three-state

Reserved

Table 2. Block Read and Block Write Protocol (continued)

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

CY28401

Document #: 38-07592 Rev. **

Page 4 of 14

Reserved

HIGH_BW#

0 = High Bandwidth, 1 = Low bandwidth

PLL/Bypass#

0 = Fanout buffer, 1 = PLL mode

SRC_DIV/2

0 = Divided by 2 mode,1 = Normal (output = input)

Byte 1: Control Register 1

Bit

@pup

Name

Description

DIF_7 Output Enable

0 = Disabled (three-state)

1 = Enabled

DIF_6 Output Enable

0 = Disabled (three-state)

1 = Enabled

DIF_5 Output Enable

0 = Disabled (three-state)

1 = Enabled

DIF_4 Output Enable

0 = Disabled (three-state)

1 = Enabled

DIF_3 Output Enable

0 = Disabled (three-state)

1 = Enabled

DIF_2 Output Enable

0 = Disabled (three-state)

1 = Enabled

DIF_1 Output Enable

0 = Disabled (three-state)

1 = Enabled

DIF_0 Output Enable

0 = Disabled (three-state)

1 = Enabled

Byte 2: Control Register 2

Bit

@pup

Name

Description

Allow Control DIF_7 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Allow Control DIF_6 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Allow Control DIF_5 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Allow Control DIF_4 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Allow Control DIF_3 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Byte 0: Control Register 0 (continued)

Bit

@pup

Name

Description

CY28401

Document #: 38-07592 Rev. **

Page 5 of 14

Allow Control DIF_2 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Allow Control DIF_1 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Allow Control DIF_0 with assertion of SRC_STOP#

0 = Free-running

1 = Stopped with SRC_STOP#

Byte 3: Control Register 3

Bit

@pup

Name

Description

Reserved

Byte 4: Vendor ID Register

Bit

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

Vendor ID Bit 2

Vendor ID Bit 1

Vendor ID Bit 0

Byte 5: Control Register 5

Bit

@Pup

Name

Description

Reserved

Byte 2: Control Register 2 (continued)

Bit

@pup

Name

Description

CY28401

Document #: 38-07592 Rev. **

Page 6 of 14

PWRDWN# Clarification

[1]

The PWRDWN# pin is used to shut off all clocks cleanly and

instruct the device to evoke power savings mode. Additionally,

PWRDWN# should be asserted prior to shutting off the input

clock or power to ensure all clocks shut down in a glitch-free

manner. PWRDWN# is an asynchronous active low input. This

signal is synchronized internal to the device prior to powering

down the clock buffer. PWRDWN# is an asynchronous input

for powering up the system. When PWRDWN# is asserted

low, all clocks will be held high or three-stated (depending on

the state of the control register drive mode and OE bits) prior

to turning off the VCO. All clocks will start and stop without any

abnormal behavior and must meet all AC and DC parameters.

This means no glitches, frequency shifting or amplitude abnor-

malities among others.

PWRDWN#--Assertion

When PWRDWN# is sampled low by two consecutive rising

edges of DIFC, all DIFT outputs will be held high or

three-stated (depending on the state of the control register

drive mode and OE bits) on the next DIFC high to low

transition. When the SMBus power-down drive mode bit is

programmed to `0', all clock outputs will be held with the DIFT

pin driven high at 2 x Iref and DIFC three-state. However, if the

control register PWRDWN# drive mode bit is programmed to

`1', then both DIFT and the DIFC are three-stated.

PWRDWN#--Deassertion

The power-up latency is less than 1 ms. This is the time from

the deassertion of the PWRDWN# pin or the ramping of the

power supply or the time from valid SRC_IN input clocks until

the time that stable clocks are output from the buffer chip (PLL

locked). IF the control register PWRDWN# three-state bit is

programmed to `1', all differential outputs must be driven high

in less than 300

µS of PWRDWN# deassertion to a voltage

greater than 200 mV.

Notes:

1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches

excessive frequency shifting.

2. The total power up latency from power on to all outputs active is less than 1ms (assuming a valid clock is present on SRC_IN input)
3. LOCk output is a latched signal that is reset with the assertion of PWRDWN# or when VDD<1.8V,
4. Special care must be taken to ensure that no abnormal clock behavior occurs after the assertion PLL LOCK (i.e overshoot undershoot is allowed).
5. If power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks

are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled.

6. In the case where OE is asserted low, the output will always be three-stated regardless of SRC_STOP# drive mode register bit state.

PWRDWN#

DIFC

DIFT

Figure 1. PWRDWN# Assertion Diagram

Table 4. Buffer Power-up State Machine

State

Description

3.3V Buffer power off

After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms0.3-ms delay

[5]

Buffer waits for a valid clock on the SRC_IN input and PWRDWN# deassertion

[2,3,4]

Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation

DIFC

DIFT

Tstable

<1mS

PWRDWN#

Tdrive_Pwrdwn#

<300uS, >200mV

Figure 2. PWRDWN# Deassertion Diagram

CY28401

Document #: 38-07592 Rev. **

Page 7 of 14

SRC_STOP# Clarification

The SRC_STOP# signal is an active low input used for clean

stopping and starting the DIFT/C outputs (valid clock must be

present on SRCT/C_IN). The SRC_STOP# signal is a

debounced signal in that it's state must remain unchanged

during two consecutive rising edges of DIFC to be recognized

as a valid assertion or deassertion. (The assertion and

deassertion of this signal is absolutely asynchronous).

SRC_STOP# Assertion

The impact of asserting the SRC_STOP# pin is all DIF outputs

that are set in the control registers to stoppable via assertion

of SRC_STOP# are stopped after their next transition. When

the control register SRC_STOP# three-state bit is

programmed to `0', the final state of all stopped DIFT/C signals

is DIFT clock = High and DIFC = Low. There will be no change

to the output drive current values, DIFT will be driven high with

a current value equal 6 x Iref, and DIFC will not be driven.

When the control register SRC_STOP# three-state bit is

programmed to `1', the final state of all stopped DIF signals is

low, both DIFT clock and DIFC clock outputs will not be driven.

SRC_STOP# Deassertion

All differential outputs that were stopped will resume normal

operation in a glitch-free manner. The maximum latency from

the deassertion to active outputs is between 2-6 DIFT/C clock

periods (2 clocks are shown) with all DIFT/C outputs resuming

simultaneously. If the control register three-state bit is

programmed to `1' (three-state), then all stopped DIFT outputs

will be driven high within 10 ns of SRC_STOP# deassertion to

a voltage greater than 200 mV.

Wait for Input

Clock &

PWRDWN# De-

assertion

PWRDWN# Asserted

Delay

>0.25ms

Power Off

Normal

Operation

No Input Clock

Figure 3. Buffer Power-up State Diagram

Table 5. SRC_STOP# Functionality

[6]

SRC_STOP#

DIFT

DIFC

Normal

Iref * 6 or Float

Low

DIFC (Stoppable)

DIFT (Stoppable)

DIFC(Free Running

DIFT(Free Running

PWRDWN#

1mS

SRC_STOP#

Figure 4. SRC_STOP# = Driven, PWRDWN# = Driven

CY28401

Document #: 38-07592 Rev. **

Page 8 of 14

Output Enable Clarification

The OE function may be implemented in two ways, via writing

a `0' to SMBus register bit corresponding to output of interest

or by asserting an OE input pin low. In both methods, if SMBus

registered bit has been written low or the OE pin is low or both,

the output of interest will be three-stated. (The assertion and

deassertion of this signal is absolutely asynchronous.)

DIFC (Stoppable)

DIFC(Free Running

PWRDWN#

1mS

SRC_STOP#

DIFT (Stoppable)

DIFT(Free Running

Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state

DIFC (Stoppable)

DIFC(Free Running

DIFT(Free Running

PWRDWN#

1mS

SRC_STOP#

DIFT (Stoppable)

Figure 6. SRC_STOP# =Three-state, PWRDWN# = Driven

DIFC(Free Running

DIFT(Free Running

DIFT (Stoppable)

DIFC (Stoppable)

PWRDWN#

1mS

SRC_STOP#

Figure 7. SRC_STOP# =Three-state, PWRDWN# = Three-state

Table 6. OE Functionality

OE (Pin)#

OE (SMBus Bit)

DIFT

DIFC

Normal

Three-state

Low

Three-state

Low

Three-state

Low

CY28401

Document #: 38-07592 Rev. **

Page 9 of 14

OE Assertion

(Transition from `0' to `1')

All differential outputs that were three-stated will resume

normal operation in a glitch-free manner. The maximum

latency from the assertion to active outputs is between 26 DIF

clock periods. In addition, DIFT clocks will be driven high within

10 ns of OE assertion to a voltage greater than 200 mV.

OE Deassertion

(Transition from `1' to `0')

The impact of deasserting OE is each corresponding output

will transition from normal operation to Three-state in a

glitch-free manner. The maximum latency from the

deassertion to three-stated outputs is between 26 DIF clock

periods.

LOCK Signal Clarification

The LOCK output signal is intended to provide designers a

signal indicating that PLL lock has been achieved and valid

clock are available. This can be helpful when cascading

multiple buffers which each contribute a 1-ms start-up delay in

addition to the start-up time of the clock source. Upon

receiving a valid clock on the SRC_IN input (PWRDWN#

deasserted), the buffer will begin ramping the internal PLL until

lock is achieved and stable, the clock buffer will assert the

LOCK pin high and enable DIF output clocks. In other words,

if power is valid and PWRDWN# is deasserted but no input

clocks are present on the SRC_IN input, all DIF clocks remain

disabled. Only after valid input clocks are detected, valid

power, PWRDWN# deasserted with the PLL locked and stable

are LOCK to be asserted and the DIF outputs enabled. The

maximum start-up latency from valid clocks on SRC_IN input

to the assertion of LOCK (output clocks are valid) is to be less

than 1 ms. Once LOCK has been asserted high, it will remain

high (regardless of the actual PLL status) until power is

removed or the PWRDWN# pin has been asserted.

SRC_DIV2# Clarification

The SRC_DIV2# input is used to configure the DIF output

mode to be equal to the SRC_IN input frequency or half the

input frequency in a glitch-free manner. The SRC_DIV2#

function may be implemented in two ways, via writing a `0' to

SMBus register bit or by asserting the SRC_DIV2# input pin

low. In both methods, if the SMBus register bit has been written

low or the SRC_DIV2# pin is low or both, all DIF outputs will

configured for divide by 2 operation.

SRC_DIV2# Assertion

The impact of asserting the SRC_DIV2# is all DIF outputs will

transition cleanly in a glitch-free manner from normal

operation (output frequency equal to input) to half the input

frequency within 26 DIF clock periods.

SRC_DIV2# Deassertion

The impact of deasserting the SRC_DIV2# is all DIF outputs

will transition cleanly in a glitch-free manner from divide by 2

mode to normal (output frequency is equal to the input

frequency) operation within 26 DIF clock periods.

PLL/BYPASS# Clarification

The PLL/Bypass# input is used to select between bypass

mode (no PLL) and PLL mode. In bypass mode, the input clock

is passed directly to the output stage resulting in 50-ps additive

jitter(50 ps + input jitter) on DIF outputs. In the case of PLL

mode, the input clock is pass through a PLL to reduce high

frequency jitter. The BYPASS# mode may be selected in two

ways, via writing a `0' to SMBus register bit or by asserting the

PLL/BYPASS# pin low. In both methods, if the SMBus register

bit has been written low or PLL/BYPASS# pin is low or both,

the device will be configure for BYPASS operation.

HIGH_BW# Clarification

The HIGH_BW# input is used to set the PLL bandwidth. This

mode is intended to minimize PLL peaking when two or more

buffers are cascaded by staggering device bandwidths. The

PLL low bandwidth mode may be selected in two ways, via

writing a `0' to SMBus register bit or by asserting the

HIGH_BW# pin is low or both, the device will be configured for

low bandwidth operation.

CY28401

Document #: 38-07592 Rev. **

Page 10 of 14

Absolute Maximum Conditions

Parameter

Description

Condition

Min.

Max.

Unit

Core Supply Voltage

0.5

4.6

DD_A

Analog Supply Voltage

0.5

4.6

Input Voltage

Relative to V

0.5

+ 0.5

VDC

Temperature, Storage

Non-functional

+150

°C

Temperature, Operating Ambient

Functional

°C

Temperature, Junction

Functional

150

°C

Dissipation, Junction to Case

Mil-Spec 883E Method 1012.1

TBD

°C/W

Dissipation, Junction to Ambient

JEDEC (JESD 51)

TBD

°C/W

ESD

HBM

ESD Protection (Human Body Model)

MIL-STD-883, Method 3015

2000

UL-94

Flammability Rating

At 1/8 in.

MSL

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing

is NOT required.

DC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

VDD_A

VDD

3.3V Operating Voltage

3.3 ± 5%

3.135

3.465

ILI2C

Input Low Voltage

SDATA, SCLK

1.0

IHI2C

Input High Voltage

SDATA, SCLK

2.2

3.3V Input Low Voltage

0.5

0.8

3.3V Input High Voltage

2.0

+ 0.5

3.3V Output Low Voltage

= 1 mA

0.4

3.3V Output High Voltage

= 1 mA

2.4

Input Low Leakage Current

except internal pull-up resistors, 0 < V

< V

µA

Input High Leakage Current

except internal pull-down resistors, 0 < V

< V

µA

High-impedance Output Current

µA

Input Pin Capacitance

OUT

Output Pin Capacitance

Pin Inductance

DD3.3V

Dynamic Supply Current

At max. load and 100 MHz

300

PD3.3V

Power-down Supply Current

PD asserted, Outputs driven

PD3.3V

Power-down Supply Current

PD asserted, Outputs Three-stated

AC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

DIF at 0.7V
T

DIFT and DIFC Duty Cycle

Measured at crossing point V

SKEW

Any DIFT/C to DIFT/C Clock Skew, SSC Measured at crossing point V

200

PERIOD

Average Period

Measured at crossing point V

at 100 MHz

9.9970

10.0533

CCJ

DIFT/C Cycle to Cycle Jitter

Measured at crossing point V

/ T

DIFT and DIFC Rise and Fall Times

Measured from V

= 0.175 to V

= 0.525V

175

700

RFM

Rise/Fall Matching

Determined as a fraction of 2*(T

)/(T

+ T

)

Rise Time Variation

125

Fall Time Variation

125

CY28401

Document #: 38-07592 Rev. **

Page 11 of 14

Switching Waveforms

HIGH

Voltage High

Measured SE

660

850

LOW

Voltage Low

Measured SE

150

Crossing Point Voltage at 0.7V Swing

250

550

Vcross Variation over all edges

140

OVS

Maximum Overshoot Voltage

HIGH

+ 0.3 V

UDS

Minimum Undershoot Voltage

0.3

Ring Back Voltage

Measured SE

0.2

N/A

PD(PLL)

Input to output skew in PLL mode

Measured at crossing point V

±250

PD(NONPLL)

Input to output skew in NonPLL mode Measured at crossing point V

2.5

6.5

AC Electrical Specifications

(continued)

Parameter

Description

Condition

Min.

Max.

Unit

D IF T

P C B

D IF C

3 3

4 9 .9

M e a s u r e m e n t

P o in t

2 p F

4 7 5

IR E F

M e a s u r e m e n t

P o in t

2 p F

T r a c e Im p e d a n c e M e a s u r e d D iffe r e n tia lly

Figure 8. Differential Clock Termination

Figure 9. Single-Ended Measurement Points for TRise and TFall

= 0.525V

TRise (CLOCK)

TFall (CLOCK)

CLO

CK#

= 0.175V

VCROSS

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