PRELIMINARY
1:20 Differential Clock Buffer/Driver
FastEdgeTM Series
CY2DP3120
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07514 Rev. *A
Revised April 16, 2003
Features
Twenty ECL/PECL differential outputs
Two ECL-/PECL-/HSTL-compatible differential clock
inputs
Hot-swappable/-insertable
50-ps output-to-output skew
500-ps device-to-device skew
Less than 10-ps intrinsic jitter
< 500-ps propagation delay (typical)
Operation from DC to 1.5 GHz
PECL mode supply range: V
CC
= 2.375V to 3.465V with
V
EE
= 0V
ECL mode supply range: V
EE
= 2.375V to 3.465V with
V
CC
= 0V
Industrial temperature range: 40
C to 85
C
52-pin 1.4-mm TQFP package
Temperature compensation like 100K ECL
Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device is fully differential and features two reference input
buffers. The CY2DP3120 may function not only as a differ-
ential clock buffer but also as a signal level translator and
fanout distributing a single-ended signal to twenty ECL/PECL
differential loads. An external bias pin, VBB, is provided for an
ECL/PECL/HSTL single-ended or differential. In such an appli-
cation, the VBB pin should be connected to either one of the
CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-
F
capacitor. Traditionally, in ECL, it is used to provide the
reference level to a receiving single ended input that might
have a different self bias point.
Since the CY2DP3120 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP3120 delivers consistent, guaranteed
performance over differing platforms.
Block Diagram
Pin Configuration
CLKA
CLKA#
VCC
CLKB
CLKB#
VCC
Q0
Q0#
Q19
Q19#
CLK_SEL
VEE
VEE
VEE
VEE
0
1
VEE
VBB
Q6
Q7
Q6#
Q7#
Q8
Q8#
Q9
Q9#
Q10
Q10#
Q11
Q11#
VCCO
Q0
Q1
Q0
#
Q1
#
Q2
Q2
#
Q3
Q3
#
Q4
Q4
#
Q5
Q5
#
VC
C
O
VCCO
CLK_SEL
VCC
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
Q19#
Q19
Q18#
Q18
VC
C
O
Q1
7
Q1
7
#
Q1
6
#
Q1
6
Q1
5
#
Q1
5
Q1
4
#
Q1
4
Q1
3
#
Q1
3
Q1
2
#
Q1
2
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
10
11
12
13
26
25
24
23
22
21
20
19
18
17
16
15
14
39
38
37
36
35
34
33
32
31
30
29
28
27
CY2DP3120
PRELIMINARY
FastEdgeTM Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 2 of 11
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3120. The agency name and relevant specification is
listed below.
Notes:
1.
In the I/O column, the following notation is used: I = Input, O = Output, PD = Pull-down, PU = Pull-up, PC = Pull Center, O = Output, OS = Open Source,
PWR = Power.
2.
in ECL mode (negative power supply mode), VEE is either 3.3V or 2.5V and VCC is connected to GND(0V). In PECL mode (positive power supply mode),
VEE is connected to GND(0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)
and are between VCC and VEE.
3.
VBB is available for use for single ended bias mode when VCC is +3.3V.
Pin Description
Pin
Name
I/O
Type
Description
4,5
CLKA, CLKA# I,PD
[1]
I,PC
ECL/PECL
Default differential clock input pair
7,8
CLKB, CLKB# I,PD
I,PC
HSTL
Alternate differential clock input pair
3
CLK_SEL
I,PD
ECL/PECL
CLK Mux select
52,50,48,46,44,42,39,3
7,35,33,31,29,26,24,22
,20,18,16,13,11
Q[0-19]
O,OS
ECL/PECL
True output
51,49,47,45,43,41,38,3
6,34,32,30,28,25,23,21
,19,17,15,12,10
Q#[0-19]
O,OS
ECL/PECL
Complement output
6
VBB
[3]
O
Bias
Reference voltage output for single-ended ECL or PECL
operation
9
VEE
[2]
-PWR
Power
Power supply, negative connection
2
VCC
+PWR
Power
Power supply, positive connection
1,14,27,40
VCCO
+PWR
Power
Power supply, positive connection
Agency Name
Specification
JEDEC
JESD 51 (Theta JA)
JESD 82 (ECL)
JESD 65A (Skew,Jitter)
JESD 8-6 (HSTL)
IEEE
1596.3 (Jitter Specs)
UL
94 (Moisture Grading)
MilSpec
883E Method 1012.1
(Thermal Theta JC)
PRELIMINARY
FastEdgeTM Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 3 of 11
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
V
cc
Supply Voltage
Non-functional
0.3
3.6
VDC
V
cc
Operating Voltage
Functional
2.5 5%
3.3 + 5%
VDC
V
BB
Output Reference Voltage
Relative to V
CC
V
CC
1.525
Vcc1.325
VDC
I
BB
Output Reference Current
Relative to V
BB
200
uA
V
TT
Output Termination Voltage
V
TT
= 0V for V
CC
= 2.5V
VCC2
VDC
V
IN
Input Voltage
Relative to V
CC
0.3
V
CC
+0.3
VDC
V
OUT
Output Voltage
Relative to V
CC
0.3
V
CC
+0.3
VDC
LU
I
Latch-up Immunity
Functional
300
mA
T
S
Temperature, Storage
Non-functional
65
+150
C
T
A
Temperature, Operating Ambient
Functional
40
+85
C
T
J
Temperature, Junction
Functional
10
+110
C
Jc
Dissipation, Junction to Case
Functional
TBD
C/W
Ja
Dissipation, Junction to Ambient
Functional
TBD
C/W
ESD
h
ESD Protection (Human Body Model)
2000
V
M
SL
Moisture Sensitivity Level
TBD
N.A.
G
ATES
Total Functional Gate Count
Assembled Die
50
Ea.
UL94
Flammability Rating
@1/8 in
V0
N.A.
FIT
Failure in Time
Manufacturing Test
TBD
PPM
PECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
V
IL
Input Voltage, Low
V
CC
1.945
V
CC
1.625
V
V
IH
Input Voltage, High
Define VCC and Load Current V
CC
1.165
V
CC
0.880
V
I
IN
Input Current
[4]
V
IN
= V
IL
or V
IN
= V
IH
200
uA
Clock input pair CLKA, CLKA#,CLKB, CLKB# (PECL Differential Signals)
V
PP
Differential Input Voltage
[5]
Differential Operation
0.1
1.3
V
V
CMR
Differential Cross Point Voltage
[6]
Differential Operation
1.2
V
CC
V
I
IN
Input Current
[4]
V
IN
= V
IL
or V
IN
= V
IH
200
uA
PECL Outputs Q0-Q19, (Q0-Q19)#(PECL Differential Signals)
V
OH
Output High Voltage
I
OH
= 30 mA
[9]
, 50
Load
V
CC
1.145
V
CC
0.895
V
V
OL
Output Low Voltage
V
CC
= 3.3V 5%V
CC
= 2.5V 5%
I
OL
= 5 ma
[9]
,50
Load
V
CC
1.945
V
CC
1.945
V
CC
1.695
V
CC
1.695
V
Clock Input Pair CLKA, CLKA#,CLKB, CLKB# (HSTL Differential Signals)
V
DIF
Differential Input Voltage
[7]
0.4
1.9
V
V
X
Differential Cross Point Voltage
[8]
0.68
0.9
V
I
IN
Input Current
Vin = Vx 0.2V
200
uA
Notes:
4.
Input have internal pullup / pulldown or biasing resistors which affect the input current.
5.
VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
6.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input
swing lies within the VPP (DC) specification.
7.
VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality.
8.
VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input
swing lies within the VPP (DC) specification.
9.
Equivalent to a termination of 50
to VTT.
PRELIMINARY
FastEdgeTM Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 4 of 11
Notes:
10. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH VTT)/Rload +
(VOL VTT)/Rload +IEE.
11. Input have internal pull-up/pull-down or biasing resistors which affect the input current.
12. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
13. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input
swing lies within the VPP (DC) specification.
14. Equivalent to a termination of 50
to VTT.
15. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH VTT)/Rload
+ (VOL VTT)/Rload +IEE.
Supply Current and VBB
I
EE
Maximum Quiescent Supply Current
without Output Termination Current
[10]
VEE Pin
130
mA
V
BB
Output Reference Voltage
I
BB
= 200 uA
V
CC
1.525
V
CC
1.325
V
I
pup
Internal Pull-up Current
TBD
TBD
mA.
I
pdwn
Internal Pull-down Current
TBD
TBD
mA.
C
IN
Input Pin Capacitance
TBD
TBD
pF
C
OUT
Output Pin Capacitance
Q0Q19, (Q0Q19)#
TBD
TBD
pF
L
IN
Pin Inductance
TBD
TBD
nH
Z
OUT
Output Impedance
Q0Q19, (Q0Q19)#
TBD
TBD
ECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
V
IL
Input Voltage, Low
1.945
1.625
V
V
IH
Input Voltage, High
1.165
0.880
V
I
IN
Input Current
[11]
V
IN
= V
IL
or V
IN
= V
IH
200
uA
Clock input pair CLKA, CLKA#,CLKB, CLKB# (ECL Differential Signals)
V
PP
Differential Input Voltage
[12]
Differential Operation
0.1
1.3
V
V
CMR
Differential Cross Point Voltage
[13]
Differential Operation
V
EE
+1.2
0
V
I
IN
Input Current
[11]
V
IN
= V
IL
or V
IN
= V
IH
200
uA
ECL Outputs Q0-Q19, (Q0-Q19)# (ECL Dfferential Signals)
V
OH
Output High Voltage
I
OH
= 30 mA
[14]
1.145
0.895
V
V
OL
Output Low Voltage
V
EE
= 3.3V 5%
V
EE
= 2.5V 5%
I
OL
= 5 ma
[14]
1.945
1.945
1.695
1.695
V
Supply Current and VBB
I
EE
Maximum Quiescent Supply Current
without Output Termination Current
[15]
V
EE
Pin
130
mA
V
BB
Output Reference Voltage
I
BB
= 200 uA
1.525
1.325
V
PECL DC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
PRELIMINARY
FastEdgeTM Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 5 of 11
Notes:
16. AC characteristics apply for parallel output termination of 50
to VTT.
17. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew.
18. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and
the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew.
19. The CY2DP3120 is fully operation up to 1.5 GHz.
20. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input
swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew.
21. Output pulse skew is the absolute difference of the propagation delay times: | tPLH tPHL |.
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Clock Input Pair CLKA, CLKA (PECL or ECL Differential Signals)
V
PP
Differential Input Voltage
[17]
Differential Operation
0.1
1.3
V
V
CMR
Differential Cross Point Voltage
[18]
Differential Operation
V
EE
+1.2 0
V
F
CLK
Input Frequency
[19]
50% Duty Cycle Standard Load
1,500
MHz
T
PD
Propagation Delay CLKA or CLKB to
Q0Q9 Pair
660 MHz 50% Duty Cycle
Standard Load Differential
Operation
400
750
ps
Clock Input Pair CLKB, CLKB (HSTL Differential Signals)
V
PP
Differential Input Voltage
[17]
Differential Operation
0.1
1.3
V
V
CMR
Differential Cross Point Voltage
[18]
Differential Operation
V
EE
+1.2 0
V
F
CLK
Input Frequency
[19]
50% Duty Cycle Standard Load
1,500
MHz
T
PD
Propagation Delay CLKA or CLKB to
Q0Q9 Pair
660 MHz 50% Duty Cycle
Standard Load Differential
Operation
400
750
ps
ECL/PECL Clock Outputs (Q019, Q#019) (Differential)
Vo
(P-P)
Differential Output Voltage
(Peak-to-Peak)
Differential PRBS
fo < 50 MHz
fo < 0.8 GHz
fo < 1.0 GHz
0.45
0.4
0.375
V
tsk
(O)
Output-to-Output skew
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
50
ps
tsk
(PP)
Output-to-output skew (part-to-part)
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
500
ps
T
jitt(cc)
Output cycle-to-cycle jitter (Intrinsic)
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
10
ps
r.m.s
tsk(P)
Output pulse skew
[21]
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
ps
T
F
, T
F
Output Rise/Fall time
660-MHz 50% Duty Cycle
Differential 20% to 80%
0.3
ns
TTB
Total Timing Budget
660-MHz 50% Duty Cycle
Standard Load
ps
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