128K x 36 Pipelined Sync SRAM

CY7C1347F

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05213 Rev. *B

Revised June 13, 2003

Features

· Fully registered inputs and outputs for pipelined

operation

· 128K by 36 common I/O architecture
· 3.3V core power supply
· 2.5V/3.3V I/O operation
· Fast clock-to-output times

-- 2.6 ns (for 250-MHz device)

-- 2.6 ns (for 225-MHz device)

-- 2.8 ns (for 200-MHz device)

-- 3.5 ns (for 166-MHz device)

-- 4.0 ns (for 133-MHz device)

-- 4.5 ns (for 100-MHz device)

· User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

· Separate processor and controller address strobes
· Synchronous self-timed writes
· Asynchronous output enable
· JEDEC-standard 100-pin TQFP, 119-pin BGA and

165-pin fBGA packages

· "ZZ" Sleep Mode option and Stop Clock option
· Available in Industrial and Commercial temperature

ranges

Functional Description

The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic.

CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V
level, the I/O pins are 3.3V tolerant when V

DDQ

= 2.5V.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250-MHz
device)

CY7C1347F supports either the interleaved burst sequence
used by the Intel Pentium processor or a linear burst sequence
used by processors such as the PowerPC

. The burst

sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Address Strobe from
Processor (ADSP) or the Address Strobe from Controller
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.

Byte write operations are qualified with the four Byte Write
Select (BW

[3:0]

) inputs. A Global Write Enable (GW) overrides

all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a read cycle when emerging from a deselected
state.

CLK

ADV

ADSC

[16:0]

BWE

BURST

COUNTER

ADDRESS

OUTPUT

REGISTERS

INPUT

REGISTERS

128KX36

MEMORY

ARRAY

CLK

CLR

SLEEP

CONTROL

[1;0]

)

MODE

ADSP

Logic Block Diagram

[31:0]

[3:0]

DQ[31:24], DP[3]

BYTEWRITE
REGISTERS

DQ[23:16], DP[2]

BYTEWRITE
REGISTERS

DQ[15:8], DP[1]

BYTEWRITE
REGISTERS

DQ[7:0], DP[0]

BYTEWRITE
REGISTERS

ENABLE CE

ENABLE DELAY

CY7C1347F

Document #: 38-05213 Rev. *B

Page 2 of 19

Selection Guide

-250

-225

-200

-166

-133

-100

Unit

Maximum Access Time

2.6

2.8

3.5

4.0

4.5

Maximum Operating Current

325

290

265

240

225

205

Maximum CMOS Standby Current

Pin Configurations

DDQ

SSQ

DDQ

NC
V

ZZ
DQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

CLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

BYTE0

BYTE1

BYTE3

BYTE2

100-Pin TQFP

CY7C1347F

CY7C1347F

Document #: 38-05213 Rev. *B

Page 3 of 19

Pin Configurations

(continued)

DDQ

DQP

ADSP

DDQ

CLK

DDQ

ADSC

ADV

DQP

MODE

DQP

BWE

119-Ball BGA

165-Ball fBGA

C
D

G
H

DQP

BWE

CE2

MODE

DDQ

CLK

DDQ

ADV

ADSC

ADSP

DDQ

DQP

DDQ

DQP

DDQ

CY7C1347F

Document #: 38-05213 Rev. *B

Page 4 of 19

Pin Definitions

Name

(BGA,FBGA)

Name

(100TQFP)

I/O

Description

A0
A1
A

[16:0]

Input-

Synchronous

Address Inputs used to select one of the 128K address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE

, and

are sampled active. A

[1:0]

feeds the 2-bit counter.

[3:0]

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW

[3:0]

and BWE).

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE

and CE

to select/deselect the device. ADSP is ignored if CE

is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A

[16:0]

is captured in the address registers. A

[1:0]

are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE

is deasserted HIGH.

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A

[16:0]

is captured in the address registers. A

[1:0]

are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.

Input-

Asynchronous

ZZ "sleep" Input. This active HIGH input places the device in a non-time-critical
"sleep" condition with data integrity preserved. For normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.

DQP

[31:0]

[3:0]

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A

[16:0]

during the previous clock rise of the read

cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ

[31:0]

and DP

[3:0]

are placed in a three-state

condition.

Power Supply

Power supply inputs to the core of the device.

Ground

Ground for the core of the device.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry.

SSQ

I/O Ground

Ground for the I/O circuitry.

MODE

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to V

DDQ

or left floating selects interleaved burst sequence. This is a strap pin and

should remain static during device operation. Mode Pin has an internal pull-up.

No Connects.

CY7C1347F

Document #: 38-05213 Rev. *B

Page 5 of 19

Introduction

Functional Overview

) is 2.6 ns

(250-MHz device).

The CY7C1347F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Address Strobe from Processor
(ADSP) or the Address Strobe from Controller (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW

[3:0]

) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE

, CE

are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE

is HIGH. The address presented to the address inputs (A

[16:0]

)

is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the Output Register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE

, CE

are all asserted active. The address presented

to A

[16:0]

is loaded into the Address Register and the address

advancement logic while being delivered to the RAM core. The

write signals (GW, BWE, and BW

[3:0]

) and ADV inputs are

ignored during this first cycle.

ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ

[31:0]

and DP

[3:0]

inputs is written into

the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW

[3:0]

signals. The CY7C1347F provides byte write

capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW

[3:0]

) input will selectively write to only the

desired bytes.

Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.

Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ

[31:0]

and DP

[3:0]

inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ

[31:0]

and DP

[3:0]

are

automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE

, CE

are all asserted active,

and (4) the appropriate combination of the write inputs (GW,
BWE, and BW

[3:0]

) are asserted active to conduct a write to

the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A

[16:0]

is loaded into the address register and the address

advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQ

[31:0]

and DP

[3:0]

written into the corresponding address location in the RAM
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.

Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ

[31:0]

and DP

[3:0]

inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ

[31:0]

and DP

[3:0]

are

automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.

Burst Sequences

The CY7C1347F provides a two-bit wraparound counter, fed
by A

[1:0]

, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.

Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY7C1347F

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY7C1347F