PRELIMINARY
256K x 36/512K x 18 Pipelined SRAM
with NoBLTM Architecture
CY7C1356BV25
CY7C1354BV25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05292 Rev. *A
Revised August 15, 2002
Features
Pin compatible and functionally equivalent to ZBT
Supports 250-MHz bus operations with zero wait states
-- Available speed grades are 250, 200 and 166 MHz
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Fully Registered (inputs and outputs) for pipelined
operation
Byte Write capability
Common I/O architecture
Single 2.5V power supply
Fast clock-to-output times
-- 2.6 ns (for 250-MHz device)
-- 3.0 ns (for 200-MHz device)
-- 3.5 ns (for 166-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP, 119 BGA, and 165 fBGA
Packages
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability--linear or interleaved burst order
"ZZ" Sleep Mode option and Stop Clock option
Functional Description
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous-Pipelined Burst SRAMs with
NoBLTM logic, respectively. They are designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1354BV25 and
CY7C1356BV25 are equipped with the advanced No Bus
LatencyTM (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1354BV25 and
CY7C1356BV25 are pin compatible and functionally equiv-
alent to ZBT
TM
devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).
Write operations are controlled by the Byte Write Selects
(BWS
a
BWS
d
for CY7C1354BV25 and BWS
a
BWS
b
for
CY7C1356BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CLK
A
x
CEN
WE
BWS
x
CE
1
CE
CE
2
OE
256KX36/
MEMORY
ARRAY
Logic Block Diagram
DQ
x
Data-In REG.
Q
D
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
Mode
DQP
x
CY7C1354
CY7C1356
A
X
DQ
X
DQP
X
BWS
X
512KX18
X = 17:0
X = 18:0
X = a, b, c, d
X = a, b
X = a, b
X = a, b
X = a, b, c, d
X = a, b, c, d
OU
TP
U
T
RE
GIS
TE
RS
and LOGIC
PRELIMINARY
CY7C1356BV25
CY7C1354BV25
Document #: 38-05292 Rev. *A
Page 2 of 25
Selection Guide
7C1354BV25-250
7C1356BV25-250
7C1354BV25-200
7C1356BV25-200
7C1354BV25-166
7C1356BV25-166
Unit
Maximum Access Time
2.6
3.0
3.5
ns
Maximum Operating Current
Com'l
250
220
180
mA
Maximum CMOS Standby Current
Com'l
30
30
30
mA
Pin Configurations
A
A
A
A
A
1
A
0
V
SS
V
DD
A
A
A
A
A
A
V
DDQ
V
SS
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
NC
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
V
SS
V
DDQ
V
DDQ
V
SS
DQc
DQc
V
SS
V
DDQ
DQc
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
V
SS
V
DDQ
A
A
CE
1
CE
2
BW
S
a
CE
3
V
DD
V
SS
CL
K
WE
CE
N
OE
E(1
8
)
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
AD
V/
L
D
ZZ
CY7C1354BV25
100-pin TQFP Packages
A
A
A
A
A
1
A
0
V
SS
V
DD
A
A
A
A
A
A
A
NC
NC
V
DDQ
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DDQ
NC
NC
NC
A
A
CE
1
CE
2
NC
NC
BWS
b
BWS
a
CE
3
V
DD
V
SS
CL
K
WE
CE
N
OE
E(
18
)
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
AD
V/L
D
ZZ
MO
DE
CY7C1356BV25
BW
S
d
MO
DE
BW
S
c
DQc
DQc
DQc
DQc
DQPc
DQd
DQd
QPd
DQd
DQPb
DQb
DQa
DQa
DQa
DQa
DQPa
DQb
DQb
(256K x 36)
(512K x 18)
BW
S
b
NC
NC
NC
DQc
NC
E
(
288)
E
(
144)
E(
72)
E(
3
6
)
E
(
2
88)
E
(
14
4)
E(
72
)
E(
3
6
)
PRELIMINARY
CY7C1356BV25
CY7C1354BV25
Document #: 38-05292 Rev. *A
Page 5 of 25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK.
BWS
a
BWS
b
BWS
c
BWS
d
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
a
controls DQ
a
and DQP
a
, BWS
b
controls DQ
b
and DQP
b
, BWS
c
controls DQ
c
and DQP
c
, BWS
d
controls DQ
d
and
DQP
d
.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new address.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device.
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a
DQ
d
are placed in
a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
DQP
a
DQP
b
DQP
c
DQP
d
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
[31:0]
. During write sequences, DQP
a
is controlled by BWS
a
, DQP
b
is controlled by
BWS
b
, DQP
c
is controlled by BWS
c
, and DQP
d
is controlled by BWS
d
.
MODE
Input
Strap Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
TCK
JTAG-Clock
Clock input to the JTAG circuitry.
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