/home/web/htmldatasheet/RUSSIAN/html/cypress/169530

8K x 8/9 Dual-Port Static RAM

with Sem, Int, Busy

fax id: 5205

CY7C145
CY7C144

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

November 1996

1CY 7C14 4

Features

· True Dual-Ported memory cells which allow

simultaneous reads of the same memory location

· 8K x 8 organization (CY7C144)
· 8K x 9 organization (CY7C145)
· 0.65-micron CMOS for optimum speed/power
· High-speed access: 15ns
· Low operating power: I

= 160 mA (max.)

· Fully asynchronous operation
· Automatic power-down
· TTL compatible
· Master/Slave select pin allows bus width expansion to

16/18 bits or more

· Busy arbitration scheme provided
· Semaphores included to permit software handshaking

between ports

· INT flag for port-to-port communication
· Available in 68-pin PLCC, 64-pin and 80-pin TQFP
· Pin compatible and functionally equivalent to

IDT7005/IDT7015

Functional Description

The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes

are included on the CY7C144/5 to handle situations when mul-
tiple processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5
can be utilized as a standalone 64/72-Kbit dual-port static
RAM or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 16/18-bit or wider mem-
ory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual-port video/graphics memory.

Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip enable (CE) pin or SEM pin.

Notes:

BUSY is an output in master mode and an input in slave mode.

Interrupt: push-pull output and requires no pull-up resistor.

C144-1

R/W

12L

12R

R/W

I/O

INTERRUPT

SEMAPHORE

ARBITRATION

CONTROL

I/O

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

SEM

BUSY

INT

M/S

(7C145) I/O

I/O

(7C145)

Logic Block Diagram

[1, 2]

[2]

CY7C145
CY7C144

Pin Configurations (continued)

9
10

52
51

80-Pin TQFP

Top View

I/O

GND

I/O

GND

BUSY

M/S

INT

I/O

CY7C145

BUSY

INT

C144-4

I/O

Pin Definitions

Left Port

Right Port

Description

I/O

7L(8L)

I/O

7R(8R)

Data bus Input/Output

12L

12R

Address Lines

Chip Enable

Output Enable

R/W

Read/Write Enable

SEM

Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O

pin is used when writing to a

semaphore. Semaphores are requested by writing a 0 into the respective
location.

INT

Interrupt Flag. INT

is set when right port writes location 1FFE and is

cleared when left port reads location 1FFE. INT

is set when left port writes

location 1FFF and is cleared when right port reads location 1FFF.

BUSY

Busy Flag

M/S

Master or Slave Select

Power

GND

Ground

CY7C145
CY7C144

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Storage Temperature

..................................... -

C to +150

Ambient Temperature with
Power Applied

.................................................. -

C to +125

Supply Voltage to Ground Potential

.................-

0.5V to +7.0V

DC Voltage Applied to Outputs
in High Z State

.....................................................-

0.5V to +7.0V

DC Input Voltage

[5]

..............................................-

0.5V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)

Latch-Up Current .................................................... >200 mA

Selection Guide

7C144-15
7C145-15

7C144-25
7C145-25

7C144-35
7C145-35

7C144-55
7C145-55

Maximum Access Time (ns)

Maximum Operating
Current (mA)

220

180

160

Maximum Standby
Current for I

SB1

(mA)

Operating Range

Range

Ambient

Temperature

Commercial

C to +70

10%

Industrial

C to +85

10%

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

7C144-15
7C145-15

7C144-25
7C145-25

Unit

Min.

Max.

Min.

Max.

Output HIGH Voltage

= Min., I

4.0 mA

2.4

Output LOW Voltage

= Min., I

= 4.0 mA

0.4

Input HIGH Voltage

2.2

Input LOW Voltage

0.8

Input Leakage Current

GND < V

< V

+10

Output Leakage Current

Outputs Disabled, GND < V

< V

+10

Operating Current

= Max., I

OUT

= 0 mA

Outputs Disabled

Com'l

220

180

Ind

190

SB1

Standby Current
(Both Ports TTL Levels)

and CE

> V

f = f

MAX

[7]

Com'l

Ind

SB2

Standby Current
(One Port TTL Level)

or CE

> V

f = f

MAX

[7]

Com'l

130

110

Ind

120

SB3

Standby Current
(Both Ports CMOS Levels)

Both Ports
CE and CE

> V

0.2V,

> V

0.2V

or V

< 0.2V, f = 0

[7]

Com'l

Ind

SB4

Standby Current
(One Port CMOS Level)

One Port
CE

or CE

> V

0.2V,

> V

0.2V or

< 0.2V, Active

Port Outputs, f = f

MAX

[7]

Com'l

125

100

Ind

115

Notes:

Pulse width < 20 ns.

is the "instant on" case temperature.

MAX

= 1/t

= All inputs cycling at f = 1/t

(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS

level standby I

SB3

CY7C145
CY7C144

]

Electrical Characteristics

Over the Operating Range (continued)

Parameter

Description

Test Conditions

7C144-35
7C145-35

7C144-55
7C145-55

Unit

Min.

Max.

Min.

Max.

Output HIGH Voltage

= Min., I

4.0 mA

2.4

Output LOW Voltage

= Min., I

= 4.0 mA

0.4

Input HIGH Voltage

2.2

Input LOW Voltage

0.8

Input Leakage Current

GND < V

< V

+10

Output Leakage Current

Outputs Disabled, GND < V

< V

+10

Operating Current

= Max., I

OUT

= 0 mA

Outputs Disabled

Com'l

160

Ind

180

SB1

Standby Current
(Both Ports TTL Levels)

and CE

> V

f = f

MAX

[7]

Com'l

Ind

SB2

Standby Current
(One Port TTL Level)

or CE

> V

f = f

MAX

[7]

Com'l

100

Ind

110

SB3

Standby Current
(Both Ports CMOS Levels)

Both Ports
CE and CE

> V

0.2V,

> V

0.2V

or V

< 0.2V, f = 0

[7]

Com'l

Ind

SB4

Standby Current
(One Port CMOS Level)

One Port
CE

or CE

> V

0.2V,

> V

0.2V or

< 0.2V, Active

Port Outputs, f = f

MAX

[7]

Com'l

Ind

100

Capacitance

[8]

Parameter

Description

Test Conditions

Max.

Unit

Input Capacitance

= 25

C, f = 1 MHz,

= 5.0V

OUT

Output Capacitance

Note:

Tested initially and after any design or process changes that may affect these parameters.

CY7C145
CY7C144

AC Test Loads and Waveforms

3.0V

GND

90%

10%

3 ns

10%

ALL INPUT PULSES

(a) Normal Load (Load1)

OUTPUT

C = 30 pF

=1.4V

OUTPUT

C=30pF

(b) Th évenin Equivalent (Load 1)

(c) Three-State Delay (Load 3)

C = 30 pF

OUTPUT

Load (Load 2)

C144-5

C144-6

C144-7

C144-8

C144-9

OUTPUT

C = 5 pF

R1=893

R2=347

=250

R1=893

R2=347

Switching Characteristics

Over the Operating Range

[9]

7C144-15
7C145-15

7C144-25
7C145-25

7C144-35
7C145-35

7C144-55
7C145-55

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

Read Cycle Time

Address to Data Valid

OHA

Output Hold From Address
Change

ACE

CE LOW to Data Valid

DOE

OE LOW to Data Valid

LZOE

[10, 11,12]

OE Low to Low Z

HZOE

[10, 11,12]

OE HIGH to High Z

LZCE

[10, 11,12]

CE LOW to Low Z

HZCE

[10, 11,12]

CE HIGH to High Z

[12]

CE LOW to Power-Up

[12]

CE HIGH to Power-Down

Notes:

Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

and 30-pF load capacitance.

10. At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

11.

Test conditions used are Load 3.

12. This parameter is guaranteed but not tested.

CY7C145
CY7C144

WRITE CYCLE

Write Cycle Time

SCE

CE LOW to Write End

Address Set-Up to Write End

Address Hold From Write
End

Address Set-Up to Write
Start

PWE

Write Pulse Width

Data Set-Up to Write End

Data Hold From Write End

HZWE

[11,12]

R/W LOW to High Z

LZWE

[11,12]

R/W HIGH to Low Z

WDD

[13]

Write Pulse to Data Delay

DDD

[13]

Write Data Valid to Read
Data Valid

BUSY TIMING

[14]

BLA

BUSY LOW from Address
Match

BHA

BUSY HIGH from Address
Mismatch

BLC

BUSY LOW from CE LOW

BHC

BUSY HIGH from CE HIGH

Port Set-Up for Priority

R/W LOW after BUSY LOW

R/W HIGH after BUSY HIGH

BDD

BUSY HIGH to Data Valid

INTERRUPT TIMING

[14]

INS

INT Set Time

INR

INT Reset Time

SEMAPHORE TIMING

SOP

SEM Flag Update Pulse (OE
or SEM)

SWRD

SEM Flag Write to Read Time

SPS

SEM Flag Contention
Window

Notes:

13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.

Switching Characteristics

Over the Operating Range

[9]

(continued)

7C144-15
7C145-15

7C144-25
7C145-25

7C144-35
7C145-35

7C144-55
7C145-55

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CY7C145
CY7C144

Write Cycle No. 1: OE Three-State Data I/Os (Either Port)

[21, 22, 23]

Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)

[21, 23, 24]

Notes:

21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either

signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates
the write.

22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t

PWE

or (t

HZWE

+ t

) to allow the I/O drivers to turn off and

data to be placed on the bus for the required t

. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply

and the write pulse can be as short as the specified t

PWE

23. R/W must be HIGH during all address transitions.
24. Data I/O pins enter high impedance when OE is held LOW during write.

Switching Waveforms (continued)

C144-13

DATA VALID

HIGH IMPEDANCE

SCE

PWE

HZOE

LZOE

SEM OR CE

R/W

ADDRESS

DATA OUT

DATA IN

SCE

PWE

HZWE

HIGH IMPEDANCE

SEM OR CE

R/W

ADDRESS

DATA OUT

DATA IN

LZWE

DATAVALID

C144-14

CY7C145
CY7C144

Architecture

The CY7C144/5 consists of a an array of 8K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit indepen-
dent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a
BUSY pin is provided on each port. Two interrupt (INT) pins
can be utilized for port-to-port communication. Two sema-
phore (SEM) control pins are used for allocating shared re-
sources. With the M/S pin, the CY7C144/5 can function as
a Master (BUSY pins are outputs) or as a slave (BUSY pins
are inputs). The CY7C144/5 has an automatic power-down
feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read
from the device.

Functional Description

Write Operation

Data must be set up for a duration of t

before the rising

edge of R/W in order to guarantee a valid write. A write op-
eration is controlled by either the OE pin (see Write Cycle
No.1 waveform) or the R/W pin (see Write Cycle No. 2 wave-
form). Data can be written to the device t

HZOE

after the OE

is deasserted or t

HZWE

after the falling edge of R/W. Re-

quired inputs for non-contention operations are summarized
in

Table 1.

If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; oth-
erwise the data read is not deterministic. Data will be valid on
the port t

DDD

after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE
and CE pins. Data will be available t

ACE

after CE or t

DOE

after

OE are asserted. If the user of the CY7C144/5 wishes to ac-
cess a semaphore flag, then the SEM pin must be asserted
instead of the CE pin.

Interrupts

The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port's inter-
rupt flag (INT

) is set. This flag is cleared when the right port reads

that same location. Setting the left port's interrupt flag (INT

) is accom-

plished when the right port writes to location 1FFE. This flag is cleared
when the left port reads location 1FFE. The message at 1FFF or
1FFE is user-defined. See

Table 2 for input requirements for INT.

INT

and INT

are push-pull outputs and do not require pull-up resis-

tors to operate.

Busy

The CY7C144/5 provides on-chip arbitration to alleviate simul-
taneous memory location access (contention). If both ports'
CEs are asserted and an address match occurs within t

of each

other the Busy logic will determine which port has access. If t

violated, one port will definitely gain permission to the location, but it
is not guaranteed which one. BUSY will be asserted t

BLA

after an

address match or t

BLC

after CE is taken LOW. BUSY

and BUSY

in master mode are push-pull outputs and do not require pull-up re-
sistors to operate.

Master/Slave

An M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external compo-
nents.Writing of slave devices must be delayed until after the BUSY
input has settled. Otherwise, the slave chip may begin a write cycle
during a contention situation.When presented a HIGH input, the M/S
pin allows the device to be used as a master and therefore the BUSY
line is an output. BUSY can then be used to send the arbitration out-
come to a slave.

Semaphore Operation

The CY7C144/5 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for t

SOP

before attempting to read the semaphore. The

semaphore value will be available t

SWRD

+ t

DOE

after the rising edge

of the semaphore write. If the left port was successful (reads a 0), it
assumes control over the shared resource, otherwise (reads a 1) it
assumes the right port has control and continues to poll the sema-
phore.When the right side has relinquished control of the semaphore
(by writing a 1), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore, a 1 is
written to cancel its request.

Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE must
remain HIGH during SEM LOW). A

represents the semaphore

address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other ad-
dress pins have no effect.

When writing to the semaphore, only I/O

is used. If a 0 is written

to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the left
port now relinquishes control by writing a 1 to the semaphore, the
semaphore will be set to 1 for both sides. However, if the right port
had requested the semaphore (written a 0) while the left port had
control, the right port would immediately own the semaphore as soon
as the left port released it.

Table 3 shows sample semaphore oper-

ations.

When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within t

SPS

of each other, the semaphore will definitely

be obtained by one side or the other, but there is no guarantee which
side will control the semaphore.

Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All Sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.

CY7C145
CY7C144

Table 1. Non-Contending Read/Write.

Inputs

Outputs

R/W

SEM

I/O

7/8

Operation

High Z

Power-Down

Data Out

Read Data in
Semaphore

High Z

I/O Lines Disabled

Data In

Write to Semaphore

Data Out

Read

Data In

Write

Illegal Condition

Table 2. Interrupt Operation Example (assumes BUSY

=BUSY

=HIGH).

Left Port

Right Port

Function

R/W

INT

R/W

INT

Set Left INT

1FFE

Reset Left INT

1FFE

Set Right INT

1FFF

Reset Right INT

1FFF

Table 3. Semaphore Operation Example.

Function

I/O

0-7/8

Left

I/O

0-7/8

Right

Status

No action

Semaphore free

Left port writes semaphore

Left port obtains semaphore

Right port writes 0 to semaphore

Right side is denied access

Left port writes 1 to semaphore

Right port is granted access to semaphore

Left port writes 0 to semaphore

No change. Left port is denied access

Right port writes 1 to semaphore

Left port obtains semaphore

Left port writes 1 to semaphore

No port accessing semaphore address

Right port writes 0 to semaphore

Right port obtains semaphore

Right port writes 1 to semaphore

No port accessing semaphore

Left port writes 0 to semaphore

Left port obtains semaphore

Left port writes 1 to semaphore

No port accessing semaphore

CY7C145
CY7C144

Typical DC and AC Characteristics

1.4

1.0

0.4

4.0

4.5

5.0

5.5

6.0

125

1.2

1.0

120

1.0

2.0

3.0

4.0

SUPPLY VOLTAGE (V)

NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE

0.0

0.8

0.6

=5.0V

1.6

1.4

1.2

1.0

0.8

125

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

1.4

1.3

1.2

1.0

0.9

4.0

4.5

5.0

5.5

6.0

SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

120

140

100

0.0

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

=5.0V

=25°C

0.6

0.8

=5.0V

=25°C

1.25

1.0

0.75

0.50

NORMALIZED I

vs. CYCLE TIME

CYCLE FREQUENCY (MHz)

25.0

30.0

20.0

10.0

5.0

200

400

600

800

15.0

SUPPLY VOLTAGE (V)

TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE

CAPACITANCE (pF)

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING

1000

0.2

0.6

1.2

SB3

0.2

0.4

SB3

1.1

=4.5V

=25°C

=5.0V

=25°C

=0.5V

5.0

=5.0V

=25°C

160

200

5.0

1.00

0.25

1.0

2.0

3.0

5.0

0.0

4.0

0.50

0.75

CY7C145
CY7C144

8K x9 Dual-Port SRAM

Ordering Information

8K x8 Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C144-15AC

A65

64-Lead Thin Quad Flat Pack

Commercial

CY7C144-15JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C144-25AC

A65

64-Lead Thin Quad Flat Pack

Commercial

CY7C144-25JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C144-25AI

A65

64-Lead Thin Quad Flat Pack

Industrial

CY7C144-25JI

J81

68-Lead Plastic Leaded Chip Carrier

CY7C144-35AC

A65

64-Lead Thin Quad Flat Pack

Commercial

CY7C144-35JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C144-35AI

A65

64-Lead Thin Quad Flat Pack

Industrial

CY7C144-35JI

J81

68-Lead Plastic Leaded Chip Carrier

CY7C144-55AC

A65

64-Lead Thin Quad Flat Pack

Commercial

CY7C144-55JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C144-55AI

A65

64-Lead Thin Quad Flat Pack

Industrial

CY7C144-55JI

J81

68-Lead Plastic Leaded Chip Carrier

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C145-15AC

A80

80-Lead Thin Quad Flat Pack

Commercial

CY7C145-15JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C145-25AC

A80

80-Lead Thin Quad Flat Pack

Commercial

CY7C145-25JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C145-25AI

A80

80-Lead Thin Quad Flat Pack

Industrial

CY7C145-25JI

J81

68-Lead Plastic Leaded Chip Carrier

CY7C145-35AC

A80

80-Lead Thin Quad Flat Pack

Commercial

CY7C145-35JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C145-35AI

A80

80-Lead Thin Quad Flat Pack

Industrial

CY7C145-35JI

J81

68-Lead Plastic Leaded Chip Carrier

CY7C145-55AC

A80

80-Lead Thin Quad Flat Pack

Commercial

CY7C145-55JC

J81

68-Lead Plastic Leaded Chip Carrier

CY7C145-55AI

A80

80-Lead Thin Quad Flat Pack

Industrial

CY7C145-55JI

J81

68-Lead Plastic Leaded Chip Carrier

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY7C145

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY7C145