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PRELIMINARY

72-Mbit QDRTM-II SRAM 4-Word Burst

Architecture

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05363 Rev. *A

Revised August 11, 2004

Features

· Separate Independent Read and Write Data Ports

-- Supports concurrent transactions

· 250-MHz Clock for High Bandwidth
· 4-Word Burst for reducing address bus frequency
· Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 500 MHz) at 250 MHz

· Two input clocks (K and K) for precise DDR timing

-- SRAM uses rising edges only

· Two output clocks (C and C) accounts for clock skew

and flight time mismatching

· Echo clocks (CQ and CQ) simplify data capture in high

speed systems

· Single multiplexed address input bus latches address

inputs for both Read and Write ports

· Separate Port Selects for depth expansion
· Synchronous internally self-timed writes
· Available in ×8,x9, ×18, and ×36 configurations
· Full data coherency providing most current data
· Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)
· 15 × 17 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball

(11 × 15 matrix)

· Variable drive HSTL output buffers
· JTAG 1149.1 Compatible test access port
· Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1511V188M x 8
CY7C1526V188M x 9
CY7C1513V184M x 18
CY7C1515V182M x 36

Functional Description

The CY7C1511V18, CY7C1526V18, CY7C1513V18, and

CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to "turn-around" the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR-II Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 8-bit words (CY7C1511V18) or 9-bit

words (CY7C1526V18) or 18-bit words (CY7C1513V18) or

36-bit words (CY7C1515V18) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K and

K and C and C), memory bandwidth is maximized while simpli-

fying system design by eliminating bus "turn-arounds".
Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

PRELIMINARY

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Document #: 38-05363 Rev. *A

Page 3 of 23

Logic Block Diagram (CY7C1513V18)

1M x 18

r
a

CLK

(19:0)

Gen.

Control

Logic

Address

[17:0]

d. D

e
c
o
d
e

Read Data Reg.

RPS

WPS

[17:0]

Control

Logic

Address

Reg.

BWS

[1:0]

REF

r
ite A

d
d
.
De

Write

Reg

(19:0)

1M x 18

r
a

1M x 18

r
a

1M x 18

r
a

Write

Reg

Write

Reg

Write

Reg

DOFF

Logic Block Diagram (CY7C1515V18)

512

x 36 Ar

r
a

CLK

(18:0)

Gen.

Control

Logic

Address

[35:0]

d
.
D

e
c
o
de

Read Data Reg.

RPS

WPS

[35:0]

Control

Logic

Address

Reg.

144

BWS

[3:0]

REF

r
i
t
e Ad

Dec

ode

Write

Reg

(18:0)

512

x 36 Ar

r
a

512

x 36 Ar

r
a

512

x 36 Ar

r
a

Write

Reg

Write

Reg

Write

Reg

DOFF

Selection Guide

250 MHz

200 MHz

167 MHz

Unit

Maximum Operating Frequency

250

200

167

MHz

Maximum Operating Current

TBD

PRELIMINARY

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Document #: 38-05363 Rev. *A

Page 4 of 23

Pin Configurations

CY7C1511V18 (8M × 8)15 × 17 FBGA

A
B
C
D

G
H

NC
NC
NC

DOFF

NWS

WPS

NC/144M

TDO

TCK

A NC/288M

NWS

DDQ

NC
NC

DDQ

REF

RPS

A NC

REF

DDQ

TDI

TMS

CY7C1526V18 (8M × 9)15 × 17 FBGA

A
B
C
D
E

N
P
R

CQ
NC
NC
NC

DOFF

NC K

WPS

NC/144M

TDO

TCK

A NC/288M

BWS

DDQ

NC
NC

DDQ

REF

RPS

A NC

REF

DDQ

TDI

TMS

PRELIMINARY

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Document #: 38-05363 Rev. *A

Page 5 of 23

Pin Configurations

(continued)

CY7C1513V18 (4M × 18)15 × 17 FBGA

A
B
C
D

G
H

CQ
NC
NC
NC

DOFF

/144M

BWS

WPS

NC/288M

TDO

D13

TCK

D10

A NC

BWS

Q10

Q11
D12

DDQ

D14

Q14

D16

Q16
Q17

DDQ

Q13

DDQ

D11

Q12

REF

Q15

D17

D15

RPS

A NC

REF

DDQ

TDI

TMS

A
B
C
D

E
F

Q27

D27
D28

D34

DOFF

Q33

/288M

BWS

WPS

BWS

Q18

D18

Q30

D31

D33

TDO

Q28

D29

D22

D32

Q34

Q31

TCK

D35

D19

BWS

Q19

Q20
D21

DDQ

D23
Q23

D25
Q25
Q26

DDQ

Q22

DDQ

D20

Q29

Q21

D30

REF

Q32

Q24

Q35

D26

D24

/144M

RPS

A D17

Q17

D16

Q16

D15

Q14

REF

Q11

DDQ

Q15

DDQ

D14

DDQ

D12

Q12

DDQ

D11

D10

Q10

TDI

TMS

D13

Q13

CY7C1515AV18 (2M × 36)15 × 17FBGA

PRELIMINARY

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Document #: 38-05363 Rev. *A

Page 6 of 23

Pin Definitions

Pin Name

I/O

Pin Description

[x:0]

Input-

Synchronous

Data input signals, sampled on the rising edge of K and K clocks during valid write opera-

tions.

CY7C1511V18

- D

[7:0]

CY7C1526V18

- D

[8:0]

CY7C1513V18

- D

[17:0]

CY7C1515V18

- D

[35:0]

WPS

Input-

Synchronous

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,

a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port

will cause D

[x:0]

to be ignored.

NWS

,NWS

Input-

Synchronous

Nibble Write Select 0, 1

- active LOW.(CY7C1511V18 Only) Sampled on the rising edge of the

K and K clocks during write operations. Used to select which nibble is written into the device

NWS

controls D

[3:0]

and NWS

controls D

[7:4]

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble

Write Select will cause the corresponding nibble of data to be ignored and not written into the

device.

BWS

, BWS

BWS

, BWS

Input-

Synchronous

Byte Write Select 0, 1, 2 and 3

- active LOW. Sampled on the rising edge of the K and K clocks

during write operations. Used to select which byte is written into the device during the current

portion of the write operations. Bytes not written remain unaltered.

CY7C1526V18

- BWS

controls D

[8:0]

CY7C1513V18

- BWS

controls D

[8:0]

and BWS

controls D

[17:9].

CY7C1515V18

- BWS

controls D

[8:0]

, BWS

controls D

[17:9]

, BWS

controls D

[26:18]

and BWS

controls D

[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write

Select will cause the corresponding byte of data to be ignored and not written into the device.

Input-

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-

tions. These address inputs are multiplexed for both Read and Write operations. Internally, the

device is organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C1511V18, 8M x 9 (4 arrays each

of 2M x 9) for CY7C1526V18,4M x 18 (4 arrays each of 1M x 18) for CY7C1513V18 and 2M x

36 (4 arrays each of 512K x 36) for CY7C1515V18. Therefore, only 21 address inputs are needed

to access the entire memory array of CY7C1511V18 and CY7C1526V18, 20 address inputs for

CY7C1513V18 and 19 address inputs for CY7C1515V18.These inputs are ignored when the

appropriate port is deselected.

[x:0]

Outputs-

Synchronous

Data Output signals. These pins drive out the requested data during a Read operation. Valid

data is driven out on the rising edge of both the C and C clocks during Read operations or K and

K. when in single clock mode. When the Read port is deselected, Q

[x:0]

are automatically

tri-stated.

CY7C1511V18

- Q

[7:0]

CY7C1526V18

- Q

[8:0]

CY7C1513V18

- Q

[17:0]

CY7C1515V18

- Q

[35:0]

RPS

Input-

Synchronous

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When

active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When

deselected, the pending access is allowed to complete and the output drivers are automatically

tri-stated following the next rising edge of the C clock. Each read access consists of a burst of

four sequential transfers.

Input-

Clock

Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from

the device. C and C can be used together to deskew the flight times of various devices on the

board back to the controller. See application example for further details.

Input-

Clock

Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from

the device. C and C can be used together to deskew the flight times of various devices on the

board back to the controller. See application example for further details.

Input-

Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

device and to drive out data through Q

[x:0]

when in single clock mode. All accesses are initiated

on the rising edge of K.

Input-

Clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the

device and to drive out data through Q

[x:0]

when in single clock mode.

PRELIMINARY

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Document #: 38-05363 Rev. *A

Page 7 of 23

Functional Overview

The CY7C1511V18, CY7C1526V18, CY7C1513V18/,

CY7C1515V18 are synchronous pipelined Burst SRAMs

equipped with both a Read Port and a Write Port. The Read

port is dedicated to Read operations and the Write Port is

dedicated to Write operations. Data flows into the SRAM

through the Write port and out through the Read Port. These

devices multiplex the address inputs in order to minimize the

number of address pins required. By having separate Read

and Write ports, the QDR-II completely eliminates the need to

"turn-around" the data bus and avoids any possible data

contention, thereby simplifying system design. Each access

consists of four 8-bit data transfers in the case of

CY7C1511V18, four 9-bit data transfers in the case of

CY7C1526V18, four 18-bit data transfers in the case of

CY7C1513V18, and four 36-bit data in the case of

CY7C1515V18 transfers in two clock cycles.
Accesses for both ports are initiated on the Positive Input

Clock (K). All synchronous input timing is referenced from the

rising edge of the input clocks (K and K) and all output timing

is referenced to the output clocks (C and C or K and K when

in single clock mode).
All synchronous data inputs (D

[x:0]

) inputs pass through input

registers controlled by the input clocks (K and K). All

synchronous data outputs (Q

[x:0]

) outputs pass through output

registers controlled by the rising edge of the output clocks (C

and C or K and K when in single-clock mode).

All synchronous control (RPS, WPS, BWS

[x:0]

) inputs pass

through input registers controlled by the rising edge of the

input clocks (K and K).
CY7C1513V18 is described in the following sections. The

same basic descriptions apply to CY7C1511V18,

CY7C1526V18 and CY7C1515V18.

Read Operations
The CY7C1513V18 is organized internally as 4 arrays of 1M x

18. Accesses are completed in a burst of four sequential 18-bit

data words. Read operations are initiated by asserting RPS

active at the rising edge of the Positive Input Clock (K). The

address presented to Address inputs are stored in the Read

address register. Following the next K clock rise, the corre-

sponding lowest order 18-bit word of data is driven onto the

[17:0]

using C as the output timing reference. On the subse-

quent rising edge of C the next 18-bit data word is driven onto

the Q

[17:0]

. This process continues until all four 18-bit data

words have been driven out onto Q

[17:0]

. The requested data

will be valid 0.45 ns from the rising edge of the output clock (C

or C or (K or K when in single-clock mode)). In order to

maintain the internal logic, each read access must be allowed

to complete. Each Read access consists of four 18-bit data

words and takes 2 clock cycles to complete. Therefore, Read

accesses to the device can not be initiated on two consecutive

K clock rises. The internal logic of the device will ignore the

second Read request. Read accesses can be initiated on

every other K clock rise. Doing so will pipeline the data flow

Echo Clock

CQ is referenced with respect to C. This is a free running clock and is synchronized to the

output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The

timings for the echo clocks are shown in the AC timing table.

Echo Clock

CQ is referenced with respect to C. This is a free running clock and is synchronized to the

output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The

timings for the echo clocks are shown in the AC timing table.

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system

data bus impedance. CQ,CQ and Q

[x:0]

output impedance are set to 0.2 x RQ, where RQ is a

resistor connected between ZQ and ground. Alternately, this pin can be connected directly to

, which enables the minimum impedance mode. This pin cannot be connected directly to

GND or left unconnected.

DOFF

Input

DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside the device.

The timings in the DLL turned off operation will be different from those listed in this data sheet.

More details on this operation can be found in the application note, "DLL Operation in the QDR-II."

TDO

Output

TDO for JTAG.

TCK

Input

TCK pin for JTAG.

TDI

Input

TDI pin for JTAG.

TMS

Input

TMS pin for JTAG.

N/A

Not connected to the die. Can be tied to any voltage level.

/144M

Input

Address expansion for 144M. This must be tied LOW on the these devices.

/288M

Input

Address expansion for 288M. This must be tied LOW on the these devices.

REF

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs

as well as AC measurement points.

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the device.

DDQ

Power Supply Power supply inputs for the outputs of the device.

Pin Definitions

(continued)

Pin Name

I/O

Pin Description

PRELIMINARY

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Document #: 38-05363 Rev. *A

Page 8 of 23

such that data is transferred out of the device on every rising

edge of the output clocks (C and C or K and K when in

single-clock mode).
When the read port is deselected, the CY7C1513V18 will first

complete the pending read transactions. Synchronous internal

circuitry will automatically tri-state the outputs following the

next rising edge of the Positive Output Clock (C). This will

allow for a seamless transition between devices without the

insertion of wait states in a depth expanded memory.

Write Operations
Write operations are initiated by asserting WPS active at the

rising edge of the Positive Input Clock (K). On the following K

clock rise the data presented to D

[17:0]

is latched and stored

into the lower 18-bit Write Data register, provided BWS

[1:0]

are

both asserted active. On the subsequent rising edge of the

Negative Input Clock (K) the information presented to D

[17:0]

is also stored into the Write Data Register, provided BWS

[1:0]

are both asserted active. This process continues for one more

cycle until four 18-bit words (a total of 72 bits) of data are

stored in the SRAM. The 72 bits of data are then written into

the memory array at the specified location. Therefore, Write

accesses to the device can not be initiated on two consecutive

K clock rises. The internal logic of the device will ignore the

second Write request. Write accesses can be initiated on

every other rising edge of the Positive Input Clock (K). Doing

so will pipeline the data flow such that 18 bits of data can be

transferred into the device on every rising edge of the input

clocks (K and K).
When deselected, the write port will ignore all inputs after the

pending Write operations have been completed.

Byte Write Operations
Byte Write operations are supported by the CY7C1513V18. A

write operation is initiated as described in the Write Operation

section above. The bytes that are written are determined by

BWS

and BWS

, which are sampled with each set of 18-bit

data words. Asserting the appropriate Byte Write Select input

during the data portion of a write will allow the data being

presented to be latched and written into the device.

Deasserting the Byte Write Select input during the data portion

of a write will allow the data stored in the device for that byte

to remain unaltered. This feature can be used to simplify

Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode
The CY7C1513V18 can be used with a single clock that

controls both the input and output registers. In this mode the

device will recognize only a single pair of input clocks (K and

K) that control both the input and output registers. This

operation is identical to the operation if the device had zero

skew between the K/K and C/C clocks. All timing parameters

remain the same in this mode. To use this mode of operation,

the user must tie C and C HIGH at power on. This function is

a strap option and not alterable during device operation.

Concurrent Transactions
The Read and Write ports on the CY7C1513V18 operate

completely independently of one another. Since each port

latches the address inputs on different clock edges, the user

can Read or Write to any location, regardless of the trans-

action on the other port. If the ports access the same location

when a read follows a write in successive clock cycles, the

SRAM will deliver the most recent information associated with

the specified address location. This includes forwarding data

from a Write cycle that was initiated on the previous K clock

rise.
Read accesses and Write access must be scheduled such that

one transaction is initiated on any clock cycle. If both ports are

selected on the same K clock rise, the arbitration depends on

the previous state of the SRAM. If both ports were deselected,

the Read port will take priority. If a Read was initiated on the

previous cycle, the Write port will assume priority (since Read

operations can not be initiated on consecutive cycles). If a

Write was initiated on the previous cycle, the Read port will

assume priority (since Write operations can not be initiated on

consecutive cycles). Therefore, asserting both port selects

active from a deselected state will result in alternating

Read/Write operations being initiated, with the first access

being a Read.

Depth Expansion
The CY7C1513V18 has a Port Select input for each port. This

allows for easy depth expansion. Both Port Selects are

sampled on the rising edge of the Positive Input Clock only (K).

Each port select input can deselect the specified port.

Deselecting a port will not affect the other port. All pending

transactions (Read and Write) will be completed prior to the

device being deselected.

Programmable Impedance
An external resistor, RQ, must be connected between the ZQ

pin on the SRAM and V

to allow the SRAM to adjust its

output driver impedance. The value of RQ must be 5X the

value of the intended line impedance driven by the SRAM, The

allowable range of RQ to guarantee impedance matching with

a tolerance of ±15% is between 175

and 350

with

DDQ

= 1.5V. The output impedance is adjusted every 1024

cycles upon powerup to account for drifts in supply voltage and

temperature.

Echo Clocks
Echo clocks are provided on the QDR-II to simplify data

capture on high speed systems. Two echo clocks are

generated by the QDR-II. CQ is referenced with respect to C

and CQ is referenced with respect to C. These are free running

clocks and are synchronized to the output clock of the QDR-II.

In the single clock mode, CQ is generated with respect to K

and CQ is generated with respect to K. The timings for the

echo clocks are shown in the AC timing table.

DLL
These chips utilize a Delay Lock Loop (DLL) that is designed

to function between 80 MHz and the specified maximum clock

frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time

of input clocks K and K to greater than 30 ns.

PRELIMINARY

CY7C1513V18

CY7C1526V18

CY7C1511V18

CY7C1515V18

Document #: 38-05363 Rev. *A

Page 9 of 23

Application Example

[1]

Truth Table

[ 2, 3, 4, 5, 6, 7]

Operation

RPS

WPS

Write Cycle:

Load address on the rising

edge of K; input write data on

two consecutive K and K

rising edges.

L-H

[8]

[9]

D(A) at

K(t+1)

D(A + 1) at

K(t+1)

D(A + 2) at K(t

+ 2)

D(A + 3) at

K(t +2)

Read Cycle:

Load address on the rising

edge of K; wait one and a

half cycle; read data on two

consecutive C and C rising

edges.

L-H

[9]

Q(A) at

C(t +1)

Q(A + 1) at

C(t + 2)

Q(A + 2) at C(t

+ 2)

Q(A + 3) at C(t

+ 3)

NOP: No Operation

L-H

D=X

Q=High-Z

D=X

Q=High-Z

D=X

Q=High-Z

D=X

Q=High-Z

Standby: Clock Stopped

Stopped

Previous State Previous State Previous

State

Previous State

Write Cycle Descriptions

CY7C1511V18 and CY7C1526V18)

[2, 10]

BWS

/NWS

BWS

/NWS

Comments

During the Data portion of a Write sequence

CY7C1511V18

- both nibbles (D

[7:0]

) are written into the device,

CY7C1513V18

- both bytes (D

[17:0]

) are written into the device.

L-H During the Data portion of a Write sequence

CY7C1511V18

- both nibbles (D

[7:0]

) are written into the device,

CY7C1513V18

- both bytes (D

[17:0]

) are written into the device.

Notes:

1. The above application shows four QDRII being used.
2. X = "Don't Care," H = Logic HIGH, L = Logic LOW,

represents rising edge.

3. Device will power-up deselected and the outputs in a tri-state condition.
4. "A" represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. "t" represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the

"t" clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

charging symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a "Don't Care" for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will

ignore the second Read or Write request.

10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table.NWS

, NWS

,BWS

, BWS

1 ,

BWS

and BWS

can be altered on different

portions of a write cycle, as long as the set-up and hold requirements are achieved.

Vt = Vddq/2

C C#

D
A

C C#

D
A

BUS

MASTER

(CPU

ASIC)

SRAM #1

SRAM #4

DATA IN

DATA OUT

Address

RPS#

WPS#

BWS#

Source K

Source K#

Delayed K

Delayed K#

R = 50

ohms

R = 250

ohms

R = 250

ohms

R
P

S
#

P
S
#

S
#

R
P

S
#

P
S
#

S
#

CQ/CQ#

CLKIN/CLKIN#

PRELIMINARY

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CY7C1515V18

Document #: 38-05363 Rev. *A

Page 10 of 23

During the Data portion of a Write sequence

CY7C1511V18

- only the lower nibble (D

[3:0]

) is written into the device. D

[7:4]

will remain

unaltered,

CY7C1513V18

- only the lower byte (D

[8:0]

) is written into the device. D

[17:9]

will remain

unaltered.

LH During the Data portion of a Write sequence

CY7C1511V18

- only the lower nibble (D

[3:0]

) is written into the device. D

[7:4]

will remain

unaltered,

CY7C1513V18

- only the lower byte (D

[8:0]

) is written into the device. D

[17:9]

will remain

unaltered.

During the Data portion of a Write sequence

CY7C1511V18

- only the upper nibble (D

[7:4]

) is written into the device. D

[3:0]

will

remain unaltered,

CY7C1513V18

- only the upper byte (D

[17:9]

) is written into the device. D

[8:0]

will remain

unaltered.

LH During the Data portion of a Write sequence

CY7C1511V18

- only the upper nibble (D

[7:4]

) is written into the device. D

[3:0]

will

remain unaltered,

CY7C1513V18

- only the upper byte (D

[17:9]

) is written into the device. D

[8:0]

will remain

unaltered.

No data is written into the devices during this portion of a write operation.

LH No data is written into the devices during this portion of a write operation.

Write Cycle Descriptions

[2, 10]

(CY7C1515V18)

BWS

Comments

During the Data portion of a Write sequence, all four bytes (D

[35:0]

) are written

into the device.

LH During the Data portion of a Write sequence, all four bytes (D

[35:0]

) are written

into the device.

During the Data portion of a Write sequence, only the lower byte (D

[8:0]

) is written

into the device. D

[35:9]

will remain unaltered.

LH During the Data portion of a Write sequence, only the lower byte (D

[8:0]

) is written

into the device. D

[35:9]

will remain unaltered.

During the Data portion of a Write sequence, only the byte (D

[17:9]

) is written into

the device. D

[8:0]

and D

[35:18]

will remain unaltered.

LH During the Data portion of a Write sequence, only the byte (D

[17:9]

) is written into

the device. D

[8:0]

and D

[35:18]

will remain unaltered.

During the Data portion of a Write sequence, only the byte (D

[26:18]

) is written

into the device. D

[17:0]

and D

[35:27]

will remain unaltered.

LH During the Data portion of a Write sequence, only the byte (D

[26:18]

) is written

into the device. D

[17:0]

and D

[35:27]

will remain unaltered.

During the Data portion of a Write sequence, only the byte (D

[35:27]

) is written

into the device. D

[26:0]

will remain unaltered.

LH During the Data portion of a Write sequence, only the byte (D

[35:27]

) is written

into the device. D

[26:0]

will remain unaltered.

No data is written into the device during this portion of a write operation.

LH No data is written into the device during this portion of a write operation.

Write Cycle Descriptions

[2, 10]

(CY7C1526V18)

BWS

During the Data portion of a Write sequence, the single byte (D

[8:0]

) is written

into the device.

LH During the Data portion of a Write sequence, the single byte (D

[8:0]

) is written

into the device.

No data is written into the device during this portion of a write operation.

LH No data is written into the device during this portion of a write operation.

Write Cycle Descriptions

CY7C1511V18 and CY7C1526V18) (continued)

[2, 10]

BWS

/NWS

BWS

/NWS

Comments

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Document #: 38-05363 Rev. *A

Page 11 of 23

Maximum Ratings

(Above which the useful life may be impaired.)

Storage Temperature .................................65°C to +150°C
Ambient Temperature with Power Applied ....10°C to +85°C
Supply Voltage on V

Relative to GND........ 0.5V to +2.9V

DC Applied to Outputs in High-Z .........0.5V to V

DDQ

+ 0.3V

DC Input Voltage

[14]

............................ 0.5V to V

DDQ

+ 0.3V

Current into Outputs (LOW) .........................................20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch-up Current..................................................... >200 mA

Operating Range

Range

Ambient

Temperature (T

)

[15]

DDQ

[15]

Com'l

0°C to +70°C

1.8 ± 0.1V

1.4V to V

DC Electrical Characteristics

Over the Operating Range

[11]

Parameter

Description

Test Conditions

Min.

Typ.

Max.

Unit

Power Supply Voltage

1.7

1.8

1.9

DDQ

I/O Supply Voltage

1.4

1.5

Output HIGH Voltage

[12]

DDQ

/2-0.12

DDQ

/2 + 0.12

Output LOW Voltage

[13]

DDQ

/2 -0.12

DDQ

/2 + 0.12

OH(LOW)

Output HIGH Voltage

-0.1 mA, Nominal Impedance

DDQ

0.2

DDQ

OL(LOW)

Output LOW Voltage

= 0.1mA, Nominal Impedance

0.2

Input HIGH Voltage

[14]

REF

+ 0.1

DDQ

+0.3

Input LOW Voltage

[14]

0.3

REF

0.1

Input Load Current

GND

DDQ

-5

µA

Output Leakage Current

GND

DDQ,

Output Disabled

-5

µA

REF

Input Reference Voltage

[16]

Typical Value = 0.75V

0.68

0.75

0.95

Operating Supply

= Max., I

OUT

= 0

mA,

f = f

MAX

= 1/t

CYC

167 MHz

TBD

200 MHz

TBD

250 MHz

TBD

SB1

Automatic

Power-down

Current

Max. V

, Both Ports

Deselected, V

f = f

MAX

1/t

CYC

Inputs Static

167 MHz

TBD

200 MHz

TBD

250 MHz

TBD

Notes:

11. All Voltage referenced to Ground.
12. Output are impedance controlled. Ioh=

(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms.

13. Output are impedance controlled. Iol=(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms.
14. Overshoot: V

(AC) < V

DDQ

+0.85V (Pulse width less than t

CYC

/2), Undershoot: V

(AC) >

1.5V (Pulse width less than t

CYC

/2).

15. Power-up: Assumes a linear ramp from 0v to V

(min.) within 200ms. During this time V

< V

and V

DDQ

< V

16. V

REF

(Min.) = 0.68V or 0.46V

DDQ

, whichever is larger, V

REF

(Max.) = 0.95V or 0.54V

DDQ

, whichever is smaller.

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AC Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min.

Typ.

Max.

Unit

Input High (Logic 1) Voltage

REF

+ 0.2

Input Low (Logic 0) Voltage

REF

0.2

Switching Characteristics

Over the Operating Range

[17,18]

Cypress

Parameter

Consortium

Parameter

Description

250 MHz

200 MHz

167 MHz

Unit

Min.

Max.

Min. Max. Min. Max.

POWER

(Typical) to the first Access

[21]

CYC

KHKH

K Clock and C Clock Cycle Time

4.0

6.3

5.0

7.9

6.0

8.4

KHKL

Input Clock (K/K; C/C) HIGH

1.6

2.0

2.4

KLKH

Input Clock (K/K; C/C) LOW

1.6

2.0

2.4

KHKH

K Clock Rise to K Clock Rise and C to C Rise

(rising edge to rising edge)

1.8

2.2

2.7

KHCH

K/K Clock Rise to C/C Clock Rise (rising edge to

rising edge)

0.0

1.8

0.0

2.2

0.0

2.7

Set-up Times
t

Address Set-up to K Clock Rise

0.5

0.6

0.7

Control Set-up to Clock (K, K, C, C) Rise (RPS,

WPS)

0.5

0.6

0.7

SCDDR

Double Data Rate Control Set-up to Clock (K, K)

Rise (BWS

, BWS

BWS

, BWS

)

0.35

0.4

0.5

[X:0]

Set-up to Clock (K/K) Rise

0.35

0.4

0.5

Hold Times
t

Address Hold after Clock (K/K) Rise

0.5

0.6

0.7

Control Hold after Clock (K /K) Rise (RPS, WPS)

0.5

0.6

0.7

HCDDR

Double Data Rate Control Hold after Clock (K/K)

Rise (BWS

, BWS

BWS

, BWS

)

0.35

0.4

0.5

[X:0]

Hold after Clock (K/K) Rise

0.35

0.4

0.5

Output Times
t

CHQV

C/C Clock Rise (or K/K in single clock mode) to

Data Valid

0.45

0.50

DOH

CHQX

Data Output Hold after Output C/C Clock Rise

(Active to Active)

0.45

-0.50

CCQO

CHCQV

C/C Clock Rise to Echo Clock Valid

0.45

0.50

CQOH

CHCQX

Echo Clock Hold after C/C Clock Rise

0.45

0.50

CQD

CQHQV

Echo Clock High to Data Valid

0.30

0.35

0.40

CQDOH

CQHQX

Echo Clock High to Data Invalid

0.30

0.35

0.40

CHZ

Clock (C and C) Rise to High-Z (Active to

High-Z)

[19, 20]

0.45

0.50

CLZ

Clock (C and C) Rise to Low-Z

[19, 20]

0.45

0.50

DLL Timing
t

KC Var

Clock Phase Jitter

0.20

KC lock

DLL Lock Time (K, C)

1024

cycles

KC Reset

K Static to DLL Reset

Notes:

17. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency,

it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.

18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250

, V

DDQ

= 1.5V, input

pulse levels of 0.25V to 1.25V, and output loading of the specified I

and load capacitance shown in (a) of AC test loads.

19. t

CHZ

, t

CLZ

, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured

± 100 mV from steady-state voltage.

20. At any given voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than t

21. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

minimum initially before a read or write operation

can be initiated.

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Page 13 of 23

Thermal Resistance

[22]

Parameter

Description

Test Conditions

165 FBGA

Package

Unit

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods and procedures for

measuring thermal impedance, per EIA/JESD51.

16.2

°C/W

Thermal Resistance

(Junction to Case)

2.3

°C/W

Capacitance

[22]

Parameter

Description

Test Conditions

Max.

(for x8,

x18,x36

options)

Max.

(for x9

option)

Unit

Input

Capacitance

= 25

°C, f = 1 MHz,

= 1.8V

DDQ

= 1.5V

TBD

CLK

Clock Input Capacitance

8.5

TBD

Output Capacitance

TBD

AC Test Loads and Waveforms

Note:

22. Tested initially and after any design or process change that may affect these parameters.

1.25V

0.25V

R = 50

5 pF

Including jig

and scope

ALL INPUT PULSES

Device

= 50

REF

= 0.75V

REF

= 0.75V

[14]

0.75V

Under
Test

0.75V

Device
Under
Test

OUTPUT

REF

OUTPUT

(a)

RQ =
250

(b)

RQ =
250

0.75V

Slew Rate = 2V / ns

PRELIMINARY

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Document #: 38-05363 Rev. *A

Page 15 of 23

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant

with IEEE Standard #1149.1-1900. The TAP operates using

JEDEC standard 1.8V I/O logic levels.

Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V

through a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

Test Access PortTest Clock
The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test Mode Select
The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)
The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see Instruction codes). The

output changes on the falling edge of TCK. TDO is connected

to the least significant bit (LSB) of any register.

Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

TAP Registers
Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

Instruction Register
Three-bit instructions can be serially loaded into the instruction

TDI and TDO pins as shown in TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.
When the TAP controller is in the Capture IR state, the two

least significant bits are loaded with a binary "01" pattern to

allow for fault isolation of the board level serial test path.

Bypass Register
To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

) when the BYPASS instruction is executed.

Boundary Scan Register
The boundary scan register is connected to all of the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices.
The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.
The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

TAP Instruction Set
Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.
Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

PRELIMINARY

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Document #: 38-05363 Rev. *A

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is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the "Update IR" state.

SAMPLE/PRELOAD
SAMPLE / PRELOAD is a 1149.1 mandatory instruction.

When the SAMPLE / PRELOAD instructions are loaded into

the instruction register and the TAP controller is in the Cap-

ture-DR state, a snapshot of data on the inputs and output pins

is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there is no guarantee as to the value that will be

captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t

and t

). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE / PRELOAD instruction. If

this is an issue, it is still possible to capture all other signals

and simply ignore the value of the CK and CK# captured in the

boundary scan register.
Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required - that is, while data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be

able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.

When this scan cell, called the "extest output bus tristate", is

latched into the preload register during the "Update-DR" state

in the TAP controller, it will directly control the state of the

output (Q-bus) pins, when the EXTEST is entered as the

current instruction. When HIGH, it will enable the output

buffers to drive the output bus. When LOW, this bit will place

the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, during the "Shift-DR" state. During "Update-DR", the value

loaded into that shift-register cell will latch into the preload

directly control the output Q-bus pins. Note that this bit is

pre-set HIGH to enable the output when the device is

powered-up, and also when the TAP controller is in the

"Test-Logic-Reset" state.

Reserved
These instructions are not implemented but are reserved for

future use. Do not use these instructions.

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TAP Controller Block Diagram

TAP Electrical Characteristics

Over the Operating Range

[11,14,27]

Parameter

Description

Test Conditions

Min.

Max.

Unit

OH1

Output HIGH Voltage

-2.0 mA

1.4

OH2

Output HIGH Voltage

-100 µA

1.6

OL1

Output LOW Voltage

= 2.0 mA

0.4

OL2

Output LOW Voltage

= 100

µA

0.2

Input HIGH Voltage

0.65V

+ 0.3

Input LOW Voltage

0.3

0.35V

Input and Output Load Current

GND

µA

TAP AC Switching Characteristics

Over the Operating Range

[28,29]

Parameter

Description

Min.

Max.

Unit

TCYC

TCK Clock Cycle Time

TCK Clock Frequency

MHz

TCK Clock HIGH

TCK Clock LOW

Set-up Times
t

TMSS

TMS Set-up to TCK Clock Rise

TDIS

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

Hold Times
t

TMSH

TMS Hold after TCK Clock Rise

TDIH

TDI Hold after Clock Rise

Capture Hold after Clock Rise

Notes:

27. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
28. t

and t

refer to the set-up and hold time requirements of latching data from the boundary scan register.

29. Test conditions are specified using the load in TAP AC test conditions. t

= 1 ns.

Boundary Scan Register

Identification Register

106

Instruction Register

Bypass Register

Selection
Circuitry

TAP Controller

TDI

TDO

TCK
TMS

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Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

Boundary Scan

109

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the Input/Output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register

between TDI and TDO. This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the Input/Output contents. Places the boundary scan register

between TDI and TDO. Forces all SRAM output drivers to a High-Z

state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures the Input/Output ring contents. Places the boundary scan

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does

not affect SRAM operation.

Boundary Scan Order

Bit #

Bump ID

11P

10P

10N

10M

11N

11L

11M

10L

11K

10K

10J

11J

11H

10G

11F

11G

10F

11E

10E

10D

10C

11D

11B

11C

10B

Boundary Scan Order

(continued)

Bit #

Bump ID

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Document #: 38-05363 Rev. *A

Page 22 of 23

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT,NEC, and Samsung

technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Ordering Information

Speed

(MHz)

Ordering Code

Package

Name

Package Type

Operating

Range

250

CY7C1511V18-250BZC

BB165E

15 x 17 x 1.4 mm FBGA

Commercial

CY7C1526V18-250BZC
CY7C1513V18-250BZC
CY7C1515V18-250BZC

200

CY7C1511V18-200BZC

BB165E

15 x 17x 1.4 mm FBGA

Commercial

CY7C1526V18-200BZC
CY7C1513V18-200BZC
CY7C1515V18-200BZC

167

CY7C1511V18-167BZC

BB165E

15 x 17 x 1.4 mm FBGA

Commercial

CY7C1526V18-167BZC
CY7C1513V18-167BZC
CY7C1515V18-167BZC

Shaded areas contain advanced information. Please contact your local Cypress sales representative for availability of these parts.

Package Diagram

PIN 1 CORNER

17.00±0.10

15.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.41±0.05

1.40

MAX.

SEATING PLANE

0.53±0.05

0.25

0.15

PIN 1 CORNER

TOP VIEW

BOTTOM VIEW

10.00

14.00

1.00

5.00

0.36

+0.14

-0.06

165-Ball FBGA (15 x 17 x 1.40 mm) Pkg. Outline (0.50 Ball Dia.) BB165E

51-85195-**

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