4Kx4 RAM
CY7C168A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
February 3, 2000
Features
Automatic power-down when deselected
CMOS for optimum speed/power
High speed
-- t
AA
= 15 ns
Low active power
-- 633 mW
Low standby power
-- 110 mW
TTL-compatible inputs and outputs
V
IH
of 2.2V
Capable of withstanding greater than 2001V electrostat-
ic discharge
Functional Description
The CY7C168A is a high-performance CMOS static RAM or-
ganized as 4096 by 4 bits. Easy memory expansion is provided
by an active LOW Chip Enable (CE) and three-state drivers.
The CY7C168A has an automatic power-down feature, reduc-
ing the power consumption by 77% when deselected.
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
four data input/output pins (I/O
0
through I/O
3
) is written into the
memory location specified on the address pins (A
0
through
A
11
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the location specified on the
address pins will appear on the four data input/output pins
(I/O
0
through I/O
3
).
The input/output pins remain in a high-impedance state when
Chip Enable (CE) is HIGH or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
128 x 128
ARRAY
C168A-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
Top View
DIP/SOJ
7C168A
A
1
A
2
A
3
A
8
A
9
A
4
A
0
COLUMN
DECODER
RO
W
DE
CO
D
E
R
SE
N
SE A
M
P
INPUTBUFFER
POWER
DOWN
WE
CE
I/O
0
A
5
A
6
A
7
A
8
A
9
A
11
WE
GND
CE
V
CC
A
2
A
1
A
0
C168A-2
I/O
1
A
10
A
11
A
5
A
4
I/O
0
I/O
1
I/O
2
I/O
3
I/O
2
I/O
3
A
7
A
6
A
10
A
3
(7C168A)
20
19
\
Selection Guide
7C168A-15
7C168A-20
7C168A-25
7C168A-35
7C168A-45
Maximum Access Time (ns)
15
20
25
35
45
Maximum Operating
Current (mA)
Commercial
115
90
90
90
90
Military
-
100
100
100
100
CY7C168A
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................-
65
C to +150
C
Ambient Temperature with
Power Applied
..................................................-
55
C to +125
C
Supply Voltage to Ground Potential
(Pin 20 to Pin 10)
................................................ -
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.................................................... -
0.5V to +7.0V
DC Input Voltage
.................................................-
3.0V to +7.0V
Output Current into Outputs (Low) .............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
5V
10%
Military
[1]
-
55
C to +125
C
5V
10%
Electrical Characteristics
Over the Operating Range
[2]
7C168A-15
7C168A-20
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
2.2
V
CC
V
V
IL
Input LOW Voltage
[3]
-
0.5
0.8
-
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
10
+10
-
10
+10
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
,
Output Disabled
-
10
+10
-
10
+10
A
I
OS
Output Short
Circuit Current
[4]
V
CC
= Max., V
OUT
= GND
-
350
-
350
mA
I
CC
V
CC
Operating
Supply Current
V
CC
=
Max.,
I
OUT
= 0 mA
Com'l
115
90
mA
Mil
-
100
I
SB1
Automatic CE
Power-Down Current
Max. V
CC
,
CE > V
IH
Com'l
40
40
mA
Mil
-
40
I
SB2
Automatic CE
Power-Down Current
Max. V
CC
,
CE > V
CC
-
0.3V
Com'l
20
20
mA
Mil
-
20
Notes:
1.
T
A
is the "instant on" case temperature.
2.
See the last page of this specification for Group A subgroup testing information.
3.
V
IL
min. =
-
3.0V for pulse durations less than 30 ns.
4.
Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C168A
3
Electrical Characteristics
Over the Operating Range
[2]
(continued)
Parameter
Description
Test Conditions
7C168A-25
7C168A-35
7C168A-45
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
2.2
V
CC
2.2
V
CC
V
V
IL
Input LOW Voltage
[3]
-
0.5
0.8
-
0.5
0.8
-
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
10
+10
-
10
10
-
10
10
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
Output Disabled
-
10
+10
-
50
50
-
50
50
A
I
OS
Output Short
Circuit Current
[4]
V
CC
= Max., V
OUT
= GND
-
350
-
350
-
350
mA
I
CC
V
CC
Operating
Supply Current
V
CC
=
Max.,
I
OUT
= 0 mA
Com'l
90
90
90
mA
Mil
100
100
100
I
SB1
Automatic CE
Power-Down Current
Max. V
CC
,
CE > V
IH
Com'l
20
20
20
mA
Mil
20
20
20
I
SB2
Automatic CE
Power-Down Current
Max. V
CC
,
CE > VCC
-
0.3 V
Com'l
20
20
20
mA
Mil
20
20
20
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
10
pF
C
OUT
Output Capacitance
10
pF
Note:
5.
Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
5V
OUTPUT
C168A-3
R1 481
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
C168A-4
(a)
(b)
OUTPUT
1.73V
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
167
CY7C168A
4
Switching Characteristics
Over the Operating Range
[2,6]
Parameter
Description
7C168A-15
7C168A-20
7C168A-25
7C168A-35
7C168A-45
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
15
20
25
35
45
ns
t
AA
Address to Data Valid
15
20
25
35
45
ns
t
OHA
Output Hold from Address Change
5
5
5
5
5
ns
t
ACE
Power Supply Current
15
20
25
35
45
ns
t
LZCE
CE LOW to Low Z
[7]
5
5
5
5
5
ns
t
HZCE
CE HIGH to High Z
[7, 8]
8
8
10
15
15
ns
t
PU
CE LOW to Power Up
0
0
0
0
0
ns
t
PD
CE HIGH to Power-Down
15
20
20
20
25
ns
t
RCS
Read Command Set-Up
0
0
0
0
0
ns
t
RCH
Read Command Hold
0
0
0
0
0
ns
WRITE CYCLE
[9]
t
WC
Write Cycle Time
15
20
20
25
40
ns
t
SCE
CE LOW to Write End
12
15
20
25
30
ns
t
AW
Address Set-Up to Write End
12
15
20
25
30
ns
t
HA
Address Hold from Write End
0
0
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
0
0
ns
t
PWE
WE Pulse Width
12
15
15
20
20
ns
t
SD
Data Set-Up to Write End
10
10
10
15
15
ns
t
HD
Data Hold from Write End
0
0
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
7
7
7
5
5
ns
t
HZWE
WE LOW to High Z
[7, 8]
5
5
5
5
10
ns
Switching Waveforms
Notes:
6.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7.
At any given temperature and voltage condition, t
HZ
is less than t
LZ
for all devices. Transition is measured
500 mV from steady state voltage with specified loading in part
(b) of AC Test Loads and Waveforms.
8.
t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (a) of Test Loads and Waveforms. Transition is measured
500 mV from steady state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can terminate a
write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = V
IL
.
Read Cycle No. 1
ADDRESS
C168A-5
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
[10, 11]
CY7C168A
5
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
Read Cycle
Write Cycle No. 1 (WE Controlled)
50%
50%
DATA VALID
t
RC
t
ACE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZCE
t
PD
CE
HIGH
C168A-6
t
WC
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
V
CC
SUPPLY
CURRENT
t
HZWE
t
LZWE
t
SD
C168A-7
CE
WE
DATA IN
DATA I/O
ADDRESS
WE
t
RCS
t
RCH
DATA
IN
VALID
[10, 12]
[9]
Write Cycle No. 2 (CS Controlled)
t
WC
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
PWE
t
HA
t
HD
t
HZWE
t
SD
ADDRESS
CE
WE
DATA IN
DATA I/O
t
SA
C168A-8
DATA
IN
VALID
[9, 13]
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