1 of 19

111899

FEATURES

Holds microprocessor in check during power
transients

Halts and restarts an out-of-control
microprocessor

Monitors pushbutton for external override

Warns microprocessor of an impending power
failure

Converts CMOS SRAM into nonvolatile
memory

Unconditionally write-protects memory when
power supply is out of tolerance

Consumes less than 100 nA of battery current
at 25

Controls external power switch for high
current applications

Accurate 10% power supply monitoring

Optional 5% power supply monitoring
designated DS1236-5

Provides orderly shutdown in nonvolatile
microprocessor applications

Supplies necessary control for low-power
"stop mode" in battery operated hand-held
applications

Standard 16-pin DIP or space-saving 16-pin
SOIC

Optional industrial temperature range -40

to +85

PIN ASSIGNMENT

PIN DESCRIPTION

BAT

- +3-Volt Battery Input

CCO

- Switched SRAM Supply Output

- +5-Volt Power Supply Input

GND -

Ground

- Power-Fail (Active High)

- Power-Fail (Active Low)

WC/

- Wake-Up Control (Sleep)

- Reset Control

- Early Warning Input

NMI

Non-Maskable

Interrupt

- Strobe Input

CEO

- Chip Enable Output

CEI

- Chip Enable Input

PBRST

- Pushbutton Reset Input

RST

- Reset Output (Active Low)

RST

- Reset Output (Active High)

DESCRIPTION

The DS1236 MicroManager Chip provides all the necessary functions for power supply monitoring, reset
control, and memory backup in microprocessor-based systems. A precise internal voltage reference and
comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
write protects external memory. The DS1236 also provides early warning detection of a user-defined
threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset

DS1236

MicroManager Chip

www.dalsemi.com

16-Pin SOIC (300-mil)

See Mech. Drawings Section

VBAT

VCCO

VCC

RST
RST
PBRST

1
2
3

16
15
14

GND

CEI

PF
PF

WC/SC

CEO
ST
NMI

5
6
7

12
11
10

RCI

16-Pin DIP (300-mil)

See Mech. Drawings Section

VBAT

VCCO

VCC

RST

PBRST

GND

CEI

WC/SC

CEO

NMI

DS1236

2 of 19

input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset
outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control
and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in
battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1.

PIN DESCRIPTION

PIN NAME

DESCRIPTION

BAT

+3V battery input provides nonvolatile operation of control functions.

CCO

output for nonvolatile SRAM applications.

+5V primary power input.

Power-fail indicator, active high, used for external power switching as shown in
Figure 9.

Power-fail indicator, active low.

WC/

Wake-up and Sleep control. Invokes low-power mode.

Reset control input. Determines reset output. Normally low for NMOS processors and
high for battery backed CMOS processors.

Early warning power-fail input. This voltage sense point can be tied (via resistor
divider) to a user-selected voltage.

NMI

Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending
power failure.

Strobe input. A high-to-low transition will reset the watchdog timer, indicating that
software is still in control.

CEO

Chip enable output. Used with nonvolatile SRAM applications.

CEI

Chip enable input.

PBRST

Pushbutton reset input.

RST

Active low reset output.

RST

Active high reset output.

PROCESSOR MODE

A distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power
consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM
and the CMOS processor. All resources would be maintained in the absence of V

. A power-down reset

is not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A
pulsed interrupt (

NMI

) is issued to allow the CMOS processor to invoke a sleep mode to save power. For

this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is
invoked by connecting RC to V

CCO

An NMOS processor consumes more power, and consequently may not be battery backed. In this case, it
is desirable to notify the processor of a power-fail, then keep it in reset during the loss of V

. This avoids

intermittent or aberrant operation. On power-up, the processor will continue to be reset until V

reaches

an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.

DS1236

3 of 19

POWER MONITOR

The DS1236 employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (V

) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RST and

RST

outputs are driven to the active state. The V

trip point (V

CCTP

) is set for 10% operation so that the

RST and

RST

outputs will become active as V

falls below 4.5 volts (4.37 typical). The V

CCTP

for the

5% operation option (DS1236-5) is set for 4.75 volts (4.62 typical). The RST and

RST

signals are

excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-
tolerance V

. On power-up, the RST and

RST

signals are held active for a minimum of 25 ms (100 ms

typical) after V

CCTP

is reached to allow the power supply and microprocessor to stabilize. Note: The

operation described above is obtained with the reset control pin (RC) connected to GND (NMOS mode).
Please review the reset control section for more information.

WATCHDOG TIMER

The DS1236 provides a watchdog timer function which forces the RST and

RST

signals to the active

state when the strobe input (

) is not stimulated for a predetermined time period. This time period is 400

ms typically with a maximum time-out of 600 ms. The watchdog time-out period begins as soon as RST
and

RST

are inactive. If a high-to-low transition occurs at the

input prior to time-out, the watchdog

timer is reset and begins to time out again. The

input timing is shown in Figure 2. To guarantee the

watchdog timer does not time out, a high-to-low transition on

must occur at or less than 100 ms

(minimum time-out) from a reset. If the watchdog timer is allowed to time out, the RST and

RST

outputs

are driven to the active state for 25 ms minimum. The

input can be derived from microprocessor

address, data, and/or control signals. Under normal operating conditions, these signals would routinely
reset the watchdog timer prior to time-out. If the watchdog timer is not required, two methods have been
provided to disable it.

Permanently grounding the IN pin in the CMOS mode (RC=1) will disable the watchdog. In normal
operation with RC=1, the watchdog is disabled as soon as the IN pin is below V

. With IN grounded, an

NMI

output will occur only at power-up, or when the

pin is strobed. As shown in the Figure 3, a

falling edge on

will generate an

NMI

when IN is below V

. This allows the processor to verify that

power is between V

and V

CCTP

, as an

NMI

will be returned immediately after the

strobe. The

watchdog timer is not affected by the IN pin when in NMOS mode (RC=0).

If the

NMI

signal is required to monitor supply voltages, the watchdog may also be disabled by leaving

the

input open. Independent of the state of the RC pin, the watchdog is also disabled as soon as V

falls to V

CCTP

PUSHBUTTON RESET

An input pin is provided on the DS1236 for direct connection to a pushbutton. The pushbutton reset input
requires an active low signal. Internally, this input is pulled high by a 10k resistor whenever V

greater than V

BAT

. The

PBRST

pin is also debounced and timed such that the RST and

RST

outputs are

driven to the active state for 25 ms minimum. This 25 ms delay begins as the pushbutton is released from
a low level. A typical example of the power monitor, watchdog timer, and pushbutton reset connections
are shown in Figure 4. The PBRST input is disabled whenever the IN pin voltage level is less than V

and the reset control (RC) is tied high (CMOS mode). The

PBRST

input is also disabled whenever V

below V

BAT

. Timing of the

PBRST

-generated RST is illustrated in Figure 5.

DS1236

4 of 19

NON-MASKABLE INTERRUPT

The DS1236 generates a non-maskable interrupt

NMI

for early warning of power failure to a

microprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (Figure 6) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point V

is 2.54 volts, the proper values

for R1 and R2 can be determined by the equation as shown in Figure 6. Proper operation of the DS1236
requires that the voltage at the IN pin be limited to V

. Therefore, the maximum allowable voltage at the

supply being monitored (V

MAX

) can also be derived as shown in Figure 6. A simple approach to solving

this equation is to select a value for R2 high enough to keep power consumption low, and solve for R1.
The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power
supply system, maximizing the amount of time for microprocessor shutdown between

NMI

and RST or

RST

When the supply being monitored decays to the voltage sense point, the DS1236 pulses the

NMI

output

to the active state for a minimum of 200

s. The

NMI

power-fail detection circuitry also has built-in time

domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33

s/cycle). Three consecutive samplings of

out-of-tolerance supply (below V

SENSE

) must occur at the IN pin to activate

NMI

. Therefore, the supply

must be below the voltage sense point for approximately 100

s or the comparator will reset. In this way,

power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any IN pin levels below V

are disabled from reaching the

NMI

pin until V

rises to V

CCTP

. As a result,

any potential

NMI

pulse will not be initiated until V

reaches V

CCTP

Removal of an active low level on the

NMI

pin is controlled by either an internal time-out (when IN pin

is less than V

) or by the subsequent rise of the IN pin above V

. The initiation and removal of the

NMI

signal during power-up results in an

NMI

pulse of from 0

s minimum to 500

s maximum, depending

on the relative voltage relationship between V

and the IN pin voltage. As an example, when the IN pin

is tied to ground during power-up, the internal time-out will result in a pulse of 200

s minimum to 500

s maximum. In contrast, if the IN pin is tied to V

CCO

during power-up,

NMI

will not produce a pulse on

power-up. Note that a fast slewing power supply may cause the

NMI

to be virtually nonexistent on

power-up. This is of no consequence, however, since an RST will be active.

DS1236

5 of 19

DS1236 FUNCTIONAL BLOCK DIAGRAM Figure 1

If the IN pin is connected to V

CCO

, the

NMI

output will pulse low as V

decays to V

CCTP

in the NMOS

mode (RC=0). In the CMOS mode (RC=V

CCO

) the power-down of V

out-of-tolerance at V

CCTP

will not

produce a pulse on the

NMI

pin. Given that any

NMI

pulse has been completed by the time V

decays

to V

CCTP

, the

NMI

pin will remain high. The

NMI

voltage will follow V

down until V

decays to

BAT

. Once V

decays to V

BAT

, the

NMI

pin will either remain at V

OHL

or enter tri-state mode as

determined by the RC pin (see "Reset Control" section).

MEMORY BACKUP

The DS1236 provides all of the necessary functions required to battery back a static RAM. First, a switch
is provided to direct SRAM power from the incoming 5-volt supply (V

) or from an external battery

BAT

), whichever is greater. This switched supply (V

CCO

) can also be used to battery back a CMOS

microprocessor. For more information about nonvolatile processor applications, review the "Reset
Control" and "Wake Control" sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output (

CEO

) to within 0.3 volts of V

or to within 0.7

volts of V

BAT

. This write protection mechanism occurs as V

falls below V

CCTP

as specified. If

CEI

DS1236

6 of 19

low at the time power-fail detection occurs,

CEO

is held in its present state until

CEI

is returned high, or

the period t

expires. This delay of write protection until the current memory cycle is completed prevents

the corruption of data. If

CEO

is in an inactive state at the time of V

fail detection,

CEO

will be

unconditionally disabled within t

. During nominal supply conditions

CEO

will follow

CEI

with a

maximum propagation delay of 20 ns. Figure 7 shows a typical nonvolatile SRAM application.

FRESHNESS SEAL

In order to conserve battery capacity during storage and/or shipment of an end system, the DS1236
provides a freshness seal to electrically disconnect the battery. Figure 8 depicts the three pulses below
ground on the IN pin required to invoke the freshness seal. The freshness seal will be disconnected and
normal operation will begin when V

is cycled and reapplied to a level above V

BAT

To prevent negative pulses associated with noise from setting the freshness mode in system applications,
a series diode and resistor can be used to shunt noise to ground. During manufacturing, the freshness seal
can still be set by holding TP2 at -3 volts while applying the 0 to 3 volts clock to TP1.

POWER SWITCHING

When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236 may not be large enough to support the required load through
V

CCO

with a reasonable voltage drop. For these applications, the PF and

outputs are provided to gate

external power switching devices. As shown in Figure 9, power to the load is switched from V

battery on power-down, and from battery to V

on power-up. The DS1336 is designed to use the

output to switch between V

BAT

and V

. It provides better leakage and switchover performance than

currently available discrete components. The transition threshold for PF and

is set to the external

battery voltage V

BAT

, allowing a smooth transition between sources. The load applied to the PF pin from

the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.

RESET CONTROL

As mentioned above, the DS1236 supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST,

RST

, and

NMI

outputs for volatile

processor operation versus nonvolatile battery backup or battery operated processor applications.

ST/INPUT TIMING Figure 2

DS1236

9 of 19

When the RC pin is tied to ground, the DS1236 is designed to interface with NMOS processors which do
not have the microamp currents required during a battery backed mode. Grounding the RC pin does,
however, continue to support nonvolatile backup of system SRAM memory. Nonvolatile systems
incorporating NMOS processors generally require that only the SRAM memory and/or timekeeping
functions be battery backed. When the processor is not battery backed (RC = 0), all signals connected
from the processor to the DS1236 are disconnected from the backup battery supply, or grounded when
system V

decays below V

BAT

. In the NMOS processor system, the principal emphasis is placed on

giving early warnings with

NMI

, then providing a continuously active RST and RST signal during

power-down while isolating the backup battery from the processor during a loss of V

During power-down,

NMI

will pulse low for a minimum of 200

s, and then return high. If RC is tied

low (NMOS mode), the voltage on

NMI

will follow V

until V

supply decays to V

BAT

, at which point

NMI

will enter tri-state (see timing diagram). Also, upon V

out-of-tolerance at V

CCTP

, the RST and

RST

outputs are driven active and RST will follow V

as the supply decays. On power-up, RST follows

up,

RST

is held low, and both remain active for t

RST

after valid V

. During a power-up from a V

voltage below V

BAT

, any detected IN pin levels below V

are disabled from reaching the

NMI

pin until

rises to V

CCTP

. As a result, any potential

NMI

pulse will not be initiated until V

reaches V

CCTP

Removal of an active low level on the

NMI

pin is controlled by either an internal time-out (when the IN

pin is less than V

), or by the subsequent rise of the IN pin above V

. The initiation and removal of the

NMI

signal results in an

NMI

pulse of 0

s minimum to 500

s maximum during power-up, depending

on the relative voltage relationship between V

and the IN pin. As an example, when the IN pin is tied to

ground, the internal timeout will result in a pulse of 200

s minimum to 500

s maximum. In contrast, if

the IN pin is tied to V

CCO

NMI

will not produce a pulse on power-up.

Connecting the RC pin to a high (V

CCO

) invokes CMOS mode and provides nonvolatile support to both

the system SRAM as well as a low power CMOS processor. When using CMOS microprocessors, it is
possible to place the microprocessor into a very low-power mode termed the "stop" or "halt" mode. In
this state the CMOS processor requires only microamp currents and is fully capable of being battery
backed. This mode generally allows the CMOS microprocessor to maintain the contents of internal RAM
as well as state control of I/O ports during battery backup. The processor can subsequently be restarted by
any of several different signals. To maintain this low-power state, the DS1236 issues no

NMI

and/or reset

signals to the processor until it is time to bring the processor back into full operation. To support the low-
power processor battery backed mode (RC = 1), the DS1236 provides a pulsed

NMI

for early power

failure warning. Waiting to initiate a Stop mode until after the

NMI

pin has returned high will guarantee

the processor that no other active

NMI

or RST/

RST

will be issued by the DS1236 until one of two

conditions occurs: 1) Voltage on the pin rises above V

, which activates the watchdog, or 2) V

cycles

below then above V

BAT

, which also results in an active RST and

RST

. If V

does not fall below V

CCTP

the processor will be restarted by the reset derived from the watchdog timer as the IN pin rises above V

With the RC pin tied to V

CCO

, RST and

RST

are not forced active as V

collapses to V

CCTP

. The

RST

held at a high level via the external battery as V

falls below battery potential. This mode of operation is

intended for applications in which the processor is made nonvolatile with an external source, and allows
the processor to power down into a Stop mode as signaled from

NMI

at an earlier voltage level. The

NMI

output pin will pulse low for t

NMI

following a low voltage detect at the IN pin of V

. Following t

NMI

however,

NMI

will also be held at a high level (V

BAT

) by the battery as V

decays below V

BAT

. On

power-up, RST and

RST

are held inactive until V

reaches V

BAT

, then RST and

RST

are driven active

for t

RST

. If the IN pin falls below V

during an active reset, the reset outputs will be forced inactive by

the

NMI

output. In addition, as long as the IN pin is less than V

, stimulation of the ST pin will result in

DS1236

10 of 19

additional

NMI

pulses. In this way, the

pin can be used to allow the CMOS processor to determine if

the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in Figure 3. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.

TIMING DIAGRAMS

This section provides a description of the timing diagrams shown in Figure 10, Figure 11, Figure 12, and
Figure 13. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 10 illustrates the relationship for power-down in CMOS mode. As V

falls, the IN pin voltage drops below V

. As a result, the processor is notified of an impending power

failure via an active

NMI

, which allows it to enter a sleep mode. As the power falls further, V

crosses

CCTP

, the power monitor trip point. Since the DS1236 is in CMOS mode, no reset is generated. The

RST

voltage will follow V

down, but will fall no further than V

BAT

. At this time,

CEO

is brought high to

write protect the RAM. When the V

reaches V

BAT

, a power-fail is issued via the PF and

pins.

Figure 11 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an

NMI

is issued. This gives the processor time to save critical data in nonvolatile SRAM. When V

reaches V

CCTP

, an active RST and

RST

are given. The RST voltage will follow V

as it falls.

CEO

, PF,

and

will operate in a similar manner to CMOS mode. Notice that the

NMI

will tri-state to prevent a

loss of battery power.

Figure 12 shows the power-up sequence for the NMOS mode. As V

slews above V

BAT

, the PF and

pins are deactivated. An active reset occurs as well as an

NMI

. Although the

NMI

may be short due to

slew rates, reset will be maintained for the standard t

RST

timeout period. At a later time, if the IN pin falls

below V

, a new

NMI

will occur. If the processor does not issue a

, a watchdog reset will also occur.

The second

NMI

and RST are provided to illustrate these possibilities.

Figure 13 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
V

. Depending on the processor type, the

NMI

may terminate the Stop mode in the processor.

WAKE CONTROL/SLEEP CONTROL

The Wake/Sleep Control input (WC/

) allows the processor to disable all comparators on the DS1236

before entering the Stop mode. This feature allows the DS1236, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery
operated applications to conserve battery capacity when an absence of activity is detected. The operation
of this signal is shown in Figure 14. The DS1236 may subsequently be restarted by a high-to-low
transition on the

PBRST

input through human interface via a keyboard, touchpad, etc. The processor will

then be restarted as the watchdog times out and drives RST and

RST

active. The DS1236 can also be

started up by forcing the WC/

pin high from an external source. Also, if the DS1236 is placed in a

sleep mode by the processor and system power is lost, the DS1236 will wake up the next time V

rises

above V

BAT

. These possibilities are illustrated in Figure 15.

When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236 is
disabled, thus leaving the

NMI

, RST, and

RST

outputs disabled as well as the

and IN inputs.

However, a loss of power during a sleep mode will result in an active RST and

RST

when the RC pin is

grounded (NMOS mode). If the RC pin is tied high, the RST and

RST

pins will remain inactive during

DS1236

17 of 19

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Pin Relative to Ground

-0.5V to +7.0V

Voltage on I/O Relative to Ground

-0.5V to V

+ 0.5V

Voltage on IN Pin Relative to Ground

-3.5V to V

+ 0.5V

Operating Temperature

0°C to 70°C

Operating Temperature (Industrial Version)

-40°C to +85°C

Storage Temperature

-55°C to +125°C

Soldering Temperature

260°C for 10 seconds

This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0

C to 70

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Supply Voltage

4.5

5.0

5.5

Supply Voltage (5% Option)

4.75

5.0

5.5

Input High Level

2.0

+0.3

Input Low Level

-0.3

+0.8

IN Input Pin

-0.3

+0.3

Battery Input

BAT

2.7

4.0

DC ELECTRICAL CHARACTERISTICS (0

C to 70

C; V

= 4.5V to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Supply Current

Sleep Supply Current in Sleep
mode

Battery Current

BAT

0.1

Supply Output Current
(V

CCO

- 0.3V)

CC01

100

Supply Output Current in Data
Retention (V

< V

BAT

)

CC02

Supply Output Voltage

CCO

-0.3

Battery Backup Voltage

CCO

BAT

-0.7

1, 6

Low Level @ RST

0.4

Output Voltage @ -500

-0.5V V

-0.1V

CEO

and PF Output

OHL

BAT

-0.7

1, 6

PBRST

Pull-up Resist

PBRST

10k

Ohms

Input Leakage Current

-1.0

+1.0

Output Leakage Current

-1.0

+1.0

Output Current @ 0.4V

4.0

DS1236

18 of 19

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Output Current @ 2.4V

-1.0

Power Sup. Trip Point

CCTP

4.25

4.37

4.50

Power Supply Trip (5% Option)

CCTP

4.50

4.62

4.75

IN Input Pin Current

CCIN

-1.0

+1.0

IN Input Trip Point

2.5

2.54

2.6

AC ELECTRICAL CHARACTERISTICS (0

C to 70

C; V

= 4.5V to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Fail Detect to RST,

RST

RPD

100

175

NMI

IPD

100

175

RESET Active Time

RST

100

150

NMI

Pulse Width

NMI

200

300

500

Pulse Width

PBRST

@ V

Slew Rate 4.75 to 4.25

300

Chip Enable Propagation Delay

Fail to Chip Enable High

Valid to RST,

RST

(RC=1)

FPU

100

Valid to RST &

RST

RPU

100

150

Slew to 4.24 to V

BAT

FB1

Slew 4.25 to 4.75 V

BAT

FB2

100

Chip Enable Output Recovery
Time

REC

Slew 4.25 to 4.75

Chip Enable Pulse Width

Watchdog Time Delay

100

400

600

to WC/

0.1

BAT

Detect to PF,

PPF

NMI

STN

NMI

to RST &

RST

NRT

BAT

Detect to RST &

RST

ARST

200

Valid to RST,

RST

BRST

100

150

DS1236

19 of 19

CAPACITANCE (t

=25

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Capacitance

Output Capacitance

OUT

NOTES:

All voltages referenced to ground. A 0.1

F capacitor is recommended between V

and GND.

Measured with V

CCO

CEO

, PF,

PBRST

, RST,

RST

, and

NMI

pin open. I

BAT

specified at 25

CCO1

is the maximum average load which the DS1236 can supply at V

-0.3V through the V

CCO

during normal 5-volt operation.

CCO2

is the maximum average load which the DS1236 can supply through the V

CCO

pin during data

retention battery supply operation, with a maximum drop of 0.8 volts.

With t

= 5

CCO

is approximately V

BAT

-0.5V at 1

A load.

Sleep mode is not invoked.

Sleep mode is invoked.

REC

is the minimum time required before

CEI

CEO

memory access is allowed.

10.

maximum must be met to ensure data integrity on power loss.

11.

IN input is less than V

but V

greater than V

CCTP

12.

All outputs except RST which is 25

A maximum.

13.

All outputs except

RST

and

NMI

which is 25

A minimum.

14.

Pulse width of

NMI

requires that the IN pin remain below V

. If the IN pin returns to a level above

for a period longer than t

IPD

and before the t

NMI

period has elapsed, the

NMI

pin will immediately

return to a high.

15.

IN pin greater than V

when V

supply rises to V

BAT

. Example: IN tied to GND.

16.

IN pin less than V

when V

supply rises to V

BAT

17.

CEI

low.

18.

The WC/

pin contains an internal latch which drives back on to the pin. This latch requires

200

amps to switch states. The

pin will sink

amps in normal operation and

amp in the

sleep mode.

19.

should be active low before the watchdog is disabled (i.e., before the

input is tristated).

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DS1236

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DS1236