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REV: 022304
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
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.
GENERAL DESCRIPTION
The DS1553 is a full-function, year-2000-compliant
(Y2KC) real-time clock/calendar (RTC) with an RTC
alarm, watchdog timer, power-on reset, battery
monitor, and 8k x 8 nonvolatile static RAM. User
access to all registers within the DS1553 is
accomplished with a bytewide interface as shown in
Figure 1. The RTC registers contain century, year,
month, date, day, hours, minutes, and seconds data in
24-hour BCD format. Corrections for day of month and
leap year are made automatically.
ORDERING INFORMATION
*
PowerCap required, must be ordered separately.
FEATURES
Integrated NV SRAM, RTC, Crystal, Power-Fail
Control Circuit, and Lithium Energy Source
Clock Registers are Accessed Identically to the
Static RAM; These Registers are Resident in the 16
Top RAM Locations
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
Precision Power-On Reset
Programmable Watchdog Timer and RTC Alarm
BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Automatic Leap Year
Compensation Valid Up to the Year 2100
Battery Voltage Level Indicator Flag
Power-Fail Write Protection Allows for 10% V
CC
Power-Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power is
Applied for the First Time
PIN CONFIGURATIONS
PART PIN-PACKAGE
V
CC
(V)
TOP MARK
DS1553-100 28
EDIP
5.0
DS1553-100
DS1553-70 28
EDIP
5.0
DS1553-070
DS1553P-100
34 PowerCap
5.0 DS1553P-100
DS1553P-70 34
PowerCap 5.0
DS1553P-70
DS1553W-120 28
EDIP
3.3 DS1553W-120
DS1553W-150 28
EDIP
3.3 DS1553W-150
DS1553WP-120 34
PowerCap
3.3 DS1553WP-120
DS1553WP-150 34
PowerCap
3.3 DS1553WP-150
DS9034PCX* --
--
DS9034PCX
DS1553
64kB, Nonvolatile, Year-2000-Compliant
Timekeeping RAM
www.maxim-ic.com
PowerCap is a registered trademark of Dallas Semiconductor.
1
IRQ/FT
2
3
N.C.
N.C.
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
N.C.
N.C.
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
N.C.
X1
GND
V
BAT
X2
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
DS1553
28-Pin Encapsulated Package
(700-mil Extended)
V
CC
WE
IRQ/FT
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DS1553
TOP VIEW
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
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PIN DESCRIPTION
A0A12
- Address Input
DQ0DQ7
- Data Input/Outputs
IRQ
/FT
- Interrupt, Frequency Test Output
(Open Drain)
RST
- Power-On Reset Output (Open Drain)
CE
- Chip Enable
OE
- Output Enable
WE
- Write Enable
V
CC
-
Power-Supply
Input
GND
- Ground
N.C.
- No Connection
DETAILED DESCRIPTION
The RTC registers in the DS1553 are double-buffered into an internal and external set. The user has direct
access to the external set. Clock/calendar updates to the external set of registers can be disabled and
enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal
set of registers is continuously updated. This occurs regardless of external registers settings to guarantee
that accurate RTC information is always maintained.
The DS1553 has interrupt (
IRQ
/FT) and reset (
RST
) outputs that can be used to control CPU activity.
The
IRQ
/FT interrupt output can be used to generate an external interrupt when the RTC register values
match user-programmed alarm values. The interrupt is always available while the device is powered from
the system supply, and it can be programmed to occur when in the battery-backed state to serve as a
system wakeup. Either the
IRQ
/FT or
RST
outputs can also be used as a CPU watchdog timer. CPU
activity is monitored and an interrupt or reset output is activated if the correct activity is not detected
within programmed limits. The DS1553 power-on reset can be used to detect a system power-down or
failure and can hold the CPU in a safe reset state until normal power returns and stabilizes. The
RST
output is used for this function.
The DS1553 also contains its own power-fail circuitry, which automatically deselects the device when the
V
CC
supply enters an out-of-tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low V
CC
levels.
PACKAGES
The DS1553 is available in a 28-pin DIP and a 34-pin PowerCap module. The 28-pin DIP module
integrates the crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module
board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the
crystal and battery. This design allows the PowerCap to be mounted on top of the DS1553P after
completion of the surface-mount process. Mounting the PowerCap after the surface-mount process
prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The
PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered
separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
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Figure 1. Block Diagram
Table 1. Operating Modes
V
CC
CE OE WE DQ0DQ7 MODE POWER
V
IH
X X
High-Z
Deselect
Standby
V
IL
X V
IL
D
IN
Write
Active
V
IL
V
IL
V
IH
D
OUT
Read Active
V
CC
> V
PF
V
IL
V
IH
V
IH
High-Z
Read
Active
V
SO
< V
CC
<V
PF
X X X
High-Z
Deselect CMOS
Standby
<V
BAT
X
X
X
High-Z
Data Retention
Battery Current
DATA READ MODE
The DS1553 is in read mode whenever
CE
(chip enable) is low and
WE
(write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data is available at
the data input/output (DQ) pins within t
AA
after the last address input is stable, provided that
CE
and
OE
access times are satisfied. If
CE
or
OE
access times are not met, valid data is available at the latter of
chip-enable access (t
CEA
) or at output-enable access time (t
OEA
). The state of the DQ pins is controlled by
CE
and
OE
. If the outputs are activated before t
AA
, the data lines are driven to an intermediate state until
t
AA
. If the address inputs are changed while
CE
and
OE
remain valid, output data remains valid for
output data hold time (t
OH
) but will then go indeterminate until the next address access.
DATA WRITE MODE
The DS1553 is in write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE
. The addresses must be held valid throughout
the cycle.
CE
and
WE
must return inactive for a minimum of t
WR
prior to the initiation of a subsequent
read or write cycle. Data in must be valid t
DS
prior to the end of the write and remain valid for t
DH
afterward. In a typical application, the
OE
signal is high during a write cycle. However,
OE
can be active
provided that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
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transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on
WE
will then disable the outputs t
WEZ
after
WE
goes active.
DATA RETENTION MODE
The 5V device is fully accessible, and data can be written and read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power-fail point (V
PF
)--the point at which write protection occurs--the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point V
SO
(battery supply level), device power is switched from the V
CC
pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
When V
CC
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
SO
, the device power is
switched from V
CC
to the internal backup lithium battery when V
CC
drops below V
PF
. If V
PF
is greater
than V
SO
, the device power is switched from V
CC
to the internal backup lithium battery when V
CC
drops
below V
SO
. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels.
All control, data, and address signals must be powered down when V
CC
is powered down.
BATTERY LONGEVITY
The DS1553 has a lithium power source that is designed to provide energy for the clock activity and
clock and RAM data retention when the V
CC
supply is not present. The capability of this internal power
supply is sufficient to power the DS1553 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at +25
C with the internal clock
oscillator running in the absence of V
CC
. Each DS1553 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a
level greater than V
PF
, the lithium energy source is enabled for battery backup operation.
INTERNAL BATTERY MONITOR
The DS1553 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags register (B4 of 1FF0h) is not writeable and should always be 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated, and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the V
CC
level. When V
CC
falls to the power-fail
trip point, the
RST
signal (open drain) is pulled low. When V
CC
returns to nominal levels, the
RST
signal
continues to be pulled low for 40ms to 200ms. The power-on reset function is independent of the RTC
oscillator and is therefore operational whether or not the oscillator is enabled.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
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CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
Table 2. Register Map
DATA
ADDRESS
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION/RANGE
1FFFh 10
Year
Year
Year
00-99
1FFEh X X X 10
M
Month
Month
01-12
1FFDh X X 10
Date
Date
Date
01-31
1FFCh X FT X X X
Day
Day
01-07
1FFBh X X 10
Hour
Hour
Hour
00-23
1FFAh X
10
Minutes
Minutes
Minutes
00-59
1FF9h
OSC
10 Seconds
Seconds
Seconds
00-59
1FF8h W R 10
Century
Century
Control
00-39
1FF7h WDS
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
1FF6h AE Y ABE Y Y Y Y
Y
Interrupts
1FF5h
AM4
Y
10 Date
Date
Alarm Date
01-31
1FF4h
AM3
Y
10 Hours
Hours
Alarm Hours
00-23
1FF3h
AM2
10 Minutes
Minutes
Alarm Minutes
00-59
1FF2h
AM1
10 Seconds
Seconds
Alarm Seconds
00-59
1FF1h Y Y Y Y Y Y Y
Y
Unused
1FF0h WF AF 0 BLF 0 0 0 0
Flags
X = Unused, Read/Writable Under Write and Read Bit Control
AE = Alarm Flag Enable
FT = Frequency Test Bit
Y = Unused, Read/Writable Without Write and Read Bit Control
OSC = Oscillator Start/Stop Bit
ABE = Alarm in Battery-Backup Mode Enable
W = Write Bit
AM1AM4 = Alarm Mask Bits
R = Read Bit
WF = Watchdog Flag
WDS = Watchdog Steering Bit
AF = Alarm Flag
BMB0BMB4 = Watchdog Multiplier Bits
0 = 0 Read Only
RB0RB1 = Watchdog Resolution Bits
BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The
OSC
bit is the
MSB of the Seconds register (B7 of 1FF9h). Setting it to 1 stops the oscillator; setting it to 0 starts the
oscillator. The DS1553 is shipped from Dallas Semiconductor with the clock oscillator turned off, with
the
OSC
bit set to 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
registers. This puts the external registers into a static state, allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h).
As long as a 1 remains in the Control register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
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