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090299
SPECIAL FEATURES
16384 bits Electrically Programmable Read
Only Memory (EPROM) communicates with
the economy of one signal plus ground
EPROM partitioned into sixty-four 256-bit
pages for randomly accessing packetized
data records
Each memory page can be permanently
write-protected to prevent tampering
Device is an "add only" memory where
additional data can be programmed into
EPROM without disturbing existing data
Architecture allows software to patch data by
superseding an old page in favor of a newly
programmed page
Reduces control, address, data, power, and
programming signals to a single data pin
8-bit family code specifies DS1985
communications requirements to reader
Reads over a wide voltage range of 2.8V to
6.0V from -40C to +85C; programs at
11.5V to 12.0V from -40C to +85C
COMMON iButton FEATURES
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alike
Multidrop controller for MicroLAN
Digital identification and information by
momentary contact
Chip-based data carrier compactly stores
information
Data can be accessed while affixed to object
Economically communicates to bus master
with a single digital signal at 16.3k bits per
second
Standard 16 mm diameter and 1-Wire
TM
protocol ensure compatibility with iButton
family
Button shape is self-aligning with cup-
shaped probes
Durable stainless steel case engraved with
registration number withstands harsh
environments
Easily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rim
Presence detector acknowledges when reader
first applies voltage
Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
F3 MICROCAN
TM
F5 MICROCAN
TM
DS1985
16-kbit Add-Only iButton
TM
www.dalsemi.com
DATA
GROUND
0.36
0.51
3.10
c
1993
YYWW REGISTERED RR
ED
0B
000000FBC52B
16.25
17.35
5.89
DATA
GROUND
0.36
0.51
c
1993
YYWW REGISTERED RR
6D
0B
000000FBD8B3
16.25
17.35
All dimensions shown in millimeters.
DS1985
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ORDERING INFORMATION
DS1985-F3
F3 MicroCan
DS1985-F5
F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P
Self-Stick Adhesive Pad
DS9101
Multi-Purpose Clip
DS9093RA
Mounting Lock Ring
DS9093F
Snap-In Fob
DS9092
iButton Probe
iButton DESCRIPTION
The DS1985 16-kbit Add-Only iButton is a rugged read/write data carrier that identifies and stores
relevant information about the product or person to which it is attached. This information can be accessed
with minimal hardware, for example a single port pin of a microcontroller.The DS1985 consists of a
factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-
bit Family Code (0BH) plus 16k bit of EPROM which is user-programmable. The power to program and
read the DS1985 is derived entirely from the 1-Wire communication line. Data is transferred serially via
the 1-Wire protocol which requires only a single data lead and a ground return. The entire device can be
programmed and then write-protected if desired. Alternatively, the part may be programmed multiple
times with new data being appended to, but not overwriting, existing data with each subsequent
programming of the device. Note: Individual bits can be changed only from a logical 1 to a logical 0,
never from a logical 0 to a logical 1. A provision is also included for indicating that a certain page or
pages of data are no longer valid and have been replaced with new or updated data that is now residing at
an alternate page address. This page address redirection allows software to patch data and enhance the
flexibility of the device as a standalone database. The 48-bit serial number that is factory-lasered into
each DS1985 provides a guaranteed unique identity which allows for absolute traceability. The durable
MicroCan package is highly resistant to harsh environments such as dirt, moisture, and shock. Its compact
button-shaped profile is self-aligning with cup-shaped receptacles, allowing the DS1985 to be used easily
by human operators or automatic equipment. Accessories permit the DS1985 to be mounted on printed
circuit boards, plastic key fobs, photo-ID badges, ID bracelets, and many other objects. Applications
include work-in-progress tracking, electronic travelers, access control, storage of calibration constants,
and debit tokens.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1985. The DS1985 has three main data components: 1) 64-bit lasered ROM, 2) 16384-bits
EPROM Data Memory, and 3) 704-bits EPROM Status Memory. The device derives its power for read
operations entirely from the 1-Wire communication line by storing energy on an internal capacitor during
periods of time when the signal line is high and continues to operate off of this "parasite" power source
during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply.
During programming, 1-Wire communication occurs at normal voltage levels and then is pulsed
momentarily to the programming voltage to cause the selected EPROM bits to be programmed. The 1-
Wire line must be able to provide 12 volts and 10 milliamperes to adequately program the EPROM
portions of the part. Whenever programming voltages are present on the 1-Wire line a special high
voltage detect circuit within the DS1985 generates an internal logic signal to indicate this condition. The
hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one
of the four ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM.
These commands operate on the 64-bit lasered ROM portion of each device and can singulate a specific
device if many are present on the 1-Wire line as well as indicate to the bus master how many and what
types of devices are present. The protocol required for these ROM Function Commands is described in
Figure 8. After a ROM Function Command is successfully executed, the memory functions that operate
on the EPROM portions of the DS1985 become accessible and the bus master may issue any one of the
DS1985
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Figure 8. After a ROM Function Command is successfully executed, the memory functions that operate
on the EPROM portions of the DS1985 become accessible and the bus master may issue any one of the
five Memory Function Commands specific to the DS1985 to read or program the various data fields. The
protocol for these Memory Function Commands is described in Figure 5. All data is read and written least
significant bit first.
DS1985 BLOCK DIAGRAM Figure 1
64-BIT LASERED ROM
Each DS1985 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3.)
The 64-bit ROM and ROM Function Control section allow the DS1985 to operate as a 1-Wire device and
follow the 1-Wire protocol detailed in the section "1-Wire Bus System." The memory functions required
to read and program the EPROM sections of the DS1985 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 8). The 1-
Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM,
3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully executed, the
bus master may then provide any one of the memory function commands specific to the DS1985 (Figure
5).
DS1985
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The 1-Wire CRC of the lasered ROM is generated using the polynomial X
8
+ X
5
+ X
4
+ 1. Additional
information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book
of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to 0. Then
starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of
the family code has been entered, then the serial number is entered. After the 48th bit of the serial number
has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the
shift register to all 0s.
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3
8-Bit CRC Code
48- Bit Serial Number
8-Bit Family Code (0BH)
MSB
LSB MSB
LSB MSB
LSB
DS1985
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16384 BITS EPROM
The memory map in Figure 4 shows the 16384 bits EPROM section of the DS1985 which is configured
as 64 pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading a 16-bit
CRC from the DS1985 that confirms proper receipt of the data and address. If the buffer contents are
correct, a programming voltage should be applied and the byte of data will be written into the selected
address in memory. This process ensures data integrity when programming the memory. The details for
reading and programming the 16384 bits EPROM portion of the DS1985 are given in the Memory
Function Commands section.
EPROM STATUS BYTES
In addition to the 16384 bits of data memory the DS1985 provides 704 bits of Status Memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS1985. The first 8 bytes of the EPROM Status Memory (addresses 000 to 007H)
contain the Write Protect Page bits which inhibit programming of the corresponding page in the 16384-bit
main memory area if the appropriate write protection bit is programmed. Once a bit has been
programmed in the Write Protect Page section of the Status Memory, the entire 32-byte page that
corresponds to that bit can no longer be altered but may still be read.
The next 8 bytes of the EPROM Status Memory (addresses 020 to 027H) contain the Write Protect bits
which inhibit altering the Page Address Redirection Byte corresponding to each page in the 16384-bit
main memory area.
The following 8 bytes within the EPROM Status Memory (addresses 040 to 047H) are reserved for use
by the iButton operating software TMEX. Their purpose is to indicate which memory pages are already in
use. Originally, all of these bits are unprogrammed, indicating that the device does not store any data. As
soon as data is written to any page of the device under control of TMEX, the bit inside this bitmap
corresponding to that page will be programmed to 0, marking this page as used. These bits are application
flags only and have no impact on the internal logic of the DS1985.
The next 64 bytes of the EPROM Status Memory (addresses 100H to 13FH) contain the Page Address
Redirection Bytes which indicate if one or more of the pages of data in the 16384 bits EPROM section
have been invalidated by software and redirected to the page address contained in the appropriate
redirection byte. The hardware of the DS1985 makes no decisions based on the contents of the Page
Address Redirection Bytes. These additional bytes of Status EPROM allow for the redirection of an entire
page to another page address, indicating that the data in the original page is no longer considered relevant
or valid. With EPROM technology, bits within a page can be changed from a logical 1 to a logical 0 by
programming, but cannot be changed back. Therefore, it is not possible to simply rewrite a page if the
data requires changing or updating, but with space permitting, an entire page of data can be redirected to
another page within the DS1985 by writing the one's complement of the new page address into the Page
Address Redirection Byte that corresponds to the original (replaced) page.
This architecture allows the user's software to make a "data patch" to the EPROM by indicating that a
particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.
To leave an authentic audit trail of data patches, it is recommended to also program the write protect bit
of the Page Address Redirection Byte, after the page redirection is programmed. Without this protection,
it is still possible to modify the Page Address Redirection Byte, making it point to a different memory
page than the true one.
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