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REV: 060805
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
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.
GENERAL DESCRIPTION
The DS80C400 network microcontroller offers the highest
integration available in an 8051 device. Peripherals include
a 10/100 Ethernet MAC, three serial ports, a CAN 2.0B
controller, 1-Wire
Master, and 64 I/O pins.
To enable access to the network, a full application-
accessible TCP IPv4/6 network stack and OS are provided
in the ROM. The network stack supports up to 32
simultaneous TCP connections and can transfer up to
5Mbps through the Ethernet MAC. Its maximum system-
clock frequency of 75MHz results in a minimum instruction
cycle time of 54ns. Access to large program or data
memory areas is simplified with a 24-bit addressing
scheme that supports up to 16MB of contiguous memory.
To accelerate data transfers between the microcontroller
and memory, the DS80C400 provides four data pointers,
each of which can be configured to automatically increment
or decrement upon execution of certain data pointer-related
instructions. The DS80C400's hardware math accelerator
further increases the speed of 32-bit and 16-bit multiply
and divide operations as well as high-speed shift,
normalization, and accumulate functions.
The High-Speed Microcontroller User's Guide and the High-Speed
Microcontroller User's Guide: Network Microcontroller Supplement
should be used in conjunction with this data sheet. Download
both at:
www.maxim-ic.com/user_guides
.
APPLICATIONS
Industrial Control/Automation
Environmental Monitoring
Data Converters (Serial-
to-Ethernet, CAN-to-
Ethernet)
Network Sensors
Remote Data Collection
Equipment
Vending
Home/Office Automation
Transaction/Payment
Terminals
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS80C400-FNY
-40C to +85C
100 LQFP
DS80C400-FNY+
-40C to +85C
100 LQFP
+ Denotes lead-free/RoHS-compliant device.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
Magic Packet is a registered trademark of Advanced Micro
Devices, Inc.
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
FEATURES
High-Performance Architecture
Single 8051 Instruction Cycle in 54ns
DC to 75MHz Clock Rate
Flat 16MB Address Space
Four Data Pointers with Auto-Increment/
Decrement and Select-Accelerate Data Movement
16/32-Bit Math Accelerator
Multitiered Networking and I/O
10/100 Ethernet Media Access Controller (MAC)
CAN 2.0B Controller
1-Wire Net Controller
Three Full-Duplex Hardware Serial Ports
Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O
Pins)
Robust ROM Firmware
Supports Network Boot Over Ethernet Using DHCP
and TFTP
Full, Application-Accessible TCP/IP Network Stack
Supports IPv4 and IPv6
Implements UDP, TCP, DHCP, ICMP, and IGMP
Preemptive, Priority-Based Task Scheduler
MAC Address can Optionally be Acquired from IEEE-
Registered DS2502-E48
10/100 Ethernet Mac
Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC
(10Mbps) Interfaces Allow Selection of PHY
Low-Power Operation
Ultra-Low-Power Sleep Mode with Magic Packet
and Wake-Up Frame Detection
8kB On-Chip Tx/Rx Packet Data Memory with Buffer
Control Unit Reduces Load on CPU
Half- or Full-Duplex Operation with Flow Control
Multicast/Broadcast Address Filtering with VLAN
Support
Full-Function CAN 2.0B Controller
15 Message Centers
Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks
Media Byte Filtering to Support DeviceNet
TM
, SDS, and
Higher Layer CAN Protocols
Auto-Baud Mode and SIESTA Low-Power Mode
Integrated Primary System Logic
16 Total Interrupt Sources with Six External
Four 16-Bit Timer/Counters
2x/4x Clock Multiplier Reduces Electromagnetic
Interference (EMI)
Programmable Watchdog Timer
Oscillator-Fail Detection
Programmable IrDA Clock
Features continued on page 32.
Pin Configuration appears at end of data sheet.
DS80C400
Network Microcontroller
www.maxim-ic.com
DS80C400 Network Microcontroller
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Input Pin Relative to Ground..................................................................-0.5V to +5.5V
Voltage Range on Any Output Pin Relative to Ground......................................................-0.5V to (V
CC3
+ 0.5)V
Voltage Range on V
CC3
Relative to Ground.............................................................................-0.5V to +3.6V
Voltage Range on V
CC1
Relative to Ground.............................................................................-0.3V to +2.0V
Operating Temperature Range............................................................................................-40C to +85C
Junction Temperature...........................................................................................................+150C max
Storage Temperature Range.............................................................................................-55C to +160C
Soldering Temperature...................................................................See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Note 1)
(V
CC3
= 3.0V to 3.6V, V
CC1
= 1.8V 10%, T
A
= -40C to +85C.)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
Supply Voltage (V
CC3
) (Note 2)
V
CC3
3.0 3.3 3.6 V
Power-Fail Warning (V
CC3
) (Note 3)
V
PFW3
2.85 3.00 3.15 V
Power-Fail Reset Voltage (V
CC3
) (Note 3)
V
RST3
2.76
2.90 3.05 V
Active Mode Current (V
CC3
) (Note 4)
I
CC3
16
35
mA
Idle Mode Current (V
CC3
) (Note 4)
I
IDLE3
7 15
mA
Stop Mode Current (V
CC3
) (Not 4)
I
STOP3
1 10
mA
VCC3
Stop Mode Current, Bandgap Enabled (V
CC3
) (Note 4)
I
SPBG3
100
150
mA
Supply Voltage (V
CC1
) (Note 2)
V
CC1
1.62 1.8 1.98 V
Power-Fail Warning (V
CC1
) (Note 5)
V
PFW1
1.52 1.60 1.68 V
Power-Fail Reset Voltage (V
CC1
) (Note 5)
V
RST1
1.47
1.55 1.63 V
Active Mode Current (V
CC1
) (Note 4)
I
CC1
27
50
mA
Idle Mode Current (V
CC1
) (Note 4)
I
IDLE1
20 40
mA
Stop Mode Current (V
CC1
) (Note 4)
I
STOP1
0.2 10 mA
VCC1
Stop Mode Current, Bandgap Enabled (V
CC1
) (Note 4)
I
SPBG1
0.2 10 mA
Input Low Level
V
IL1
0.8
V
Input Low Level for XTAL1, RST, OW
V
IL2
1.0
V
Input High Level
V
IH1
2.0 V
Input High Level for XTAL1, RST, OW
V
IH2
2.4 V
Output Low Current for Port 1, 37 at V
OL
= 0.4V
I
OL1
6
10 mA
Output Low Current for Port 0, 2, TX_EN, TXD[3:0], MDC, MDIO,
RSTOL, ALE, PSEN, and Ports 37 (when used as any of the following:
A21A0,
WR, RD, CE0-7, PCE0-3) at V
OL
= 0.4V (Note 6)
I
OL2
12
20 mA
Output Low Current for OW,
OWSTP at V
OL
= 0.4V
I
OL3
10
16 mA
Output High Current for Port 1, 37 at V
OH
= V
CC3
- 0.4V (Note 7)
I
OH1
-75
-50
mA
Output High Current for Port 1, 37 at V
OH
= V
CC3
- 0.4V (Note 8)
I
OH2
-8 -4
mA
Output High Current for Port 0, 2, TX_EN, TXD[3:0], MDC, MDIO,
RSTOL, ALE, PSEN, and Ports 37 (when used as any of the following:
A21A0,
WR, RD, CE0-7, PCE0-3) at V
OH
= V
CC3
- 0.4V (Notes 6, 9)
I
OH3
-16
-8
mA
Input Low Current for Port 17 at 0.4V (Note 10)
I
IL
-50
-20
-10
mA
Logic 1-to-0 Transition Current for Port 1, 37 (Note 11)
I
TL
-650
-400
mA
Input Leakage Current, Port 0 Bus Mode, V
IL
= 0.8V (Note 12)
I
TH0
20
50 200
mA
Input Leakage Current, Port 0 Bus Mode, V
IH
= 2.0V (Note 12)
I
TL0
-200
-50 -20
mA
Input Leakage Current, Input Mode (Note 13)
I
L
-15
0 15
mA
RST Pulldown Resistance
R
RST
50
100 200 k
W
Note 1: Specifications to -40C are guaranteed by design and not production tested.
Note 2: The user should note that this part is tested and guaranteed to operate down to V
CC3
= 3.0V and V
CC1
= 1.62V, while the reset
thresholds for those supplies, V
RST3
and V
RST1
respectively, may be above or below those points. When the reset threshold for a given
supply is greater than the guaranteed minimum operating voltage, that reset threshold should be considered the minimum operating
point since execution ceases once the part enters the reset state. When the reset threshold for a given supply is lower than the
guaranteed minimum operating voltage, there exists a range of voltages for either supply, (V
RST3
< V
CC3
< 1.62V) or (V
RST1
< V
CC1
<
3.0V), where the processor's operation is not guaranteed, and the reset trip point has not been reached. This should not be an issue in
DS80C400 Network Microcontroller
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most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be
desirable to use a more accurate external reset.
Note 3: While the specifications for V
PFW3
and V
RST3
overlap, the design of the hardware makes it such that this is not possible. Within the ranges
given, there is a guaranteed separation between these two voltages.
Note 4: Current measured with 75MHz clock source on XTAL1, V
CC3
= 3.6V, V
CC1
= 2.0V,
EA and RST = 0V, Port0 = V
CC3
, all other pins
disconnected.
Note 5: While the specifications for V
PFW1
and V
RST1
overlap, the design of the hardware makes it such that this is not possible. Within the ranges
given, there will be a guaranteed separation between these two voltages.
Note 6: Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory
interface function (in parentheses) are as follows: Port 3.6-3.7 (
WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-6.5
(
CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).
Note 7: This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (V
OH2
). This I/O
pin state can be achieved by applying RST = V
CC3.
Note 8: The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot
circuit drives the ports hard for two clock cycles. A weak pullup device (V
OH1
) remains in effect following the strong two-clock cycle
drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O
mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.
Note 9: Port 3 pins 3.6 (
WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition of
either
WR or RD from a 0 to a 1.
Note 10: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to
1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition
current.
Note 11: Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a
maximum at approximately 2V.
Note 12: During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the Port
0 pin is driven by an external memory source.
Note 13:
The OW pin (when configured to output a 1) at V
IN
= 5.5V,
EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],
CRS, COL, MDIO) at V
IN
= 3.6V.
AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)
(Note 1)
(V
CC3
= 3.0V to 3.6V, V
CC1
= 1.8V 10%, T
A
= -40C to +85C.)
75MHz VARIABLE
CLOCK
PARAMETER SYMBOL
MIN MAX
MIN
MAX
UNITS
External Crystal Frequency
4
40
16
37.5
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
1 / t
CLK
11
18.75
MHz
External Clock Oscillator Frequency
DC
75
Clock Mutliplier 2X Mode
16
37.5
Clock Multiplier 4X Mode
1 / t
CLK
11
18.75
MHz
ALE Pulse Width
15.0
t
CLCL
+ t
CHCL
- 5
ns
Port 0 Instruction Address Valid to ALE Low
t
LHLL
1.7 t
CHCL
- 5
ns
Address Hold After ALE Low
t
AVLL
4.7 t
CLCH
- 2
ns
ALE Low to Valid Instruction In
t
LLAX
14.3 2t
CLCL
+ t
CLCH
- 19
ns
ALE Low to
PSEN Low
t
LLIV
3.7 t
CLCH
- 3
ns
PSEN Pulse Width
t
LLPL
21.7 2t
CLCL
- 5
ns
PSEN Low to Valid Instruction In
t
PLPH
9.7
2t
CLCL
-17
ns
Input Instruction Hold After
PSEN
t
PLIV
0
0
ns
Input Instruction Float After
PSEN
t
PXIX
8.3
t
CLCL
- 5
ns
Port 0 Address to Valid Instruction In
t
AVIV0
21.0
3t
CLCL
- 19
ns
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
t
AVIV2
27.7 3t
CLCL
+ t
CLCH
- 19
ns
PSEN Low to Address Float
t
PLAZ
0
0
ns
Note 1: Specifications to -40C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3: t
CLCL
, t
CLCH
, t
CHCL
are time periods associated with the internal system clock and are related to the external clock (t
CLK
) as defined in the
External Clock Oscillator (XTAL1) Characteristics table.
Note 4: The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
Note 5: All signals guaranteed with load capacitance of 80pF except Port 0, Port 2,
ALE, PSEN, RD, and WR with 100pF. The following signals,
when configured for memory interface, are also characterized with 100pF loading: Port 4 (
CE0-3, A16A19), Port 5.45.7 ( PCE0-3),
Port 6.06.5 (
CE4-7, A20, A21), Port 7 (demultiplexed mode A0A7).
Note 6: For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid bus
contention.
Note 7: References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
DS80C400 Network Microcontroller
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EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS
PARAMETER SYMBOL
MIN
MAX
UNITS
Clock Oscillator Period
t
CLK
See External Clock
Oscillator Frequency
Clock Symmetry at 0.5 x V
CC3
t
CH
0.45
t
CLK
0.55
t
CLK
ns
Clock Rise Time
t
CR
3
ns
Clock Fall Time
t
CF
3
ns
EXTERNAL CLOCK DRIVE
SYSTEM CLOCK TIME PERIODS (t
CLCL
, t
CHCL
, t
CLCH
)
SYSTEM CLOCK SELECTION
SYSTEM CLOCK HIGH (t
CHCL
) AND
SYSTEM CLOCK LOW (t
CLCH
)
4X/
2X
CD1 CD0
SYSTEM CLOCK
PERIOD t
CLCL
MIN MAX
1 0 0
t
CLK
/ 4
0.45 (t
CLK
/ 4)
0.55 (t
CLK
/ 4)
0 0 0
t
CLK
/ 2
0.45 (t
CLK
/ 2)
0.55 (t
CLK
/ 2)
X 1 0
t
CLK
0.45
t
CLK
0.55
t
CLK
X 1 1
256
t
CLK
0.45 (256 t
CLK)
0.55 (256 t
CLK)
Note 1:
Figure 20
shows a detailed description and illustration of the system clock selection.
Note 2: When an external clock oscillator is used in conjunction with the default system clock selection (CD1:CD0 = 10b), the
minimum/maximum system clock high (t
CHCL
) and system clock low (t
CLCH
) periods are directly related to clock oscillator duty cycle.
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(V
CC3
= 3.0V to 3.6V, V
CC1
= 1.8V 10%, T
A
= -40
C to +85C.)
PARAMETER SYMBOL MIN
MAX
UNITS
STRETCH VALUES
C
ST
(MD2:0)
t
CLCL
+ t
CHCL
- 5
C
ST
= 0
2t
CLCL
- 5
1
C
ST
3
MOVX ALE Pulse Width
t
LHLL2
6t
CLCL
- 5
ns
4
C
ST
7
t
CHCL
- 5
C
ST
= 0
t
CLCL
- 6
1
C
ST
3
Port 0 MOVX Address Valid
to ALE Low
t
AVLL2
5t
CLCL
- 6
ns
4
C
ST
7
t
CLCH
- 2
C
ST
= 0
t
CLCL
- 2
1
C
ST
3
Port 0 MOVX Address Hold
after ALE Low
t
LLAX2
and t
LLAX3
5t
CLCL
- 2
ns
4
C
ST
7
2t
CLCL
- 5
C
ST
= 0
RD Pulse Width (P3.7 or
PSEN)
t
RLRH
(4 x C
ST
) t
CLCL
- 3
ns
1
C
ST
7
2t
CLCL
- 5
C
ST
= 0
WR Pulse Width (P3.6)
t
WLWH
(4 x C
ST
) t
CLCL
- 3
ns
1
C
ST
7
2t
CLCL
- 17
C
ST
= 0
RD (P3.7 or PSEN) Low to
Valid Data In
t
RLDV
(4 x C
ST
) t
CLCL
- 17
ns
1
C
ST
7
Data Hold After
RD (P3.7 or
PSEN) High
t
RHDX
-2
ns
t
CR
t
CF
t
CLK
t
CH
XTAL1
t
CL
DS80C400 Network Microcontroller
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PARAMETER SYMBOL MIN
MAX
UNITS
STRETCH VALUES
C
ST
(MD2:0)
t
CLCL
- 5
C
ST
= 0
2t
CLCL
- 5
1
C
ST
3
Data Float After
RD (P3.7 or
PSEN) High
t
RHDZ
6t
CLCL
- 5
ns
4
C
ST
7
2t
CLCL
+ t
CLCH
- 19
C
ST
= 0
(4 x C
ST
+ 1) t
CLCL
- 19
1
C
ST
3
ALE Low to Valid Data In
t
LLDV
(4 x C
ST
+ 5) t
CLCL
- 19
ns
4
C
ST
7
3t
CLCL
- 19
C
ST
= 0
(4 x C
ST
+ 2)t
CLCL
- 19
1
C
ST
3
Port 0 Address to Valid Data
In
t
AVDV0
(4 x C
ST
+ 10)t
CLCL
- 19
ns
4
C
ST
7
3t
CLCL
+ t
CLCH
- 19
C
ST
= 0
(4 x C
ST
+ 2)t
CLCL
+ t
CLCH
-
19
1
C
ST
3
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
Data In
t
AVDV2
(4 x C
ST
+ 10)t
CLCL
+ t
CLCH
-
20
ns
4
C
ST
7
t
CLCH
- 3
t
CLCH
+ 6
C
ST
= 0
t
CLCL
- 3
t
CLCL
+ 6
1
C
ST
3
ALE Low to (
RD or PSEN) or
WR Low
t
LLWL
5t
CLCL
- 3
5t
CLCL
+ 6
ns
4
C
ST
7
t
CLCL
- 5
C
ST
= 0
2t
CLCL
- 6
1
C
ST
3
Port 0 Address to (
RD or
PSEN) or WR Low
t
AVWL0
10t
CLCL
- 6
ns
4
C
ST
7
t
CLCL
+ t
CLCH
- 5
C
ST
= 0
2t
CLCL
+ t
CLCH
- 5
1
C
ST
3
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (
RD or PSEN)
or
WR Low
t
AVWL2
10t
CLCL
+ t
CLCH
- 5
ns
4
C
ST
7
Data Valid to
WR Transition
t
QVWX
0
ns
t
CLCL
- 4
C
ST
= 0
2
CLCL
- 7
1
C
ST
3
Data Hold After
WR High
t
WHQX
6t
CLCL
- 7
ns
4
C
ST
7
RD Low to Address Float
t
RLAZ
(Note
2)
0
C
ST
7
0 7
C
ST
= 0
t
CLCL
- 3
t
CLCL
+ 4
1
C
ST
3
(
RD or PSEN) or WR High to
ALE
t
WHLH
5t
CLCL
- 3
5t
CLCL
+ 4
ns
4
C
ST
7
t
CHCL
-5
t
CHCL
+ 13
C
ST
= 0
t
CLCL
+ t
CHCL
- 5
t
CLCL
+ t
CHCL
+ 13
1
C
ST
3
(
RD or PSEN) or WR High to
Port 4 CE or Port 5 PCE
High
t
WHLH2
5t
CLCL
+ t
CHCL
- 5
5t
CLCL
+ t
CHCL
+ 13
ns
4
C
ST
7
Note 1: Specifications to -40C are guaranteed by design and not production tested.
Note 2: For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
Note 3: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t
CLCL
, t
CLCH
, t
CHCL
are time
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE,
PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (
CE0-3, A16A19), Port 5.45.7
(
PCE0-3), Port 6.06.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0A7).
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams are to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
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