ESS Technology, Inc.
SAM0191-052901
1
ES3880
Video CD MPEG Processor
Product Brief
DESCRIPTION
The ES3880 Video CD MPEG processor is ESS' third
generation highly integrated, optimal quality, and cost-
effective single chip solution for Video CD players. The
ES3880 is the best quality available for both video and
audio and easily passes the highest graded level for the
China VCD standard
.
The ES3880 integrates MPEG-1
video and audio processing and a full-fledged MPEG
system bit stream parser. The ES3880 can be used as a
microcontroller to provide system control, while also
performing such basic video operations as arbitrary
scaling and video filtering. The MPEG-1 system layer
bitstream is decoded at up to 9 Mb/s at Standard
Intermediate Format (SIF) resolution with a picture rate of
30 frames per second. Two channels of MPEG-1 Layer 1
or Layer 2 audio are decoded simultaneously.
The ES3880 supports SmartScale advanced scaling
techniques, along with SmartStream for audio and video
error concealment, and SmartZoom for enabling in/out
zooming of a particular area of a still picture or movie.
Additional features include DiscScan, TrackScan, QuickScan, On-
Screen-Display (OSD), Karaoke, Playback Control (PBC)
for Video CD 2.0, and entertainment game software.
System control and house-keeping functions (keypad and
remote control) are also provided.
The ES3880 can be implemented with the ES3883 Video
CD Video Encoder, which integrates most of the analog
discrete components required for a Video CD player.
Figure 1 shows a typical Video CD system using the
ES3880 and the companion ES3883 video encoder. When
the ES3880 and ES3883 are used in the design,
enhanced support for 3DSound and SurroundSound is
realized, along with support for interactive games.
The ES3880 is available in an industry-standard 100-pin
Plastic Quad Flat Pack (PQFP) package.
FEATURES
Programmable Multimedia Processor (PMP) architecture
MPEG-1 audio/video decoder and system parser
CD block decoder functions
Video interlacing hardware
Color Space Conversion (CSC)
STC interpretation and video/audio Phase-lock Loop (PLL)
Supports both 8- and 16-bit YUV output
256/384 frame sampling frequency for audio system clock
Programmable master clock for external audio DAC
Independent bit clock for audio transmit and receive
SmartScale video scaling supports X- and Y-axis interpolation
SmartZoom supports 4X picture enlargement and reduction
SmartStream supports audio and video bit stream error
concealment
SmartVocal: cancels the vocal on an audio-CD
Karaoke function
Video Fader for fading video image (in and out)
On-screen-Display (OSD)
Playback Control (PBC) for Video CD 2.0
Trick mode functions (Repeat, Goto, Set A-B, etc.)
DiscScan, TrackScan, and QuickScan
Video CD 1.1 and 2.0, and Audio CD compatible
Power management
3.6 V power supply with 5 V tolerant I/O's
100-pin PQFP
Can be used with either serial or parallel interfaces
Figure 1 ES3880 System Block Diagram
Video CD
ES3880
MPEG
Processor
Keypad
Panel
Interface
CD-ROM
DRAM
256K X 16
ROM
Echo
Audio DAC
NTSC/PAL
Encoder
Interrupt
I/O Expansion
Audio
Video
DSC
Television
Speakers
IR
Microphone
Companion Chip
ES3883 Video CD
2
SAM0191-052901
ESS Technology, Inc.
ES3880 PRODUCT BRIEF
ES3880 PINOUT
ES3880 PINOUT
Figure 2 shows the ES3880 device pinout.
Figure 2 ES3880 Device Pinout
LA1
LD5
LD4
LD6
LA7
LA6
LD7
LW
R
#
LO
E#
LCS0#
LA2
LD3
DB
US
1
2
DB
US
1
1
VD
D
LD1
LD2
VD
D
R
AS#
DW
E
#
DA
0
DA
1
DA
2
DA
3
DA
4
DA
5
DA
6
DA
8
DB
US
0
DB
US
1
DB
US
2
DB
US
3
DB
US
4
DB
US
5
DB
US
6
DB
US
8
DB
US
9
DB
US
1
0
LA3
LA0
LD0
AU
X7
AU
X5
AU
X6
LCS3#
LCS1#
LA4
LA5
DB
US
7
DA
7
1
31
30
51
50
80
81
100
2
3
4
5
6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
ES3880
100-pin PQFP
AUX4
AUX3
AUX2
AUX1
AUX0
PCLK
CPUCLK
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
VDD
DB
US
1
5
DB
US
1
4
DB
US
1
3
VSYNC
HSYNC
VSS
PCLK2X
RE
S
E
T
#
VS
S
LA1
1
LA13
LA14
LA15
LA16
LA17
ACLK
AOUT/SEL_PLL0
ATCLK
ATFS/SEL_PLL1
DA9/DOE#
AIN
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
VSS
LA10
LA9
LA8
VS
S
VPP
LA12
ARCLK
ESS Technology, Inc.
SAM0191-052901
3
ES3880 PRODUCT BRIEF
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES3880.
Table 1 ES3880 Pin Descriptions List
Name
Number
I/O
Definition
VDD
1, 31, 51
I
3.3V power supply.
RAS#
2
O
Row address strobe.
DWE#
3
O
DRAM write enable.
DA[8:0]
12:4
O
DRAM multiplexed row and column address bus.
DBUS[15:0]
28:13
I/O
DRAM data bus.
RESET#
29
I
System reset.
VSS
30, 50, 80, 100
I
Ground.
YUV[7:0]
39:32
O
YUV[7:0] 8-bit video data bus.
VSYNC
40
I/O
Vertical sync.
HSYNC
41
I/O
Horizontal sync.
CPUCLK
42
I
RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00 to bypass
PLL.
PCLK2X
43
I/O
Doubled 54 MHz pixel clock.
PCLK
44
I/O
27 MHz pixel clock.
AUX[7:0]
54:52, 49:45
I/O
Auxiliary control pins 7:0. AUX0 and AUX1 are open collectors.
LD[7:0]
62:55
I/O
RISC interface data bus.
LWR#
63
O
RISC interface write enable.
LOE#
64
O
RISC interface output enable.
LCS[3,1,0]#
65, 66, 67
O
RISC interface chip select.
LA[17:0]
87:82, 79:68
O
RISC interface address bus.
VPP
81
I
5.0V power supply.
ACLK
88
I/O
Master clock for external audio DAC.
AOUT
89
O
Audio interface serial data output when selected.
SEL_PLL0
I
System and DSCK output clock frequency selection at reset time. The matrix below lists
the available clock frequencies and their respective PLL bit settings.
ATCLK
90
I/O
Audio transmit bit clock.
ATFS
91
O
Audio transmit frame sync.
SEL_PLL1
I
Refer to the description and matrix for SEL_PLL0 pin 89.
DA9
92
O
DRAM multiplexed row and column address line 9.
DOE#
O
DRAM output enable.
AIN
93
I
Audio serial data input.
ARCLK
94
I
Audio receive bit clock.
ARFS
95
I
Audio receive frame sync.
TDMCLK
96
I
TDM serial clock.
SEL_PLL1
SEL_PLL0
DCLK
0
0
Bypass PLL (input mode)
0
1
54 MHz (output mode) Default
1
0
67.5 MHz (output mode)
1
1
81.0 MHz (output mode)
4
2000 ESS Technology, Inc. All rights reserved.
SAM0191-052901
ES3880 PRODUCT BRIEF
BLOCK DIAGRAM
No part of this publication may be reproduced, stored in a
retrieval system, transmitted, or translated in any form or
by any means, electronic, mechanical, manual, optical, or
otherwise, without the prior written permission of ESS
Technology, Inc.
ESS Technology, Inc. makes no representations or
warranties regarding the content of this document.
All specifications are subject to change without prior
notice.
ESS Technology, Inc. assumes no responsibility for any
errors contained herein.
(P) U.S. Patent 4,384,169 and others, other patents
pending.
SmartScaleTM, SmartStreamTM, and
VideoDrive
TM are
trademarks of ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/
IEC. References to MPEG2 in this document refer to the
ISO/IEC 13818-1.
All other trademarks are owned by their respective
holders and are used for identification purposes only.
BLOCK DIAGRAM
Figure 3 provides a functional block diagram of the
ES3880.
Figure 3 ES3880 Functional Block Diagram
ORDERING INFORMATION
TDMDR
97
I
TDM serial data receive.
TDMFS
98
I
TDM frame sync.
CAS#
99
O
DRAM column address strobe.
Table 1 ES3880 Pin Descriptions List (Continued)
Name
Number
I/O
Definition
Part Number
Description
Package
ES3880
Video CD MPEG Processor
100-pin PQFP
DRAM DMA
Controller
DRAM Interface
Huffman
Decoder
64x32 ROM
32x32 SRAM
Registers
On Screen
MPEG
Video Output
2Kx32 ROM
512x32 SRAM
Processor
RISC
Serial Audio
TDM
Processor
Display
Interface
Interface
AOUT
ARFS
AIN
ATCLK
ACLK
AUX[7:0]
CPUCLK
DBUS[15:0]
CAS#
DOE#
RAS#
DWE#
HSYNC
LCS3#, LCS#[1:0]
LOE#
LA[17:0]
LWR#
LD[7:0]
DA[9:0]
PCLK2X
PCLK
RESET#
ATFS
SEL_PLL[1:0]
TDMCLK
TDMDR
VSYNC
YUV[7:0]
Serial
Audio
Interface
TDM
Interface
DRAM
AUX
Screen
Display
Misc.
Processor
Interface
TDMFS
ARCLK
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