AT1008F

8-Channel ADPCM Processor

Atelic Systems Inc.

AT1008F Application Note

8-Channel ADPCM Processor

Description

The AT1008F is an eight full-duplex channel ADPCM processor. It follows G.726 ITU Standard for ADPCM

compression for 40k, 32k, 24k and 16k with selectable

-law and A-law input/output. This chip can operate on 16

channels of PCM to ADPCM compression, 16 channels of ADPCM to PCM decompression, 8 channels of full-
duplex operation in an 8KHz frame basis, or any combination of M-channels of compression plus N-channels of
decompression when M+N

16. Through its three wire serial port, the chip can be dynamically programmed to

perform the ADPCM algorithm at different bit rates, idle or reset of the algorithm. It can also be programmed to set
up different input/output time bit-slots, or to select, (1) bypass without compression at 64kbps PCM, (2) idle, or (3)
reset of the algorithm.

Features

ADPCM coding and decoding with bypass mode

· µ

-law or A-law PCM selectable

ITU-T G.726 compatible at 40kbps, 32kbps, 24kbps and 16kbps

8 full duplex channels of operation, or any combination of (M encodes + N decodes) where M+N

16.

Up to 8 synchronous signals for direct interface with popular combo/codec.

Flexible on-chip time bit-slot assignment circuits.

Internal clock generator and frame sync. generator

The attributes for each individual channel such as compression rate, input/output time bit-slots, etc. can be
independently configured through the three wire serial port.

On-chip power-on reset

28-pin DIP or SOP packages

The two clock pins (CLKA and CLKP) used as PCM/ADPCM data clocks and the two pins (FSX and FSY)
used for the two Frame Sync signals can be programmed to become either as input pins or as output pins. (The
defaults are as input pins).

Applications

Wireless or wireline telephone systems

PBX systems

T1/E1applications

Digital voice storage and recording devices

AT1008F

8-Channel ADPCM Processor

PIN Description

See figure 1 for PIN assignment.

PIN

SYMBOL

TYPE

DESCRIPTION

XIN

X Channel Data In. Sampled on the falling edge of CLKX during selected

time slots.

FSX/SYNC1

I/O

X Channel Frame Sync. Master X Channel Frame Sync. signal followed
by the first time slot of transmission. It can be either input or output by
initial setup sequence.
Sync 1. Frame sync. for 1

CODEC.

XOUT

X Channel Data Out. Updated on the rising edge of CLKX during
selected time slots.

YIN

Y Channel Data In. Sampled on the falling edge of CLKY during selected
time slots.

FSY

I/O

Y Channel Frame Sync. Master X Channel Frame Sync. signal followed
by the first time slot of transmission. It can be either input or output by
initial setup sequence.

YOUT

Y Channel Data Out. Updated on the rising edge of CLKY during

selected time slots.

RSTZ

Reset. Low active signal to force chip reset.

13
12

XTAL1/MCLK

XTAL2

Crystal In & Out. 10MHz source or 14.318 (10.000) MHz Crystal
connected.

CLKP

I/O

PCM Clock. It can be either input created by external control circuit, or
output generated by internal control circuit.

CLKA

I/O

ADPCM Clock. It can be either input created by external control circuit, or
output generated by internal control circuit.

15
11
10

9
8
5
1

SYNC2
SYNC3
SYNC4
SYNC5
SYNC6
SYNC7
SYNC8

O
O
O
O
O
O
O

Sync 2. Frame sync. for 2

CODEC.

Sync 3. Frame sync. for 3

CODEC.

Sync 4. Frame sync. for 4

CODEC.

Sync 5. Frame sync. for 5

CODEC.

Sync 6. Frame sync. for 6

CODEC.

Sync 7. Frame sync. for 7

CODEC.

Sync 8. Frame sync. for 8

CODEC.

4
3

TM1
TM0

I
I

TM1 & TM0 . Tie to Ground for normal operation.

7
6

A1
A0

I
I

A1 & A0. Address ID key for 3-wire serial port. If match, 3-wire serial port
can be enabled for configuration.

SDI

Serial Data In. Data for configuration on the fly by 3-wire serial port.
Sampled on the rising edge of SCLK with LSB first.

SCLK

Serial Clock. Used to write to the 3-wire serial port registers.

SCSZ

Serial Port Chip Select. Low active to enable 3-wire serial port.

VDD

Power. 3.3 Volts.

14
19

Vss1
Vss2

-
-

Ground. 0 Volt.

AT1008F

8-Channel ADPCM Processor

SYNC8 1

RSTZ 2

TM0 3

TM1 4

SYNC7 5

A0 6

A1 7

SYNC6 8

SYNC5 9

SYNC4 10

SYNC3 11

XTAL2 12

XTAL1 13

VSS1 14

VDD

YIN

CKLA

FSY

YOUT

SCSZ

SDI

SCLK

XOUT

VSS2

FSX/SYNC1

CLKP

XIN

SYNC2

Figure 1. AT1008F pin assignment.

Xin

Yout

Fsx
CLKP(PCM)
Xtal

TM0
TM1
A0
A1

Clock

Control

RSTZ VDD VSS

3-wire generator

SCSZ SCLK SDI

PCM Full duplex ADPCM
I/O Quad I/O

Transcoder

Xout

Yin

Fsy
CLKA
(ADPCM)

SYNC 2

SYNC 8

Figure 2. AT1008F functional block diagram.

AT1008F

8-Channel ADPCM Processor

Power consumption

The AT1008F is powered by a 3.3 V source and draws 60-70 mA at full operation and < 1 mA in powerdown

mode.

AT1008F chip initialization

There are two different classes of resets available on the AT1008F chip. For the default reset, hold the RSTZ pin

low for 50 ms, this reset will bring the chip to a functioning default state. In the default state, the following
parameters are set:

Pins FSX, FSY, CLKP, CLKA default as input pins (chip will receive these signals from external source).

A second type of reset involving the use of the 3-wire serial interface can also be used direct the pin I/O
configurations of FSX, FSY, CLKP, and CLKA during reset.

SCLK

SCSZ

SDI

RSTZ

Byte 1

Byte 2

Figure 3. AT1008F FSX, FSY, CLKP, CLKA I/O direction configuration.

FSX, FSY, CLKP, CLKA I/O direction setup pattern (byte 1):

B7 (MSB)

B0 (LSB)

FSX, FSY, CLKP, CLKA I/O direction setup pattern (byte 2):

B7 (MSB)

B0 (LSB)

where:

value

description

CLKP set as output

CLKP set as input

value

description

CLKA set as output

CLKA set as input

AT1008F

8-Channel ADPCM Processor

value

description

FSX set as output

FSX set as input

value

description

FSY set as output

FSY set as input

Configuration sequence: Write 2-bytes to the 3-wire serial interface when RSTZ is held active low. The first byte
written must be 0xA5 as a key to enter the AT1008F FSX, FSY, CLKP, CLKA I/O direction configuration mode; if
the first byte hasn't been written correctly, all four pins will remain set as input pins (default reset value).

Chip ID Setup
The two Chip ID pins A0 and A1 (Pins 6,7) should also be set during chip initialization. The "Chip ID" is used to
differentiate between AT1008F chips in a system that uses more than one AT1008F chip. When using only one
chip, it is recommended to tie A0 and A1 to digital zero. Thus, when programming the AT1008F chip, you can use
the Chip ID = `00' to substitute wherever you see A1, A0.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AT1008F

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AT1008F