MX88L284AEC
Revision: 1.06A
2
Table of Contents
GENERAL DESCRIPTION ...................................................................................................................................4
APPLICATIONS .....................................................................................................................................................4
FEATURES .............................................................................................................................................................4
G
ENERAL
F
EATURES
...............................................................................................................................................4
I
NPUT
.....................................................................................................................................................................5
O
UTPUT
.................................................................................................................................................................5
CPU I
NTERFACE
.....................................................................................................................................................6
M
EMORY
I
NTERFACE
..............................................................................................................................................6
P
OWER
...................................................................................................................................................................6
O
THERS
.................................................................................................................................................................6
CHIP BLOCK DIAGRAM .....................................................................................................................................7
SYSTEM BLOCK DIAGRAM FOR LCD MONITOR (TTL AND PANELLINK/LVDS INTERFACED)........7
SYSTEM DIAGRAM W/O FRAME BUFFER......................................................................................................8
SYSTEM DIAGRAM FOR DIGITAL INPUT INTERFACE ...............................................................................8
PIN CONFIGURATIONS.......................................................................................................................................9
GENERAL DESCRIPTION .................................................................................................................................10
VIP (V
IDEO
I
NPUT
P
ROCESSOR
) F
UNCTION
D
ESCRIPTION
.......................................................................................10
MIU (M
EMORY
I
NTERFACE
U
NIT
) F
UNCTIONAL
D
ESCRIPTION
...............................................................................10
M
EMORY
C
ONFIGURATION
T
ABLE
.........................................................................................................................11
VOP (V
IDEO
O
UTPUT
P
ROCESSOR
) F
UNCTION
D
ESCRIPTION
..................................................................................11
BIU (B
US
I
NTERFACE
U
NIT
) F
UNCTION
D
ESCRIPTION
............................................................................................11
PIN DESCRIPTION..............................................................................................................................................12
CPU I
NTERFACE
P
INS
: (15
PINS
) ...........................................................................................................................12
DRAM I
NTERFACE
P
INS
: (52
PINS
) ** 3.3 V
OLT
I
NTERFACE
*** ..........................................................................12
I
NPUT
I
NTERFACE
P
INS
: (30
PINS
)..........................................................................................................................13
LCD I
NTERFACE
P
INS
: (53
PINS
) ...........................................................................................................................13
OSD
INTERFACE
P
INS
: (6
PINS
) .............................................................................................................................14
I
NTERNAL
VCG I
NTERFACE
P
INS
: (2
PINS
) ............................................................................................................14
O
THER
I
NTERFACE
P
INS
: (9
PINS
) ..........................................................................................................................14
E
XTERNAL
C
LOCK
I
NPUT
I
NTERFACE
P
INS
: (2) .....................................................................................................15
P
OWER
P
INS
: ........................................................................................................................................................15
AC CHARACTERISTICS ....................................................................................................................................16
AC
TIMINGS IF THE LOAD OF ALL OUTPUT PINS IS
5~20
P
F........................................................................................16
1.
I
NPUT SIGNAL
........................................................................................................................................16
2. O
UTPUT SIGNAL
................................................................................................................................................19
E
XTERNAL
OSD
SIGNAL
.......................................................................................................................................20
3. D
IRECT
CPU I
NTERFACE
...................................................................................................................................21
4. S
ERIAL
B
US
I
NTERFACE
.....................................................................................................................................22
5. F
RAME MEMORY
(SDRAM/SGRAM) I
NTERFACE
..............................................................................................23
6. E
XTERNAL
C
LOCK
I
NPUT
I
NTERFACE
.................................................................................................................25
MX88L284AEC
Revision: 1.06A
3
DC CHARACTERISTICS ....................................................................................................................................26
1. E
NVIRONMENTAL SPECIFICATION
: .....................................................................................................................26
2. S
TANDARD
DC S
PECIFICATION FOR
3.3 V
OLTS
O
PERATION
:...............................................................................26
DIMENSIONS .......................................................................................................................................................27
MX88L284AEC
Revision: 1.06A
4
General Description
The MX88L284AEC is a highly integration chip for Flat Panel Display application. It's fully
compatible with MX88L284. With Macronix's Smartscaling
TM
-2 filter, it provides high quality
scaled video image and format conversion capability.
Applications
LCD monitor
LCD projector
Other Flat Panel Display Application (DMD, PDP, PALC ...
)
Features
General Features
Converts NTSC/PAL and PC video signal into flat panel display device timing and
resolution
Provide Full frame buffer, reduce frame buffer (w/ compression) and frame buffer less
optional architecture.
Built-in memory and output clock generator
Built-in OSD generator with 64 ROM font, and 64 programmable RAM fonts
Provide 90 degree rotation for internal OSD to support portrait direction display
Arbitrary scaling from 1/32 to 32 times with filters (SmartScaling
TM
2
+
Technology)
Support Auto-tracking and Auto-position capabilities (SmartTracking
TM
Technology)
Support Auto-gain capability for input image
Support Flip and Mirror capabilities
On-chip brightness and contrast adjustments
On-chip
correction for panel compensation
Support dynamic dithering capability to make 18 bit video as good as 24 bit quality
Support H/V Sync. Polarity and pulse width information for mode detection
Support two types of CPU interface (direct and serial bus)
MX88L284AEC
Revision: 1.06A
5
Provide 1 pixel/clock and 2 pixel/clock output to connect TFT LCD panel directly
Built-in Color space converter for video decoder input
Support configurable SDRAM/SGRAM (x0 x1 and x2 ) for different resolution to
minimize the system cost
Support Composite Sync. input
Support DPMS and H/V sync. Interrupt
Input
PC video up to 1024 x 768 @ 85Hz
Support YCrCb422, RGB888 mode (Interlaced and Non-interlaced)
Support Philips, Samsung, and Techwell NTSC/PAL video decoder in 16 bit interface
Support TTL clock input
Support input H/V sync. polarity and odd/even field detection
Support digital input capability
Output
Support TFT LCD panel in following resolution and frequency
Resolution
800x600
1024x768
Horizontal frequency (KHz)
20 ~ 55
20 ~ 70
Vertical frequency (Hz)
50 ~ 75
50 ~ 75
Dot clock (MHz)
32.5 ~ 60
25 ~ 80
Remark:
The Max. output resolution and frequency is depend on memory bus bandwidth, input resolution/frequency and image
size.
Single (18/24) and Dual (36/48) bit RGB data output
Support Inverse, delay adjustment and frequency adjustment for LCD panel clock
(LCKA and LCKB)
Support programmable H/V sync. and LDTG timing for LCD panel
Support OSD MUX capability for On-Screen-Display chip input
Built-in OSD generator
Built-in YCrCb to RGB color space converter
Built-in programmable Brightness and Contrast control
MX88L284AEC
Revision: 1.06A
6
Built-in programmable gamma correction table
Support Horizontal and Vertical position adjustment
Support SmartScaling
TM
-2
+
or double scan capability for Interlaced input
Support Edge Filter control
CPU Interface
Support direct 8 bit uP interface and serial bus (high-speed) interface
Support CPU line write/read and flush screen capability
Memory Interface
Optimized single buffer design
Support Memory clock fine-tune and frequency programmable capabilities
Support 32/16 bit bus width
Support SDRAM/SGRAM x0 x1 and x2 configuration
Support power down mode
Support DRAM self test
Power
Power supplier: 3.3 volt power supplier
Power Consumption: less than 1.5W
Others
Support power down mode
Power on strapped input for system configuration
Support GPIO pins to minimized the system cost.
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