Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.

303 S. Technology Court,

Phone: (800) SMI-MMIC

http://www.sirenza.com

Broomfield, CO 80021

1 EDS-104013 Rev D

Case Flange = Ground

ESD
Protection

Sirenza Microdevices' SLD-1083CZ is a robust 4 Watt high perfor-
mance LDMOS transistor designed for operation from to 2700MHz. It is
an excellent solution for applications requiring high linearity and effi-
ciency at a low cost. The SLD-1083CZ is typically used in the design of
driver stages for power amplifiers, repeaters, and RFID applica-
tions.The power transistor is fabricated using Sirenza's latest, high per-
formance LDMOS II process.

RF Specifications

Symbol

Parameter

Unit

Min

Typ

Max

Frequency

Frequency of Operation

MHz

2700

Gain

3 Watt CW, 902-928MHz

Efficiency

Drain Efficiency at 3 Watt CW, 915MHz

IRL

Input Return Loss, 3 Watt Output Power, 915MHz

-9.5

-12

Linearity

Order IMD at 3 Watt PEP (Two Tone), 915MHz

dBc

-30

-26

1dB Compression (P

1dB

), 915MHz

Watt

IS-95, 9 Ch Fwd, Offset=750KHz, ACPR Integrated Bandwidth,

ACPR=-55dB

dBm

IS-95, 9 Ch Fwd, Offset=750KHz, ACPR Integrated Bandwidth,

ACPR=-45dB

dBm

Thermal Resistance (Junction-to-Case)

ºC/W

SLD-1083CZ

4 Watt Discrete LDMOS FET in
Ceramic Package

Product Features

Applications

4 Watt Output P

1dB

Single Polarity Supply Voltage

High Gain: 18 dB at 915 MHz

High Efficiency: 47% at 10W CW

XeMOS II LDMOS

Integrated ESD Protection, Class 1B

Base Station PA driver

Repeaters

RFID

Military Communication

GSM/CDMA

Product Description

RoHS Compliant

Package

Green

Test Conditions V

= 28.0V, I

= 30mA, T

Flange

= 25ºC

Functional Schematic Diagram

DC Specifications

Symbol

Parameter

Unit

Min

Typical

Max

Forward Transconductance @ 30mA I

mA / V

150

Threshold

=3mA, V

=28V

Volts

4.2

Breakdown

1mA V

current

Volts

iss

Input Capacitance (Gate to Source) V

=0V V

=28V

5.2

rss

Reverse Capacitance (Gate to Drain) V

=0V V

=28V

0.2

oss

Output Capacitance (Drain to Source) V

=0V V

=28V

3.2

DSon

Drain to Source Resistance, V

=10V V

=250mV

3.0

SLD-1083CZ 2700MHz 4 Watt LDMOS FET

303 S. Technology Court

Phone: (800) SMI-MMIC

http://www.sirenza.com

Broomfield, CO 80021

EDS-104013 Rev D

Pin Description

Pin #

Function

Description

Gate

Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant

bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the

maximum input power or voltage.

Drain

Transistor RF output and drain bias voltage. Typical voltage 28V.

Flange

Source, Gnd

Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for

optimum thermal and RF performance. See mounting instructions for recommendation.

Absolute Maximum Ratings

Parameters

Value

Unit

Drain Voltage (V

)

Volts

Gate Voltage (V

)

Volts

RF Input Power

+30

dBm

Load Impedance for Continuous Operation

Without Damage

10:1

VSWR

Output Device Channel Temperature

+200

ºC

Lead Temperature During Solder Reflow

+270

ºC

Operating Temperature Range

-20 to +90

ºC

Storage Temperature Range

-40 to +100

ºC

Operation of this device beyond any one of these limits may

cause permanent damage. For reliable continuous operation

see typical setup values specified in the table on page one.

Caution: ESD Sensitive

Appropriate precaution in handling, packaging
and testing devices must be observed.

Case Flange = Ground

ESD
Protection

Pin Diagram

Pin 1

Pin 2

Quality Specifications

Parameter

Description

Unit

Typical

ESD Rating

Human Body Model

Volts

750

MTTF

C Leadframe, 200

C Channel

Hours

1.2 X 10

Note 1:
Gate voltage must be applied to V

lead concurrently or after

application of drain voltage to prevent potentially destructive
oscillations. Bias voltages should never be applied to the tran-
sistor unless it is properly terminated on both input and output.

Note 2:
The required V

corresponding to a specific I

will vary from

device to device due to the normal die-to-die variation in thresh-
old voltage withLDMOS transistors.

Note 3:
The threshold voltage (V

GSTH

) of LDMOS transistors varies with

device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature Compensation.

SLD-1083CZ 2700MHz 4 Watt LDMOS FET

303 S. Technology Court

Phone: (800) SMI-MMIC

http://www.sirenza.com

Broomfield, CO 80021

EDS-104013 Rev D

Typical Performance Curves in 900 MHz Application Circuit

CW Gain, Efficiency vs Pout

Vdd=28V, Idq=50mA, Freq=915 MHz

Pout (W)

i
n

(

)

ffici

c
y (

)

Gain
Efficiency

2 Tone Gain, Efficiency, Linearity vs Pout

Vdd=28V, Idq=50mA, Freq=915 MHz, Delta F=1 MHz

Pout (W PEP)

a
i
n
(

d
B

)
,
E

f
f
i
ci

e
n
cy (

)

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

(

d
B

c
)

Gain

Efficiency

IM3

IM5

IM7

2 Tone Gain, Efficiency, Linearity and IRL vs Frequency

Vdd=28V, Idq=50mA, Pout=3W PEP, Delta F=1 MHz

900

905

910

915

920

925

Frequency (MHz)

i
n

)
,
E

f
f
i
c
i
e

c
y
(%

)

-60

-50

-40

-30

-20

-10

(
d

c
)
,
IR

(

)

Gain

Efficiency

IM3

IM5

IM7

IRL

CW Gain, Efficiency, IRL vs Frequency

Vdd=28V, Idq=50mA, Pout=3W

900

905

910

915

920

925

Frequency (MHz)

a
i
n
(

d
B),

f
i
c
i
e
n
c
y

(%

)

-20

-16

-12

-8

-4

p
u
t R

e
tu

o
s
s
(

d
B

)

Gain
Efficiency
IRL

To receive Gerber files, DXF drawings, and assembly recommendations for the test board with fixture, contact applications
support at

support@sirenza.com.

SLD-1083CZ 2700MHz 4 Watt LDMOS FET

303 S. Technology Court

Phone: (800) SMI-MMIC

http://www.sirenza.com

Broomfield, CO 80021

EDS-104013 Rev D

Bill of Materials - 900 MHz Application Circuit

Reference Designation

Description

Mfg

Mfg part #

CAP 68PF250V 5% 0603

ATC

600S680JT250XT

CAP 18PF250V 2% 0604

ATC

600S180GT250XT

IND, 16 nH 5% 0603

coilcraft

0603CS-160XJB

IND, 9.5 nH 5% nH 0603

coilcraft

0603CS-9N5XJB

C10

CAP 0.1 UF 16V 10% 0603

AVX

0603YG104ZA2A

C11, C20

CAP 1000 PF 50V 10% 603

AVX

06035C102KAT2A

C12

CAP 68PF 250V 5% 603 LF

ATC

600S680JT250XT

C18

CAP 10 UF 35V 20% TAN T ELECT

Kemet

T494D106M035AS

C19, C22

CAP 0.1 UF 50V 10% 805

Panasonic

ECJ2YB1H104K

J1, J2

Connector SMA END 0.037

Johnson

142-0751-821

Connector MTA SMD R/A 2 PIN

Amp

640455-2

RES 324 1/16W 1% 603

Panasonic

ERJ-3EKF3240V

RES 0 Ohm jumper 805

Panasonic

ERJ6GEY0R00V

POT TRIM 500 OHM 2MM

Panasonic

EVM-2WSX80B52

R30

RES 49.9 1/16W 1% 603

Panasonic

ERJ-EKF49R9V

RES 130 1/16W 1% 603

Panasonic

ERJ-3EKF1300V

RES 210 1/16W 1% 603

Phillips

9C06031A2100FKHFT

RES 0 1/16W 5% 603

Panasonic

ERJ-3GSY0R00V

R90

RES 1.0K 1/16W 1% 603

Panasonic

ERJ-3EKF1001V

RT1

THERMISTOR 100K 5% 603

Panasonic

ERT-J1VV104J

IC VOLT REG 100 MA 5 V SOT-23

National

LM3480IM3-5.0

6 Screws

SCREW #2-56 PHILIPS PAN HEAD

various

6 Washers

WASHER #2 FLAT SS

various

PCB

PCB, 30 mils thick Dk=3.48

Rogers

4350

Heatsink

machined alumininum

various

To receive Gerber files, DXF drawings, and assembly recommendations for the test board with fixture, contact applications
support at

support@sirenza.com.

900 MHz Application Circuit

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SLD-1083CZ

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SLD-1083CZ