October 1997
FDC6302P
Digital FET, Dual P-Channel
General Description Features
Absolute Maximum Ratings
T
A
= 25
o
C unless other wise noted
Symbol
Parameter
FDC6302P
Units
V
DSS
Drain-Source Voltage
-25
V
V
GSS
Gate-Source Voltage
-8
V
I
D
Drain Current
- Continuous
-0.12
A
- Pulsed
-0.5
P
D
Maximum Power Dissipation
(Note 1a)
0.9
W
(Note 1b)
0.7
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6.0
kV
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
140
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
60
C/W
FDC6302P Rev.C
-25 V, -0.12 A continuous, -0.5 A Peak.
R
DS(ON)
= 13
@ V
GS
= -2.7 V
R
DS(ON)
= 10
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple PNP digital transistors (IMHxA series) with
one DMOS FET.
These Dual P-Channel logic level enhancement mode field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This device
has been designed especially for low voltage applications as a
replacement for digital transistors in load switchimg applications.
Since bias resistors are not required this one P-Channel FET
can replace several digital transistors with different bias resistors
like the IMBxA series.
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
5
6
3
2
1
4
1997 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 A
-25
V
BV
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
I
D
= -250 A, Referenced to 25
o
C
-20
mV /
o
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -20 V, V
GS
= 0 V
-1
A
T
J
= 55C
-10
A
I
GSS
Gate - Body Leakage Current
V
GS
= -8 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
/
T
J
Gate Threshold Voltage Temp. Coefficient
I
D
= -250 A, Referenced to 25
o
C
1.9
mV /
o
C
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 A
-0.65
-1
-1.5
V
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -2.7 V, I
D
= -0.05A
10.6
13
V
GS
= -4.5 V, I
D
= -0.2 A
7.9
10
T
J
=125C
12
18
I
D(ON)
On-State Drain Current
V
GS
= -2.7 V, V
DS
= -5 V
-0.05
A
g
FS
Forward Transconductance
V
DS
= -5 V, I
D
= -0.2 A
0.135
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
11
pF
C
oss
Output Capacitance
7
pF
C
rss
Reverse Transfer Capacitance
1.4
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -6 V, I
D
= -0.2 A,
V
GS
= -4.5 V, R
GEN
= 50
5
12
ns
t
r
Turn - On Rise Time
8
16
ns
t
D(off)
Turn - Off Delay Time
9
18
ns
t
f
Turn - Off Fall Time
5
10
ns
Q
g
Total Gate Charge
V
DS
= -5 V, I
D
= - 0.2 A,
V
GS
= -4.5 V
0.22
0.31
nC
Q
gs
Gate-Source Charge
0.12
nC
Q
gd
Gate-Drain Charge
0.05
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
-0.7
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.7 A
(Note 2)
-1
-1.3
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
FDC6302P Rev.C
b. 180
O
C/W on a 0.005 in
2
of pad
of 2oz copper.
a. 140
O
C/W on a 0.125 in
2
pad of
2oz copper.
FDC6302P Rev.C
0
1
2
3
4
0
0.05
0.1
0.15
0.2
-V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN-SOURCE CURRENT (A)
V = -5.0V
GS
DS
D
-4.5
-2.7
-2.5
-2.0
-3.0
-3.5
-4.0
0
0.05
0.1
0.15
0.2
0.5
1
1.5
2
-I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
R , NORMALIZED
V = -2.0 V
GS
D
DS(ON)
-3.5
-4.5
-2.7
-2.5
-3.0
-4.0
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 3. On-Resistance Variation
with Temperature.
-3
-2.5
-2
-1.5
-1
-0.5
-1
-0.75
-0.5
-0.25
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = -5V
DS
GS
D
T = -55C
J
125C
25C
Figure 5. Transfer Characteristics.
0
0.2
0.4
0.6
0.8
1
1.2
0.0001
0.01
0.1
0.5
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0V
GS
SD
S
Figure 6. Body Diode Forward Voltage
Variation with Source Current and
Temperature.
Figure 4. On Resistance Variation with
Gate-To- Source Voltage.
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE (OHMS)
J
R , NORMALIZED
DS(ON)
V = -2.7V
GS
I = -0.05A
D
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
-V ,GATE TO SOURCE VOLTAGE (V)
,DRAIN-SOURCE ON-RESISTANCE
GS
R
DS(ON)
I = -0.05A
D
T = 25C
A
125 C
FDC6302P Rev.C
Figure 10. Single Pulse Maximum Power
Dissipation.
0.1
0.3
1
2
5
10
15
25
1
2
3
5
10
15
25
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0 V
GS
C
oss
C
rss
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical And Thermal Characteristics
0
0.1
0.2
0.3
0.4
0.5
0
2
4
6
8
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
V = -5V
DS
-10
-15
I = -0.2A
D
1
2
5
10
20
40
0.01
0.02
0.05
0.1
0.2
0.5
0.8
- V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN CURRENT (A)
RDS(ON) LIMIT
D
DC
DS
1s
100ms
10ms
V = -2.7V
SINGLE PULSE
R =See Note 1b
T = 25C
GS
A
JA
1ms
0.01
0.1
1
10
100
300
0
1
2
3
4
5
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =See note 1b
T = 25C
JA
A
0.0001
0.001
0.01
0.1
1
10
100
300
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
r(t), NORMALIZED EFFECTIVE
Duty Cycle, D = t / t
1
2
R (t) = r(t) * R
R = See Note 1b
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
Figure 11. Transient Thermal Response Curve
.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.
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