2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
RFD16N06LESM
16A, 60V, 0.047 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
a modern process. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
relay drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V to 5V range, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.
Formerly developmental type TA49027.
Features
16A, 60V
r
DS(ON)
= 0.047
Temperature Compensating PSPICE
Model
Can be Driven Directly from CMOS, NMOS, TTL
Circuits
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
- TB334 "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD16N06LESM*
TO-252AA
16N06LE
NOTE: When ordering, use the entire part number. Add suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e.,
RFD16N06LESM9A.
*RFD16N06LESM is only availabe in tape and reel.
D
G
S
JEDEC TO-252AA
GATE
SOURCE
DRAIN (FLANGE)
Data Sheet
September 2002
2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFD16N06LESM
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
60
V
Drain to Gate Voltage (R
GS
= 20k
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
60
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
+10, -8
V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
16
Refer to Peak Current Curve
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
0.606
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V, Figure 11
60
-
-
V
Gate Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A, Figure 10
1
-
3
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 55V, V
GS
= 0V
-
-
1
A
V
DS
= 50V, V
GS
= 0V, T
C
= 150
o
C
-
-
250
A
Gate to Source Leakage Current
I
GSS
V
GS
= +10, -8V
-
-
10
A
Drain to Source On Resistance (Note 2)
r
DS(ON)
I
D
= 16A, V
GS
= 5V
-
-
0.047
Turn-On Time
t
ON
V
DD
= 30V, I
D
= 16A, R
L
= 1.88
,
V
GS
= 5V, R
GS
= 5
Figures 16, 17
-
-
100
ns
Turn-On Delay Time
t
d(ON)
-
11
-
ns
Rise Time
t
r
-
60
-
ns
Turn-Off Delay Time
t
d(OFF)
-
48
-
ns
Fall Time
t
f
-
35
-
ns
Turn-Off Time
t
OFF
-
-
115
ns
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 10V
V
DD
= 48V,
I
D
= 16A, R
L
= 3
Figures 18, 19
-
51
62
nC
Gate Charge at 5V
Q
g(5)
V
GS
= 0V to 5V
-
29
35
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 1V
-
1.8
2.6
nC
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
Figure 12
-
1350
-
pF
Output Capacitance
C
OSS
-
300
-
pF
Reverse Transfer Capacitance
C
RSS
-
90
-
pF
Thermal Resistance Junction to Case
R
JC
-
-
1.65
o
C/W
Thermal Resistance Junction to Ambient
R
JA
TO-251AA, TO-252AA
-
-
80
o
C/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage (Note 2)
V
SD
I
SD
= 16A
-
-
1.5
V
Diode Reverse Recovery Time
t
rr
I
SD
= 16A, dI
SD
/dt = 100A/
s
-
-
125
ns
NOTES:
2. Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature.
RFD16N06LESM
2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 6. SATURATION CHARACTERISTICS
T
C
, CASE TEMPERATURE (
o
C)
25
50
75
100
125
150
175
0
P
O
W
E
R DI
S
S
IP
A
T
ION
MUL
T
IP
L
I
E
R
0
0
0.2
0.4
0.6
0.8
1.0
1.2
T
C
, CASE TEMPERATURE (
o
C)
I
D
, DRAIN
CURRENT
(
A
)
20
10
5
0
25
50
75
100
125
150
175
15
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
10
100
I
D,
DRAIN C
URRENT
(
A
)
1
10
200
100
1ms
V
DSS
MAX = 60V
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
100
s
10ms
T
C
= 25
o
C
T
J
= MAX RATED
t, PULSE WIDTH (s)
I
DM
, PEAK CURRENT
CAP
ABIL
I
T
Y
(
A
)
500
100
10
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
V
GS
= 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
(
)
175 - T
C
150
V
GS
= 10V
T
C
= 25
o
C
t
AV
,
TIME IN AVALANCHE (ms)
0.01
0.1
1
10
I
AS
,
A
V
AL
ANCHE C
URRENT
(
A
)
1
10
100
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 150
o
C
STARTING T
J
= 25
o
C
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT
(
A
)
0
20
40
60
0
1.5
3.0
4.5
6.0
7.5
V
GS
= 3V
V
GS
= 4V
V
GS
= 4.5V
V
GS
= 5V
80
100
V
GS
= 10V
PULSE DURATION = 80
s
T
C
=25
o
C
DUTY CYCLE = 0.5% MAX.
RFD16N06LESM
2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs
TEMPERATURE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Typical Performance Curves
Unless Otherwise Specified (Continued)
25
o
C
V
GS
, GATE TO SOURCE VOLTAGE (V)
0
3.0
4.5
6.0
7.5
1.5
0
20
40
60
I
D(O
N
)
,
ON ST
A
T
E DRAIN
CURRENT
(
A
)
-55
o
C
80
100
175
o
C
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
, JUNCTION TEMPERATURE (
o
C)
NORM
AL
IZ
ED D
RAIN T
O
SOURCE
0
0.5
1.0
1.5
2.0
2.5
-80
-40
0
40
80
120
160
200
V
GS
= 5V, I
D
= 16A
PULSE DURATION = 80
s
ON RE
SIST
ANCE
DUTY CYCLE = 0.5% MAX.
T
J
, JUNCTION TEMPERATURE (
o
C)
-80
-40
0
40
80
120
200
160
0
0.5
1.0
1.5
2.0
NORMA
L
IZ
E
D
GA
T
E
THRESHO
L
D V
O
L
T
A
G
E
V
GS
= V
DS
, I
D
= 250
A
2.0
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
200
NO
RM
AL
IZ
E
D
DRAIN T
O
SOURCE
BREAKDO
WN V
O
L
T
A
G
E
T
J
, JUNCTION TEMPERATURE (
o
C)
I
D
= 250
A
2000
1500
500
0
0
5
10
15
20
25
C
,
CAP
A
C
IT
ANCE
(
p
F
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
RSS
1000
C
ISS
C
OSS
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
V
GS
= 0V, f = 1MHz
60
45
30
15
0
20
I
G REF
(
)
I
G ACT
(
)
----------------------
t, TIME (
s)
80
I
G REF
(
)
I
G ACT
(
)
----------------------
5.00
3.75
2.50
1.25
0
V
DS
,
DR
AIN T
O
SOURCE V
O
L
T
A
G
E
(
V
)
V
GS
,
GA
T
E
T
O
S
O
URC
E
V
O
L
T
A
G
E
(V
)
V
DD
= BV
DSS
V
DD
= BV
DSS
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
R
L
= 3.75
I
G(REF)
= 0.65mA
V
GS
= 5V
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
RFD16N06LESM
2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
Test Circuits and Waveforms
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORMS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
OR Q
g(5)
V
GS
= 5V FOR
Q
g(TOT)
V
GS
= 20V
V
DS
V
GS
I
g(REF)
0
0
V
GS
= 1V FOR
L
2
DEVICES
L
2
DEVICES
V
GS
= 10V
V
GS
= 10V FOR
L
2
DEVICES
RFD16N06LESM
PDF 
ZIP