Product Flyer
December 96
MB86680B
Version 2.05
ATM Switch Element (SRE)
FML/NPD/SRE/FL/1203
Copyright 1996 Fujitsu Microelectronics Limited
Page 1 of 6
The Fujitsu MB86680B is a Self-Routing switch Element for
use in ATM switch fabrics.
The device is organized as a 4 x 4 switch with separate input
and output ports running at 155Mbps for matrix expansion.
The switch element has non-blocking inputs with a 75 cell
buffer per output port. Multiple devices can be used to build
larger switch fabrics.
The device is suited to applications in a variety of customer
premises equipment such as ATM hubs and network access
controllers.
FEATURES
Highly integrated 4x4 structure
Active matrix expansion ports for row and column interconnect
Selectable high and low priority output queues
Output port buffer capacity of 75 cells, which can be divided into a 50 cell low priority queue and a 25
cell high priority queue
Multicast support
Selective cell discard based on CLP bit and selectable queue level
Selectable Forward Explicit Congestion Notification (FECN) function
Flexible tag processing to allow a variety of switch fabric architectures to be realized
All input / output ports operate at up to 20MHz using an 8-bit data format
Separate input clock signals for each interface
Separate cell synchronization signals for each port
JTAG pins compliant to IEEE1149.1 are provided
Fabricated in 0.8 micron CMOS technology with CMOS/TTL compatible I/O and single +5V power
supply
PLASTIC PACKAGE
SQFP-176
December 96Version 2.05
FML/NPD/SRE/FL/1203
MB86680B ATM Switch Element (SRE)
Copyright 1996 Fujitsu Microelectronics Limited
Page 2 of 6
Expansion
Ports
MUX
Input Ports
Regeneration Ports
Fig. 1 - MB86680B Block Diagram
Output Holding Registers
Configuration
Manager
Expansion Port
Holding
Registers
Input Port
Holding
Registers
Address Filter
Output
Ports
JTAG Interface
JTAG
Buffer Timing
& Control
M
U
X
75 Cell
Output
Buffer
Buffer Timing
& Control
M
U
X
75 Cell
Output
Buffer
Buffer Timing
& Control
M
U
X
75 Cell
Output
Buffer
Buffer Timing
& Control
M
U
X
75 Cell
Output
Buffer
December 96Version 2.05
FML/NPD/SRE/FL/1203
MB86680B ATM Switch Element (SRE)
Copyright 1996 Fujitsu Microelectronics Limited
Page 3 of 6
General
The SRE is offered as a basic building block suitable for the construction
of a variety of ATM switch fabrics. The SRE provides an aggregate 75 cell
storage capacity per port. A flexible output queue configuration permits
the allocation of a separate 25 cell High priority queue per port suitable
for CBR traffic. On chip Explicit Forward Congestion Indication (EFCI)
mechanisms permit early indication of congestion within the switch fabric.
The pin assignment on the SRE minimises the interconnect and real
estate required for larger switch configurations.
Traffic Routing
Flexible variations of a 3 byte routing tag appended to the 53 byte ATM
cell permit the SRE to carry out Point to Point and Point to Multi-Point
(Multicast) connections.Variants of the 3 byte routing tag permit the cell
to be marked as a High priority cell or as a Low priority cell subject to
selective cell discard.
The selective cell discard feature allows traffic congestion within the
switch fabric to be alleviated by carrying out the selective discard of Low
priority cells.
The format of the SRE's routing tag permits larger switch fabrics to be
constructed without the need for further address translation being
required.
EFCI operation
Traffic congestion within individual switch elements may be signalled by
the selective marking of the Congestion Indication (CI) bit in the ATM
cell's Payload Type (PT) field.
JTAG
The SRE provides boundary scan test circuitry fully compliant with IEEE
1149.1 (JTAG). The SRE's JTAG circuitry permits easier board level
testing to be carried out by allowing the signal pins on the device to form
a serial scan chain around the device. JTAG test modes are controlled by
accessing an internal test access port controller, which is in turn
controlled by the 4 provided test access ports.
December 96Version 2.05
FML/NPD/SRE/FL/1203
MB86680B ATM Switch Element (SRE)
Copyright 1996 Fujitsu Microelectronics Limited
Page 4 of 6
I01
I02
I32
I33
I34
I64
B
C
E
F
SRE
SRE
SRE
SR
E2E
E1
STAGE 1
STAGE 2
O01
O02
O32
O33
O34
O64
SRE
SRE
SRE
SRE
SRE
SRE
SR
E2E
E1
SRE
SRE
SRE
Fig. 2 - Example of a large switch configuration
December 96Version 2.05
FML/NPD/SRE/FL/1203
MB86680B ATM Switch Element (SRE)
Copyright 1996 Fujitsu Microelectronics Limited
Page 5 of 6
Fig. 3 - MB86680B I/O Block Diagram
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit.
TDO
Expansion ports
Input
Regeneration
INITOUT
OP1
OP2
OP3
OP4
IP1
IP2
IP3
IP4
RP1
RP2
RP3
RP4
RESET
IPCLK
OPCLK
EPCLK
INITIN
JTAG
port
TMS
TCK
EP1
EP2
EP3
EP4
MB86680B
Output ports
TDI
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