HD151011
Dual BCD Programmable Counter
with Synchronous Preset Enable
ADE-205-100(Z)
Rev 0
April 1995
The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to
max 99 counts and synchronous preset (
SPE) input can preset the data. When the count value is 0, the next
clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse,
whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid
crystal and general-use divider.
Features
High speed operation
tpd (CLK or
CLK to Q) = 35 ns (typ)
High output current
Fanout of 10 LS TTL Loads
Wide operating voltage
Vcc = 2 to 6 V
Low supply current (Ta = 25
C)
Icc (Static) = 4
A (max)
HD151011
2
Function Table
Control Inputs
CLR
PR
SPE
C/
T
Mode
Operation Description
H
H
H
X
Generally count
Down count at the rise edge of clock (CLK),
Down count at the fall edge of clock (
CLK
)
X
X
L
X
Synchronous preset
Jn data is preset at the rise of clock (CLK),
the fall of clock (
CLK
)
--
--
--
H
--
Clock inputs (CLK,
CLK
) is CMOS level
--
--
--
L
--
Clock inputs (CLK,
CLK
) is TTL level
L
H
--
--
Initialize of Q output
Initialize of Q = "L"
H
L
--
--
Initialize of Q output
Initialize of Q = "H"
H: High level
L: Low level
Z: Immaterial
--: Irrespective of condition
1. Synchronous preset (
SPE
) input can set max 99 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
4. Clock inputs (CLK,
CLK
) is selectable CMOS level (V
CC
= 2.0 to 6.0 V) and TTL level (V
CC
= 4.5 to 5.5V)
(Jn, C/
T
, PR, CLR and
SPE
inputs are CMOS level)
Note:
Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB)
HD151011
3
Pin Arrangement
15
16
17
18
V
CC
1
2
3
4
5
6
7
14
CO
GND
(Top view)
8
13
19
20
J 0
(Test 1)*
J 1
J 2
J 3
J 4
J 5
J 6
9
10
J 7
12
11
(Test 2)*
C / T
CLK
CLK
Q
PR
SPE
CLR
* Pins 18 and 19 are for function test only and should be open.
Pin Description
Pin Name
Pin Description
Input pins
J0 to J7
Count data input for option
C/
T
Level change input for CLK,
CLK
(CMOS level or TTL level)
CLK,
CLK
Clock inputs
CLK : Rise edge trigger
CLK
: Fall edge trigger
SPE
Preset input for Jn data
PR
Preset input for D-type Flip Flop (Initialize "L" at Q output)
CLR
Clear input for D-type Flip Flop (Initialize "H" at Q output)
Output pins
CO
Output for BCD decimal counter
Q
Output for D-type Flip Flop
HD151011
4
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
V
CC
0.5 to 7.0
V
Input / output voltage
V
IN
/ V
OUT
0.5 to V
CC
+0.5
V
VCC, GND current
I
CC
, I
GND
50
mA
Output current / pin
I
OUT
25
mA
Power dissipation
P
T
757
mW
Storage temperature
Tstg
65 to 150
C
Input diode current
I
IK
20
mA
Output diode current
I
OK
20
mA
Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
2. All voltage values except for differential input voltage are with respect to network ground
terminal.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
2
--
6
V
Input / output voltage
V
IN
/
OUT
0
--
V
CC
V
Operating temperature
Topr
40
--
+85
C
Input rise / fall time
*1
V
CC
= 2.5 V
tr, tf
0
--
1000
ns
V
CC
= 4.5 V
0
--
500
V
CC
= 5.5 V
0
--
400
Note:
1. This item guarantees maximum limit when one input switches.
HD151011
5
Logic Diagram
C/T
CLK
CLK
CLK
BCD decimal counter
SPE
PR
CLR
PR
D
CK
Q
Q
CLR
Q
CO
CO
SPE
J0
J0
J1
J1
J2
J2
J3
J3
J4
J4
J5
J5
J6
J6
J7
J7
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