FEATURES
High-speed access time: 9, 10, 12, 15 ns
CMOS low power operation
--
594 mW (max.) operating @ 9 ns
--
36 mW (max.) CMOS standby
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Available in 100-pin LQFP
DESCRIPTION
The
ICSI
IS61LV6424 is a high-speed, static RAM organized
as 65,536 words by 24 bits. It is fabricated using
ICSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 9 ns with low power consumption.
When CE1 is HIGH and CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE1, CE2, and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory.
The IS61LV6424 is packaged in the JEDEC standard
100-pin 14*20*1.4mm LQFP.
FUNCTIONAL BLOCK DIAGRAM
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
IS61LV6424
64K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
Integrated Circuit Solution Inc.
S2-95
AHSR012-0D
A0-A14
CE1
CE2
OE
WE
64K x 24
MEMORY ARRAY
ROW
DECODER
COLUMN
DECODER
I/O DATA
CIRCUIT
I/O0-I/O23
CONTROL
CIRCUIT
GND
V
CC
MULTIPLEX
ADDRESS
CONTROL
X/Y
A15
V/S
IS61LV6424
S2-96
Integrated Circuit Solution Inc.
AHSR012-0D
PIN CONFIGURATION
100-Pin LQFP
PIN DESCRIPTIONS
A0-A14
Address Inputs
A15, X/Y
Multiplexed Address
I/O0-I/O23Data Inputs/Outputs
CE1, CE2 Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
V/S
Address Multiplexer
NC
No Connection
Vcc
Power
V
CCQ
Isolated Output Buffer Supply
GND
Ground
GNDQ
solated Output Buffer Ground
NC
NC
NC
NC
NC
I/O11
I/O10
I/O9
I/O8
GNDQ
V
CCQ
I/O7
I/O6
GND
NC
V
CC
NC
I/O5
I/O4
V
CCQ
GNDQ
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
NC
A14
A15
CE1
CE2
NC
NC
NC
X/Y
V/S
V
CC
GND
NC
WE
NC
OE
NC
NC
NC
A0
A1
NC
NC
NC
NC
NC
I/O12
I/O13
I/O14
I/O15
GNDQ
V
CCQ
I/O16
I/O17
NC
V
CC
NC
GND
I/O18
I/O19
V
CCQ
GNDQ
I/O20
I/O21
I/O22
I/O23
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
NC
A13
A12
A11
A10
A9
A8
NC
NC
GND
V
CC
NC
NC
A7
A6
A5
A4
A3
A2
NC
46 47 48 49 50
IS61LV6424
Integrated Circuit Solution Inc.
S2-97
AHSR012-0D
1
2
3
4
5
6
7
8
9
10
11
12
OPERATING RANGE
Range
Ambient Temperature
V
CC
(9, 10 ns)
V
CC
(12, 15 ns)
Commercial
0C to +70C
3.3V + 10%, 5%
3.3V 10%
Industrial
40C to +85C
3.3V + 10%, 5%
3.3V 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3V
V
IL
Input LOW Voltage
(1)
0.30.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
1
1
A
Note:
1. V
IL
(min.) = 0.3V DC; V
IL
(min.) = 2.0V AC (pulse width
2.0 ns).
V
IH
(max.) = V
CC
+ 0.3V DC; V
IH
(max.) = V
CC
+ 2.0V AC (pulse width
2.0 ns).
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Voltage Relative to GND
0.5 to 5.0
V
V
TERM
Terminal Voltage with Respect to GND
0.5 to Vcc + 0.5
V
T
STG
Storage Temperature
65 to + 150
C
T
BIAS
Temperature Under Bias:
Com.
10 to + 85
C
Ind.
45 to + 90
C
P
T
Power Dissipation
2.0
W
I
OUT
DC Output Current
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
Mode
CE1
CE1
CE1
CE1
CE1
CE2
OE
OE
OE
OE
OE
WE
WE
WE
WE
WE
V/
S
S
S
S
S
I/O0-I/O23
Vcc Current
Not Selected
H
X
X
X
X
High-Z
ISB1, ISB2
X
H
X
X
X
High-Z
Read Using X/Y
L
H
L
H
H
D
OUT
I
CC
Read Using A15
L
H
L
H
L
D
OUT
I
CC
Write Using X/Y
L
H
X
L
H
D
IN
I
CC
Write Using A15
L
H
X
L
L
D
IN
I
CC
Output Disable
L
H
H
H
X
High-Z
I
CC
IS61LV6424
S2-98
Integrated Circuit Solution Inc.
AHSR012-0D
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-9 ns
-10ns
-12 ns
-15 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating
V
CC
= Max.,
Com.
--
165
--
150
--
125
--
100
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
170
--
155
--
130
--
105
I
SB
1
TTL Standby Current
V
CC
= Max.,
Com.
--
40
--
40
--
35
--
30
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
, f = max.
Ind.
--
45
--
45
--
40
--
25
CE1 > V
IH
, CE2 < V
IL
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
10
--
10
--
10
--
10
mA
Current (CMOS Inputs)
CE1 > V
CC
0.2V,
Ind.
--
15
--
15
--
15
--
15
CE2 < 0.2V, V
IN
> V
CC
0.2V,
or V
IN
< 0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
2 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
OUTPUT
Z
O
= 50
1.5V
50
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
IS61LV6424
Integrated Circuit Solution Inc.
S2-99
AHSR012-0D
1
2
3
4
5
6
7
8
9
10
11
12
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-9
-10
-12
-15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
9
--
10
--
12
--
15
--
ns
t
AA
Address Access Time
--
9
--
10
--
12
--
15
ns
t
AV
V/S Access Time
--
9
--
10
--
12
--
15
ns
t
OH
Output Hold Time
3--
3--
3 --
3--
ns
From MUX Change
t
OHA
Output Hold Time
3--
3--
3 --
3--
ns
From Address Change
t
ACE
CE1Access Time
--
9
--
10
--
12
--
15
ns
t
ACE
2
CE2 Access Time
t
DOE
OE Access Time
--
5
--
5
--
6
--
7
ns
t
HZOE
(2)
OE to High-Z Output
0
30
30
30
3ns
t
LZOE
(2)
OE to Low-Z Output
0
--
0
--
0
--
0
--
ns
t
HZCE
(2)
CE1 to High-Z Output
0
5
0
5
0
6
0
7
ns
t
HZCE
2
(2)
CE2 to High-Z Output
t
LZCE
(2)
CE to Low-Z Output
3--
3--
3 --
3--
ns
t
LZCE
2
(2)
CE2 to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
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