Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- nCLK_EN Timing Diagram
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVHSTL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V/1.8V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagrams
- Output Rise/Fall Time Diagram
- odc, tPW & tPeriod Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Differential Clock Input Interface
- CLK/nCLK Input Driven by ICS HiPerClockS LVHSTL Driver Diagram
- CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagrams
- CLK/nCLK Input Driven by 3.3V LVPECL Driver with AC Couple Diagram
- Schematic Example
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVHSTL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
1
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS85214 is a low skew, high performance
1-to-5 Differential-to-HSTL Fanout Buffer and a
member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
CLK0, nCLK0 pair can accept most standard dif-
ferential input levels. The single ended CLK1 input accepts
LVCMOS or LVTTL input levels. Guaranteed output and part-
to-part skew characteristics make the ICS85214 ideal for
those clock distribution applications demanding well de-
fined performance and repeatability.
F
EATURES
5 differential HSTL compatible outputs
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL
clock inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Output frequency up to 700MHz
Translates any single ended input signal to HSTL levels
with resistor bias on nCLK0 input
Output skew: 30ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.8ns (maximum)
3.3V core, 1.8V output operating supply
0C to 85C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
nCLK_EN
V
DD
nc
CLK1
CLK0
nCLK0
nc
CLK_SEL
GND
ICS85214
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
CLK0
nCLK0
CLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
nCLK_EN
CLK_SEL
D
Q
LE
0
1
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
2
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
3
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
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F
UNCTION
T
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T
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LOCK
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F
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T
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Q0:Q4
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
4
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
85C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
85C
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3
=
5
A
0
K
L
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D
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=
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=
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:
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T
O
N
H
I
.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
85C
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L
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_
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L
C
n
V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
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,
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S
_
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L
C
,
1
K
L
C
N
E
_
K
L
C
n
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
Supply Voltage, V
DD
X
4.6V
Inputs, V
DD
-0.5V to V
DD
+ 0.5 V
Outputs, V
DDO
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
5
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
85C
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4D. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
85C
l
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b
m
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S
r
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.
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V
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L
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;
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g
a
t
l
o
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w
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L
t
u
p
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T
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N
0
4
.
0
V
V
X
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a
t
l
o
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r
e
v
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s
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r
C
t
u
p
t
u
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(
x
%
8
3
V
H
O
- V
L
O
+
)
V
L
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(
x
%
0
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H
O
V
-
L
O
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+
)
L
O
V
V
G
N
I
W
S
k
a
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-
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t
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
6
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
odc, t
PW
& t
P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ART
-
TO
-P
ART
S
KEW
V
CMR
Cross Points
V
PP
GND
CLK0
nCLK0
V
DD
P
ROPAGATION
D
ELAY
Q0:Q4
CLK0
nCLK0
nQx
SCOPE
HSTL
Qx
nQx
1.8V0.2V
V
DD
GND = 0V
3.3V5%
V
DDO
tsk(o)
Qx
nQy
Qy
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ4
Q0:Q4
t
PD
nQ0:nQ4
t
PD
Q0:Q4
CLK1
nQ0:nQ4
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
7
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
8
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements.
Figures 3A to 3D show inter-
face examples for the ICS85214 clock input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver com-
ponent to confirm the driver termination requirements. For ex-
ample in
Figure 3A, the input termination applies for ICS
HiPerClockS HSTL drivers. If you are using an HSTL driver from
another vendor, use their termination recommendations.
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
9
Integrated
Circuit
Systems, Inc.
ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
Zo = 50 Ohm
R9
50
R11
1K
U1
ICS85214
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
GND
CLK_SEL
nc
nCLK
CLK
SCLK
VDDO
nCLK_EN
VDD
nc
3.3V
Zo = 50 Ohm
R1
50
C2
0.1u
Zo = 50
R4
50
R7
50
LVHSTL Driver
R12
1K
R10
50
R3
50
Zo = 50
C1
0.1u
1.8V
Zo = 50
+
-
+
-
Zo = 50
Zo = 50
+
-
R8
50
Zo = 50
1.8V
R2
50
F
IGURE
4. ICS85214 HSTL B
UFFER
S
CHEMATIC
E
XAMPLE
S
CHEMATIC
E
XAMPLE
Figure 4 shows a schematic example of the ICS85214. In this
example, the input is driven by an ICS HiPerClockS HSTL
driver. The decoupling capacitors should be physically located
near the power pin. For ICS85214, the unused outputs can be
left floating.
85214AG
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REV. A JULY 17, 2003
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ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85214.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85214 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 80mA = 227.2mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power
_MAX
(3.465V, with all outputs switching) = 227.2mW + 164mW = 391.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.391W * 66.6C/W = 111C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
T
ABLE
6. T
HERMAL
R
ESISTANCE
q
JA
F
OR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85214AG
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REV. A JULY 17, 2003
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OW
S
KEW
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TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DDO_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DDO_MAX
- V
OL_MAX
)
Pd_H = (1.0V/50
) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
5. HSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
85214AG
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REV. A JULY 17, 2003
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ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85214 is: 674
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85214AG
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REV. A JULY 17, 2003
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ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
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85214AG
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ICS85214
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OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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85214AG
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REV. A JULY 17, 2003
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ICS85214
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
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85214AG
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REV. A JULY 17, 2003
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ICS85214
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OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
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