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Электронный компонент: ICS950227

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Integrated
Circuit
Systems, Inc.
ICS950227
0641D--07/03/03
Block Diagram
Pin Configuration
56-Pin 300-mil SSOP
Frequency Table
Recommended Application:
CK-408 clock Intel 845 with P4 processor.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
* These inputs have 150K internal pull-up resistor to VDD.
Programmable Timing Control HubTM for P4TM
2
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1
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X1
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55 FS1
X2
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54 FS0
GND
4
53 CPU_STOP#*
PCICLK_F0
5
52 CPUCLKT0
PCICLK_F1
6
51 CPUCLKC0
PCICLK_F2
7
50 VDDCPU
VDDPCI
8
49 CPUCLKT1
GND
9
48 CPUCLKC1
PCICLK0 10
47 GND
PCICLK1 11
46 VDDCPU
PCICLK2 12
45 CPUCLKT2
PCICLK3 13
44 CPUCLKC2
VDDPCI 14
43 MULTSEL0*
GND 15
42 IREF
PCICLK4 16
41 GND
PCICLK5 17
40 FS2
PCICLK6 18
39 48MHz_USB
VDD3V66 19
38 48MHz_DOT
GND 20
37 VDD48
3V66_2 21
36 GND
3V66_3 22
35 3V66_1/VCH_CLK
3V66_4 23
34 PCI_STOP#*
3V66_5 24
33 3V66_0
*PD# 25
32 VDD3V66
VDDA 26
31 GND
GND 27
30 SCLK
Vtt_PWRGD# 28
29 SDATA
I
C
S
950227
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
3V66 (5:2,0)
48MHz_DOT
3V66_1/VCH_CLK
X1
WDEN
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
Vtt_PWRGD#
FS (2:0)
I REF
Control
Logic
Config.
Reg.
REF
3
3
7
5
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK_F (2:0)
Stop
Stop
2
Integrated
Circuit
Systems, Inc.
ICS950227
0641D--07/03/03
Pin Description
Power Groups
(Analog)
(Digital)
VDDA = Analog Core PLL1
VDDPCI
VDDREF = REF, Xtal
VDD3V66
VDD48 = 48MHz, PLL
VDDCPU
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Integrated
Circuit
Systems, Inc.
ICS950227
0641D--07/03/03
Host Swing Select Functions
Maximum Allowed Current
Truth Table
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Integrated
Circuit
Systems, Inc.
ICS950227
0641D--07/03/03
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each
byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
5
Integrated
Circuit
Systems, Inc.
ICS950227
0641D--07/03/03
I
2
C Table: Frequency Select Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
SPREAD ENABLE
Frequency H/W IIC
Select
RW
OFF
ON
0
Bit 6
CENTER/DOWNSP
READ SELECT
CENTER/DOWNSPRE
AD SELECT
RW
DOWN
SPREAD
CENTER
SPREAD
0
Bit 5
3V66/VCH SELECT 48MHz/66.66MHz SEL
RW
66.66MHz
48.00MHz
0
Bit 4
CPU_STOP#
CPU STOP Read Back
R
X
Bit 3
PCI_STOP#
HW/SW SELECT
Freq Select Bit 3
RW/R
PCI STOP
PCI
RUNNING
1
Bit 2
FS2
Freq Select 2 Read
Back
R
X
Bit 1
FS1
Freq Select 1 Read
Back
R
X
Bit 0
FS0
Freq Select 0 Read
Back
R
X
I
2
C Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
MULTSEL0
MULTSEL0
READBACK
R
X
Bit 6
WD ALARM
Watchdog Alarm Read
Back
R
NO ALARM
ALARM SET
0
Bit 5
CPU2/CPUC2
RW
STOPPABLE FREE-RUN
0
Bit 4
CPU1/CPUC1
RW
STOPPABLE FREE-RUN
0
Bit 3
CPU0/CPUC0
RW
STOPPABLE FREE-RUN
0
Bit 2
CPU2/CPUC2
Output Control
RW
Disable
Enable
1
Bit 1
CPU1/CPUC1
Output Control
RW
Disable
Enable
1
Bit 0
CPU0/CPUC0
Output Control
RW
Disable
Enable
1
I
2
C Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Reserved
Reserved
RW
-
-
0
Bit 6
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK0
Output Control
RW
Disable
Enable
1
I
2
C Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
48MHz_DOT
Output Control
RW
Disable
Enable
1
Bit 6
48MHz_USB
Output Control
RW
Disable
Enable
1
Bit 5
PCIF2
RW
FREE-RUN STOPPABLE
0
Bit 4
PCIF1
RW
FREE-RUN STOPPABLE
0
Bit 3
PCIF0
RW
FREE-RUN STOPPABLE
0
Bit 2
PCICLK_F2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK_F1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK_F0
Output Control
RW
Disable
Enable
1
5
7
6
5
READBACK
Byte 1
43
READBACK
53
34
40
55
54
READBACK
Byte 0
-
-
35
-
45, 44
49, 48
52, 51
17
16
13
Byte 2
-
18
45, 44
49, 48
52, 51
12
11
10
6
Byte 3
38
39
7
CPU FREE-RUN NING
CONTROL
CPU FREE-RUN NING
CONTROL