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IDT74FCT162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
MAY 2001
IDT74FCT162601AT/CT
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
18-BIT UNIVERSAL
BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
DESCRIPTION:
The FCT162601T 18-bit registered transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power 18-bit registered
bus transceivers combine D-type latches and D-type flip-flops to allow data flow
in either direction in a transparent, latched or clocked mode. Each direction has
an independent latch enable, an independent clock with a clock enable, and an
independent output enable. The package is organized with a flow-through signal
pin organization to ease board layout. All inputs are designed with hysteresis
for improved noise margin.
This transceiver is ideally suited for high speed memory interfaces which
utilize high speed synchronous writes, by clocking the data into a high speed
register. Reads can then be performed in a transparent or latched mode utilizing
the same transceiver.
The FCT162601T have balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
timesreducing the need for external series terminating resistors. The
FCT162601T are plug-in replacements for the FCT16601T and ABT16601
for on-board bus interface applications.
LEAB
C LKA B
LEBA
C LKB A
CLKENAB
OEA B
A
1
TO 17 OTHER CH ANN ELS
OEB A
CE
1D
C1
C LK
CE
1D
C1
CLK
CLKENBA
1
56
55
2
28
30
29
27
3
54
B
1
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
1A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V 10%
Balanced Output Drivers: 24mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25C
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2001 Integrated Device Technology, Inc.
DSC-5447/-
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
CLKENAB
B
2
B
3
GND
B
4
B
5
V
CC
B
6
B
7
B
1
B
8
B
9
B
10
B
11
GND
B
12
B
13
V
CC
B
14
GND
CLKAB
B
16
B
15
B
17
GND
B
18
CLKBA
CLKENBA
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
GND
A
6
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
18
A
14
A
13
A
16
GND
A
17
LEBA
A
15
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB
A to B Clock Enable Input
CLKENBA
B to A Clock Enable Input
PIN DESCRIPTION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to 7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
(1)
(1)
(1)
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
3.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
3.5
8
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(1, 4)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and
CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
= HIGH-to-LOW Transition
Inputs
Outputs
CLKENAB
OEAB
LEAB
CLKAB
A
B
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B
0
(2)
L
L
L
L
L
L
L
L
H
H
L
L
L
L
X
B
0
(2)
L
L
L
H
X
B
0
(3)
3
IDT74FCT162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current (Input pins)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
--
--
1
I
IL
Input LOW Current (Input pins)
V
I
= GND
--
--
1
Input LOW Current (I/O pins)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
250
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= Max.
--
5
500
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 10%
OUTPUT DRIVE CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max. Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
60
115
200
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 24mA
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 24mA
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
1.5
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
75
120
A/
Current
(4)
Outputs Open
V
IN
= GND
MHz
OEAB = V
CC
,
OEBA = GND
One Input Togging
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
0.8
1.7
mA
Outputs Open
V
IN
= GND
f
CP
= 10MHz (CLKBA)
50% Duty Cycle
OEAB = V
CC
OEBA = GND
LEBA = GND
V
IN
= 3.4V
--
1.3
3.2
CLKENBA = GND
V
IN
= GND
One Bit Toggling
f
I
= 5MHz
50% Duty Cycle
V
CC
= Max.
V
IN
= V
CC
--
3.8
6.5
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz (CLKBA)
50% Duty Cycle
OEAB = V
CC
OEBA = GND
LEAB = GND
V
IN
= 3.4V
--
8.5
20.8
(5)
CLKENBA = GND
V
IN
= GND
Eighteen Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
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IDT74FCT162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FCT162601AT
FCT162601CT
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Unit
f
MAX
CLKAB or CLKBA frequency
(4)
C
L
= 50pF
--
150
1.5
150
MHz
t
PLH
Propagation Delay
R
L
= 500
1.5
4.9
1.5
4
ns
t
PHL
Ax to Bx or Bx to Ax
t
PLH
Propagation Delay
1.5
5.2
1.5
4.2
ns
t
PHL
LEBA to Ax, LEAB to Bx
t
PLH
Propagation Delay
1.5
4.7
1.5
4.2
ns
t
PHL
CLKBA to Ax, CLKAB to Bx
t
PZH
Output Enable Time
1.5
5.8
1.5
4.8
ns
t
PZL
OEBA to Ax, OEAB to Bx
t
PHZ
Output Disable Time
1.5
6.2
1.5
5.2
ns
t
PLZ
OEBA to Ax, OEAB to Bx
t
SU
Set-up Time, HIGH or LOW
4
--
2.4
--
ns
Ax to CLKAB, Bx to CLKBA
t
H
Hold Time, HIGH or LOW
0
--
0
--
ns
Ax to CLKAB, Bx after CLKBA
t
SU
Set-up Time
Clock
1
--
1
--
ns
HIGH or LOW
LOW
Ax to LEAB
Clock
2.5
--
1.5
--
ns
Bx to LEBA
HIGH
t
H
Hold Time, HIGH or LOW
2
--
0.5
--
ns
Ax after LEAB, Bx after LEBA
t
SU
Set-up Time, CLKEN to CLK
2.5
--
2
--
ns
t
H
Hold Time, CLKEN to CLK
0
--
0
--
ns
t
W
LEAB or LEBA Pulse Width HIGH
(4)
2.5
--
2.5
--
ns
t
W
CLKAB or CLKBA Pulse Width HIGH or
3
--
3
--
ns
LOW
(4)
t
SK(o)
Output Skew
(3)
--
0.5
--
0.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
D ATA
INPUT
TIM IN G
INPUT
ASYNC HR ONOUS C ONTROL
PRES ET
CLEA R
ETC .
SYNCHR ON OUS CONTROL
t
SU
t
H
t
R EM
t
SU
t
H
PRES ET
CLEA R
CLOCK ENABLE
ETC .
HIGH-LOW -H IGH
PU LSE
LOW -HIGH-LOW
PU LSE
t
W
1.5V
1.5V
SAM E PHASE
INPUT TRAN SITION
3V
1.5V
0V
1.5V
V
O H
t
PLH
OU TPU T
OPPOSITE P HASE
INPUT TRAN SITION
3V
1.5V
0V
t
PL H
t
PH L
t
PH L
V
O L
CONTROL
IN PU T
3V
1.5V
0V
3.5V
0V
OUTPU T
NORM ALLY
LOW
OUTPU T
NORM ALLY
H IGH
SW ITCH
C LOSE D
SW ITC H
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
D ISABLE
V
OH
TEST CIRCUITS AND WAVEFORMS
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Test Circuits For all Outputs
Set-up, Hold, and Release Times
Propagation Delay
Pulse Width
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
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IDT74FCT162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X
Temperature
Range
IDT
FCT
XXX
Device
Type
XX
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
601AT
601CT
18-Bit Universal Bus Transceiver
40C to +85C
74
XXX
Family
162
Double-Density, 5 Volt, Balanced Drive
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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