PROFET BTS712N1
Semiconductor Group
1 of 15
2004-Mar-11
Smart Four Channel Highside Power Switch
Features
Overload protection
Current limitation
Short-circuit protection
Thermal shutdown
Overvoltage protection
(including load dump)
Fast demagnetization of inductive loads
Reverse battery protection
1)
Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
Open drain diagnostic output
Open load detection in OFF-state
CMOS compatible input
Loss of ground and loss of V
bb
protection
Electrostatic discharge (ESD) protection
Application
C compatible power switch with diagnostic feedback
for 12 V and 24 V DC grounded loads
All types of resistive, inductive and capacitive loads
Replaces electromechanical relays and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS
technology. Providing embedded protective functions.
Pin Definitions and Functions
Pin
Symbol Function
1,10,
11,12,
15,16,
19,20
V
bb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 4 and also for low
thermal resistance
3 IN1
Input 1 .. 4, activates channel 1 .. 4 in case of
5
IN2
logic high signal
7 IN3
9 IN4
18 OUT1
Output 1 .. 4, protected high-side power output
17
OUT2
of channel 1 .. 4. Design the wiring for the
14
OUT3
max. short circuit current
13 OUT4
4 ST1/2
Diagnostic feedback 1/2 of channel 1 and
channel 2, open drain, low on failure
8 ST3/4
Diagnostic feedback 3/4 of channel 3 and
channel 4, open drain, low on failure
2 GND1/2
Ground 1/2 of chip 1 (channel 1 and channel 2)
6 GND3/4
Ground 3/4 of chip 2 (channel 3 and channel 4)
1
) With external current limit (e.g. resistor R
GND
=150
) in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Product Summary
Overvoltage Protection
V
bb(AZ)
43
V
Operating voltage
V
bb(on)
5.0 ... 34
V
active channels: one
two parallel four parallel
On-state resistance R
ON
200 100 50
m
Nominal load current
I
L(NOM)
1.9 2.8 4.4
A
Current limitation
I
L(SCr)
4 4 4
A
Pin configuration
(top view)
V
bb
1
20 V
bb
GND1/2 2
19 V
bb
IN1 3
18 OUT1
ST1/2 4
17 OUT2
IN2 5
16 V
bb
GND3/4 6
15 V
bb
IN3 7
14 OUT3
ST3/4 8
13 OUT4
IN4 9
12 V
bb
V
bb
10
11 V
bb
P-DSO-20
BTS712N1
Semiconductor Group
2
2004-Mar-11
Block diagram
Four Channels; Open Load detection in off state;
+ V bb
IN1
ST1/2
ESD
OUT1
Logic
Voltage
sensor
Voltage
source
Open load
detection 1
Short to Vbb
Level shifter
Temperature
sensor 1
Rectifier 1
Limit for
unclamped
ind. loads 1
Gate 1
protection
Current
limit 1
3
4
V
Logic
Overvoltage
protection
OUT2
Open load
detection 2
Short to Vbb
Level shifter
Temperature
sensor 2
Rectifier 2
Limit for
unclamped
ind. loads 2
Gate 2
protection
Current
limit 2
IN2
5
Charge
pump 1
Charge
pump 2
Channel 2
Channel 1
Signal GND
GND1/2
2
Chip 1
Chip 1
+ V bb
IN3
ST3/4
PROFET
OUT3
7
8
OUT4
IN4
9
Channel 4
Channel 3
Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20
Leadframe
18
17
Load GND
Load
Leadframe
14
13
Load GND
Load
Signal GND
GND3/4
6
Chip 2
Chip 2
Logic and protection circuit of chip 2
(equivalent to chip 1)
BTS712N1
Semiconductor Group
3
2004-Mar-11
Maximum Ratings at T
j
= 25C unless otherwise specified
Parameter Symbol
Values
Unit
Supply voltage (overvoltage protection see page 4)
V
bb
43
V
Supply voltage for full short circuit protection
T
j,start
=
-40 ...+150C
V
bb
34
V
Load current (Short-circuit current, see page 5)
I
L
self-limited
A
Load dump protection
2
)
V
LoadDump
= U
A
+ V
s
, U
A
= 13.5 V
R
I
3
)
= 2
, t
d
= 200
ms; IN
= low or high,
each channel loaded with R
L
=
7.1
,
V
Load
dump
4
)
60
V
Operating temperature range
Storage temperature range
T
j
T
stg
-40 ...+150
-55 ...+150
C
Power dissipation (DC)
5
T
a
= 25C:
(all channels active)
T
a
= 85C:
P
tot
3.6
1.9
W
Inductive load switch-off energy dissipation, single pulse
V
bb
=
12V, T
j,start
=
150C
5)
,
I
L
=
1.9
A, Z
L
=
66
mH, 0
one
channel:
I
L
=
2.8
A, Z
L
=
66
mH, 0
two parallel channels:
I
L
=
4.4
A, Z
L
=
66
mH, 0
four parallel channels:
see diagrams on page 10
E
AS
150
320
800
mJ
Electrostatic discharge capability (ESD)
(Human Body Model)
V
ESD
1.0
kV
Input voltage (DC)
V
IN
-10 ... +16
V
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagram page 9
I
IN
I
ST
2.0
5.0
mA
Thermal resistance
junction - soldering point
5),6)
each
channel:
R
thjs
16
K/W
junction - ambient
5)
one channel active:
all channels active:
R
thja
44
35
2
) Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins, e.g. with a
150
resistor in the GND connection and a 15 k
resistor in series with the status pin. A resistor for input
protection is integrated.
3)
R
I
= internal resistance of the load dump test pulse generator
4)
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
5
) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70
m thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 15
6
) Soldering point: upper side of solder edge of device pin 15. See page 15
BTS712N1
Semiconductor Group
4
2004-Mar-11
Electrical Characteristics
Parameter and Conditions,
each of the four channels
Symbol
Values
Unit
at T
j
= 25 C, V
bb
= 12 V unless otherwise specified
min typ
max
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT)
I
L
= 1.8 A
each channel, T
j
= 25C:
T
j
= 150C:
two parallel channels, T
j
= 25C:
four parallel channels, T
j
= 25C:
R
ON
--
165
320
83
42
200
400
100
50
m
Nominal load current
one channel active:
two parallel channels active:
four parallel channels active:
Device on PCB
5)
, T
a
=
85C, T
j
150C
I
L(NOM)
1.7
2.6
4.1
1.9
2.8
4.4
--
A
Output current while GND disconnected or pulled
up; V
bb
=
30 V, V
IN
= 0, see diagram page 10
I
L(GNDhigh)
-- --
10
mA
Turn-on time
to 90% V
OUT
:
Turn-off time
to 10% V
OUT
:
R
L
=
12
,
T
j
=-40...+150C
t
on
t
off
80
80
200
200
400
400
s
Slew rate on
10 to 30% V
OUT
,
R
L
=
12
,
T
j
=-40...+150C:
dV/dt
on
0.1 -- 1
V/
s
Slew rate off
70 to 40% V
OUT
, R
L
=
12
,
T
j
=-40...+150C:
-dV/dt
off
0.1 -- 1
V/
s
Operating Parameters
Operating voltage
7
)
T
j
=-40...+150C: V
bb(on)
5.0
--
34
V
Undervoltage shutdown
T
j
=-40...+150C: V
bb(under)
3.5 --
5.0
V
Undervoltage restart
T
j
=-40...+25C:
T
j
=+150C:
V
bb(u rst)
--
--
5.0
7.0
V
Undervoltage restart of charge pump
see diagram page 14
T
j
=-40...+150C:
V
bb(ucp)
-- 5.6 7.0
V
Undervoltage hysteresis
V
bb(under)
= V
bb(u rst)
- V
bb(under)
V
bb(under)
-- 0.2 --
V
Overvoltage shutdown
T
j
=-40...+150C: V
bb(over)
34
--
43
V
Overvoltage restart
T
j
=-40...+150C: V
bb(o rst)
33 -- --
V
Overvoltage hysteresis
T
j
=-40...+150C:
V
bb(over)
-- 0.5 --
V
Overvoltage protection
8
)
T
j
=-40...+150C:
I
bb
=
40 mA
V
bb(AZ)
42
47
--
V
7)
At supply voltage increase up to V
bb
=
5.6
V typ without charge pump, V
OUT
V
bb
- 2 V
8)
see also V
ON(CL)
in circuit diagram on page 9.
BTS712N1
Parameter and Conditions,
each of the four channels
Symbol
Values
Unit
at T
j
= 25 C, V
bb
= 12 V unless otherwise specified
min typ
max
Semiconductor Group
5
2004-Mar-11
Standby current, all channels off
T
j
=25C
:
V
IN
=
0
T
j
=150C:
I
bb(off)
--
--
180
160
300
300
A
Operating current
9)
, V
IN
=
5V, T
j
=-40...+150C
I
GND
= I
GND1/2
+ I
GND3/4
,
one channel on:
four channels on:
I
GND
--
--
0.35
1.2
0.8
2.8
mA
Protection Functions
10)
Initial peak short circuit current limit,
(see timing
diagrams, page 12)
each channel, T
j
=-40C:
T
j
=25C:
T
j
=+150C:
I
L(SCp)
5.5
4.5
2.5
9.5
7.5
4.5
13
11
7
A
two parallel channels
twice the current of one channel
four parallel channels
four times the current of one channel
Repetitive short circuit current limit,
T
j
= T
jt
each channel
two parallel channels
four parallel channels
(see timing diagrams, page 12)
I
L(SCr)
--
--
--
4
4
4
--
--
--
A
Initial short circuit shutdown time
T
j,start
=-40C:
T
j,start
= 25C:
(see page 11 and timing diagrams on page 12)
t
off(SC)
--
--
5.5
4
--
--
ms
Output clamp (inductive load switch off)
11)
at V
ON(CL)
= V
bb
- V
OUT
V
ON(CL)
-- 47 --
V
Thermal overload trip temperature
T
jt
150 -- --
C
Thermal hysteresis
T
jt
-- 10 --
K
Reverse Battery
Reverse battery voltage
12
)
-V
bb
--
--
32
V
Drain-source diode voltage
(V
out
> V
bb
)
I
L
=
-
1.9
A, T
j
=
+150C
-V
ON
--
610
--
mV
Diagnostic Characteristics
Open load detection current
I
L(off)
-- 30
--
A
Open load detection voltage
T
j
=-40..+150C:
V
OUT(OL)
2 3
4
V
9
)
Add I
ST
, if I
ST
> 0
10
) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
11
)
If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
V
ON(CL)
12
) Requires a 150
resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 3 and circuit page 9).
BTS712N1
Parameter and Conditions,
each of the four channels
Symbol
Values
Unit
at T
j
= 25 C, V
bb
= 12 V unless otherwise specified
min typ
max
Semiconductor Group
6
2004-Mar-11
Input and Status Feedback
13
)
Input resistance
(see circuit page 9)
T
j
=-40..+150C:
R
I
2.5
3.5 6
k
Input turn-on threshold voltage
T
j
=-40..+150C:
V
IN(T+)
1.7 --
3.5
V
Input turn-off threshold voltage
T
j
=-40..+150C:
V
IN(T-)
1.5 -- --
V
Input threshold hysteresis
V
IN(T)
-- 0.5 --
V
Off state input current
V
IN
= 0.4 V:
T
j
=-40..+150C:
I
IN(off)
1
-- 50
A
On state input current
V
IN
= 5 V:
T
j
=-40..+150C:
I
IN(on)
20 50 90
A
Delay time for status with open load
(see timing diagrams, page 13)
t
d(ST OL3)
-- 220
--
s
Status output (open drain)
Zener limit voltage
T
j
=-40...+150C, I
ST
= +1.6 mA:
ST low voltage
T
j
=-40...+25C, I
ST
= +1.6 mA:
T
j
= +150C, I
ST
= +1.6 mA:
V
ST(high)
V
ST(low)
5.4
--
--
6.1
--
--
--
0.4
0.6
V
13)
If ground resistors R
GND
are used, add the voltage drop across these resistors.
BTS712N1
Semiconductor Group
7
2004-Mar-11
Truth Table
Channel 1 and 2
Chip 1
IN1
IN2
OUT1
OUT2
ST1/2
ST1/2
Channel 3 and 4
(equivalent to channel 1 and 2)
Chip 2
IN3
IN4
OUT3
OUT4
ST3/4
ST3/4
BTS 711L1
BTS 712N1
Normal operation
L
L
H
H
L
H
L
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Open load
Channel 1 (3)
L
L
H
L
H
X
Z
Z
H
L
H
X
H(L
14
))
H
L
L
H
H
Channel 2 (4)
L
H
X
L
L
H
L
H
X
Z
Z
H
H(L
14
))
H
L
L
H
H
Short circuit to Vbb
Channel 1 (3)
L
L
H
L
H
X
H
H
H
L
H
X
L
15)
H
H(L
16
))
L
15)
H
H
Channel 2 (4)
L
H
X
L
L
H
L
H
X
H
H
H
L
15)
H
H(L
16
))
L
15)
H
H
Overtemperature
both channel
L
X
H
L
H
X
L
L
L
L
L
L
H
L
L
H
L
L
Channel 1 (3)
L
H
X
X
L
L
X
X
H
L
H
L
Channel 2 (4)
X
X
L
H
X
X
L
L
H
L
H
L
Undervoltage/ Overvoltage
X
X
L
L
H
H
L = "Low" Level
X = don't care
Z = high impedance, potential depends on external circuit
H = "High" Level
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
14
) With additional external pull up resistor
15)
An external short of output to V
bb
in the off state causes an internal current from output to ground. If R
GND
is
used, an offset voltage at the GND and ST pins will occur and the V
ST low
signal may be errorious.
16
) Low resistance to V
bb
may be detected by no-load-detection
BTS712N1
Semiconductor Group
8
2004-Mar-11
Terms
PROFET
IN2
ST1/2
OUT2
GND1/2
Vbb
VOUT2
IGND1/2
VON2
18
2
Leadframe
3
4
IN1
V
OUT1
VON1
I L1
OUT1
5
17
V
IN1 VIN2 VST1/2
Ibb
I IN1
I IN2
I ST1/2
I L2
R
GND1/2
V
bb
Chip 1
PROFET
IN4
ST3/4
OUT4
GND3/4
Vbb
VOUT4
IGND3/4
VON4
14
6
Leadframe
7
8
IN3
V
OUT3
VON3
I L3
OUT3
9
13
V
IN3 VIN4 VST3/4
I IN3
I IN4
I ST3/4
I L4
R GND3/4
Chip 2
Leadframe (V
bb
) is connected to pin 1,10,11,12,15,16,19,20
External R
GND
optional; two resistors R
GND1/2
,R
GND3/4
=
150
or a single resistor R
GND
=
75
for
reverse battery protection up to the max. operating voltage
BTS712N1
Semiconductor Group
9
2004-Mar-11
Input circuit (ESD protection),
IN1...4
IN
GND
I
R
ESD-ZD
I
I
I
ESD zener diodes are not to be used as voltage clamp at
DC conditions. Operation in this mode may result in a drift of
the zener voltage (increase of up to 1 V).
Status output,
ST1/2 or ST3/4
ST
GND
ESD-
ZD
+5V
R
ST(ON)
ESD-Zener diode: 6.1
V typ., max 5.0 mA; R
ST(ON)
< 380
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may resul
t
in
a drift of
the zener voltage (increase of up to 1 V).
Inductive and overvoltage output clamp,
OUT1...4
+Vbb
OUT
PROFET
VZ
V
ON
Power GND
V
ON
clamped to V
ON(CL)
= 47 V typ.
Overvoltage protection of logic part
GND1/2 or GND3/4
+ Vbb
IN
ST
ST
R
GND
GND
R
Signal GND
Logic
V
Z2
IN
RI
VZ1
V
Z1
=
6.1
V typ., V
Z2
=
47
V typ., R
I
=
3.5
k
typ.
,
R
GND
= 150
Reverse battery protection
GND
Logic
ST
R
IN
ST
5V
OUT
L
R
Power GND
GND
R
Signal GND
Power
Inverse
I
R
Vbb
-
Diode
R
GND
= 150
,
R
I
= 3.5 k
typ
,
Temperature protection is not active during inverse current
operation.
Open-load detection,
OUT1...4
OFF-state diagnostic condition:
V
OUT
> 3 V typ.; IN low
Open load
detection
Logic
unit
VOUT
Signal GND
I
L(OL)
OFF
BTS712N1
Semiconductor Group
10
2004-Mar-11
GND disconnect
(channel 1/2 or 3/4)
PROFET
V
IN2
ST
OUT2
GND
bb
V
bb
Ibb
IN1
OUT1
V
IN1
V
IN2
V
ST
V
GND
Any kind of load. In case of IN
=
high is V
OUT
V
IN
-
V
IN(T+)
.
Due to V
GND
>
0, no V
ST
= low signal available.
GND disconnect with GND pull up
(channel 1/2 or 3/4)
PROFET
V
IN2
ST
OUT2
GND
bb
V
bb
IN1
OUT1
V
IN1
V
IN2
V
ST
V
GND
Any kind of load. If V
GND
> V
IN
- V
IN(T+)
device stays off
Due to V
GND
>
0, no V
ST
= low signal available.
V
bb
disconnect with energized inductive
load
PROFET
V
IN2
ST
OUT2
GND
bb
V
bb
IN1
OUT1
high
For an inductive load current up to the limit defined by EAS
(max. ratings see page 3 and diagram on page 10) each
switch is protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb dis-
connection with energized inductive load the whole load
current flows through the GND connection.
Inductive load switch-off energy
dissipation
PROFET
V
IN
ST
OUT
GND
bb
=
E
E
E
EAS
bb
L
R
ELoad
RL
L
{
L
Z
Energy stored in load inductance:
E
L
=
1/2
L
I
2
L
While demagnetizing load inductance, the energy
dissipated in PROFET is
E
AS
= E
bb
+ E
L
- E
R
=
V
ON(CL)
i
L
(t) dt,
with an approximate solution for RL
>
0
:
E
AS
=
I
L
L
2
R
L
(
V
bb
+
|V
OUT(CL)
|)
ln
(1+
I
L
R
L
|V
OUT(CL)
|
)
Maximum allowable load inductance for
a single switch off
(one channel)
5)
L = f (IL );
Tj,start =
150C, Vbb =
12
V, RL =
0
L [mH]
1
10
100
1000
1
1.5
2
2.5
3
IL [A]
BTS712N1
Semiconductor Group
11
2004-Mar-11
Typ. on-state resistance
R
ON
= f (Vbb,Tj )
; I
L
=
1.8
A, IN
= high
R
ON
[mOhm]
0
50
100
150
200
250
300
350
400
450
500
0
10
20
30
40
Tj = 150C
85C
25C
-40C
V
bb
[V]
Typ. standby current
I
bb(off)
= f (T
j
)
; V
bb
= 9...34 V, IN1...4
= low
I
bb(off)
[
A]
0
50
100
150
200
250
-50
0
50
100
150
200
T
j
[C]
Ibb(off) includes four times the current IL(off) of the open
load detection current sources.
Typ. ground pin operating current
I
GND
= f (Vbb,Tj );
V
IN
= high (one channel on)
I
GND
[mA]
0
0.25
0.5
0.75
1
1.25
1.5
0
10
20
30
40
50
T
j
= -40C
25C
85C
150C
V
bb
[V]
Typ. initial short circuit shutdown time
t
off(SC)
= f (Tj,start )
; V
bb
=12 V
t
off(SC)
[msec]
0
1
2
3
4
5
6
-50
0
50
100
150
200
T
j,start
[C]
BTS712N1
Semiconductor Group
12
2004-Mar-11
Figure 1a: V
bb
turn on:
IN2
V
OUT1
t
V
bb
ST open drain
IN1
V
OUT2
Figure 2a: Switching a lamp:
IN
ST
OUT
L
t
V
I
The initial peak current should be limited by the lamp and not by
the initial short circuit current I
L(SCp)
= 7.5 A typ. of the device.
Figure 2b: Switching an inductive load,
IN
ST
L
t
V
I
OUT
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
other channel: normal operation
t
I
ST
IN1
L1
L(SCr)
I
IL(SCp)
toff(SC)
Heating up of the chip may require several milliseconds, depending
on external conditions (toff(SC) vs. Tj,start see page 11)
Timing diagrams
Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams
are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently
the diagrams are valid for each channel as well as for permuted channels
BTS712N1
Semiconductor Group
13
2004-Mar-11
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
t
ST1/2
IN1/2
L1 L2
L(SCr)
I
I L(SCp)
I + I
toff(SC)
Figure 4a: Overtemperature:
Reset if T
j
<T
jt
IN
ST
OUT
J
t
V
T
Figure 5a: Open load: detection in OFF-state, turn
on/off to open load
OUT1
t
V
ST
IN1
I
L1
t
d(ST OL3)
t
d(ST OL3)
IN2 channel 2: normal operation
channel 1: open load
t
d(ST,OL3)
depends on external circuitry because of high
impedance
*) I
L
=
30
A typ
Figure 6a: Undervoltage:
IN
V
OUT
t
V
bb
ST open drain
V
V
bb(under)
bb(u rst)
bb(u cp)
V
BTS712N1
Semiconductor Group
14
2004-Mar-11
Figure 6b: Undervoltage restart of charge pump
bb(under)
V
V
bb(u rst)
V
bb(over)
V
bb(o rst)
V
bb(u cp)
off-state
on-state
V
ON(CL)
V
bb
V
on
off-state
IN = high, normal load conditions.
Charge pump starts at V
bb(ucp)
= 5.6
V typ.
Figure 7a: Overvoltage:
IN
V
OUT
t
V
bb
ST
ON(CL)
V
V
bb(over)
V
bb(o rst)
BTS712N1
Semiconductor Group
15
2004-Mar-11
Package and Ordering Code
Standard P-DSO-20-9
Ordering
Code
BTS712N1
Q67060-S7001-A2
All dimensions in millimetres
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Definition of soldering point with temperature T
s
:
upper side of solder edge of device pin 15.
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70
m, 6cm
2
active heatsink area) as a reference for
max. power dissipation P
tot
, nominal load current
I
L(NOM)
and thermal resistance R
thja
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 Mnchen
Infineon Technologies AG 2001
All Rights Reserved.
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