Other brands and names are the property of their respective owners

Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

April 1994

INTEL CORPORATION 1995

Order Number 272323-002

8XC196MD

INDUSTRIAL MOTOR CONTROL

MICROCONTROLLER

87C196MD 16 Kbytes of On-Chip OTPROM

87C196MD ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM

80C196MD ROMless

High-Performance CHMOS 16-Bit CPU

16 Kbytes of On-Chip OTPROM
Factory-Programmed OTPROM

488 bytes of On-Chip Register RAM

Up to 64 I O Lines

Peripheral Transaction Server (PTS)
with 17 Prioritized Sources

Event Processor Array (EPA)

6 High Speed Capture Compare
Modules
6 High Speed Compare Modules

Extended Temperature Standard

Programmable Frequency Generator

Two 16-Bit Timers with Quadrature
Counting Input

3-Phase Complementary Waveform
Generator

14 Channel 8 10-Bit A D with Sample
Hold with Zero Offset Adjustment H W

18 Prioritized Interrupt Sources

Flexible 8- 16-Bit External Bus

1 75 ms 16 x 16 Multiply

3 ms 32 16 Divide

Idle and Power Down Modes

The 8XC196MD is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brush-
less motors The 8XC196MD is based on Intel's MCS

96 16-bit microcontroller architecture and is manufac-

tured with Intel's CHMOS process

The 8XC196MD has a three phase waveform generator specifically designed for use in ``Inverter'' motor
control applications This peripheral allows for pulse width modulation three phase sine wave generation with
minimal CPU intervention It generates 3 complementary non-overlapping PWM pulses with resolutions of
0 125 ms (edge trigger) or 0 250 ms (centered)

The 8XC196MD has 16 Kbytes on-chip OTPROM ROM and 488 bytes of on-chip RAM It is available in two
packages PLCC (84-L) and EIAJ QFP (80-L)

Operational characteristics are guaranteed over the temperature range of b40 C to a85 C

The 87C196MD contains 16 Kbytes on-chip OTPROM The 83C196MD contains 16 Kbytes on-chip ROM All
references to the 80C196MD also refers to the 83C196MD and 87C196MD unless noted

OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package

and cannot be erased It is user programmable

8XC196MD

PROCESS INFORMATION

This device is manufactured on PX29 5 a CHMOS
III-E process Additional process and reliability infor-
mation is available in Intel's

Components Quality

and Reliability Handbook

Order Number 210997

272323 2

EXAMPLE

N87C196MD is 84-Lead PLCC OTPROM

16 MHz
For complete package dimensional data refer to the
Intel Packaging Handbook (Order Number 240800)

NOTE
EPROMs are available as One Time Programmable
(OTPROM) only

Figure 2 The 8XC196MD Family Nomenclature

Table 1 Thermal Characteristics

Package

Type

PLCC

35 C W

13 C W

QFP

56 C W

12 C W

All thermal impedance data is approximate for static air
conditions at 1W of power dissipation Values will change
depending on operation conditions and application See
the Intel

Packaging Handbook (order number 240800) for a

description of Intel's thermal impedance test methodology

Table 2 8XC196MD Memory Map

Description

Address

External Memory or I O

0FFFFH

06000H

Internal ROM EPROM or External

5FFFH

Memory (Determined by EA)

2080H

Reserved Must contain FFH

207FH

(Note 5)

205EH

PTS Vectors

205DH

2040H

Upper Interrupt Vectors

203FH

2030H

ROM EPROM Security Key

202FH

2020H

Reserved Must contain FFH

201FH

(Note 5)

201CH

Reserved Must Contain 20H

201BH

(Note 5)

CCB1

201AH

Reserved Must Contain 20H

2019H

(Note 5)

CCB0

2018H

Reserved Must contain FFH

2017H

(Note 5)

2014H

Lower Interrupt Vectors

2013H
2000H

SFR's

1FFFH

1F00H

External Memory

1EFFH

0200H

488 Bytes Register RAM (Note 1)

01FFH

0018H

CPU SFR's (Notes 1 3)

0017H
0000H

NOTES
1 Code executed in locations 0000H to 01FFH will be
forced external
2 Reserved memory locations must contain 0FFH unless
noted
3 Reserved SFR bit locations must contain 0
4 Refer to 8XC196MC for SFR descriptions
5 WARNING Reserved memory locations must not be
written or read The contents and or function of these lo-
cations may change with future revisions of the device
Therefore a program that relies on one or more of these
locations may not function properly

8XC196MD

8XC196MC AND 8XC196MD
DIFFERENCES

INT

MASK1 INT

PEND1 Registers

There

are

some

differences

between

the

8XC196MC

and

8XC196MD

INT

MASK1

INT

PEND1 registers

The 8XC196MD interrupt

mask and pending registers are shown below No-
tice that the CAPCOM5 COMP4 and CAPCOM4
bits are reserved bits on the 8XC196MC The PI bit
of the INT

PEND1 register will be set when a

Waveform Generator or Compare Module 5 event
occurs and the corresponding bit in the PI

MASK

MASK1 register is set

The 8XC196MC User's Manual should be refer-
enced for details about the interrupts

INT

MASK1 (0031H)

and INT

PEND1 (0012H)

RSV EXTINT

CAPCOM5 COMP4 CAPCOM4 COMP3 CAPCOM3

RSV

RESERVED BIT MUST WRITE AS 0

THIS BIT RESERVED ON 8XC196MC

Figure 3 Interrupt Mask and Status Registers

PTSSRV and PTSSEL Register

Similarly there are differences between 8XC196MC
and 8XC196MD PTS registers The 8XC196MD PTS
registers are shown below Notice the CAPCOM5
COMP4 and CAPCOM4 bits are reserved bits on
the 8XC196MC The PI bit in the PTSSRV will be set
when a Waveform Generator or Compare Module 5
end of PTS interrupt occurs and the corresponding
bit in the PI

MASK register is set The PI PTS vec-

tor can be used when the PI bit in the PTSSEL regis-
ter is set The 8XC196MC User's Manual should be
referenced for details about the PTS

PTSSEL (0004H) and PTSSRV (0006H)

RSV

EXTINT

CAPCOM5

COMP4

CAPCOM4

COMP3 CAPCOM3

COMP2 CAPCOM2 COMP1 CAPCOM1 COMP0 CAPCOM0 AD

DONE TOVF

RSV

RESERVED BIT MUST WRITE AS 0

THIS BIT RESERVED ON 8XC196MC

Figure 4 PTS Select and Service Registers

MASK and PI

PEND Registers

The PI

MASK PI

PEND registers contain the bits

for the Compare Module 5 (COMP5) Waveform Gen-
erator (WG) Timer 1 Overflow (TFI) and Timer 2
Overflow (TF2) mask status flag The diagram be-
low shows the registers Notice that the COMP5 bit
is a reserved bit on the 8XC196MC The 8XC196MC
User's Manual should be referenced for details
about the Waveform Generator Compare Modules
and Timers

MASK (1FBEH) and

PEND (1FBCH Read Only)

RSV

COMP5

RSV

TF2

RSV

TF1

RSV

RESERVED BIT MUST WRITE AS 0

READ AS 1

THIS BIT RESERVED ON 8XC196MC

Figure 5 Peripheral Interrupt Mask

and Status Registers

The PI bit in the INT

PEND1 register is set if a

Waveform Generator event or Compare Module 5
event occurs and the corresponding PI

MASK bit is

set For either of these events to cause an interrupt
the PI bit in the INT

MASK1 register and the corre-

sponding event bit in the PI

MASK register must be

set

Similarly the TOVF bit in the INT

PEND register is

set if Timer 1 or Timer 2 overflow and the corre-
sponding bit in the PI

MASK register is set For ei-

ther of these two events to cause an interrupt the
TOVF bit in the INT

MASK register and the corre-

sponding event bit in the PI

MASK must be set

Upon a PI and or a TOVF interrupt it may be neces-
sary to check if the Compare Module 5 the Wave-
form Generator Timer 1 or Timer 2 event caused
the interrupt The PI

PEND will give this informa-

tion However it should be noted that reading the
PI

PEND register will clear the register So the indi-

vidual bits in the PI

PEND register must be read by

loading PI

PEND into another ``shadow'' register

then checking the ``shadow'' register to see what
event occurred

8XC196MD

Table 3 Interrupt Sources Vectors and Priorities

Interrupt Service

PTS Service

Interrupt Source

Symbol

Name

Vector

Priority

Name

Vector

Priority

Capture Compare5

CAPCOMP5

INT12

2038H

PTS12

2058H

Compare4

COMP4

INT11

2036H

PTS11

2056H

Capture Compare4

CAPCOMP4

INT10

2034H

PTS10

2054H

Interrupt and PTS Vectors

The 8XC196MD has three new interrupt and PTS
vectors which are Capture Compare5 Compare 4
and Capture Compare4 Table 3 shows these inter-
rupt vectors and priorities These are shown as re-
served vectors in the 8XC196MC User's Manual

Frequency Generator

The Frequency Generator (FG) Peripheral which
was not available on the 8XC196MC device is avail-
able on the 8XC196MD device The FG outputs a
programmable-frequency 50% duty cycle waveform
on the FREQOUT pin (P7 7) There are two 8-bit reg-
isters which control the FG peripheral

Frequency Generator Control Register
(FG

CON) at 1FB8h

Frequency Generator Period Count Register
(FG

COUNT) at 1FBAh

The FG

CON can be read or written This register

is loaded with a value which determines the number
of counts necessary for toggling the output The fol-
lowing equation should be used to calculate the
FG

CON value

XTAL

(FG Frequency)

where FG Frequency is from 4 kHz to 1 MHz

The FG

COUNT is loaded with the FG

CON reg-

ister value The FG

COUNT register is decrement-

ed every eighth state time When it reaches 00h the
FG

COUNT register will send a signal to toggle the

output pin and reload the FG

COUNT register with

the

value

the

CON

The

COUNT can only be read not written

The FREQOUT pin (P7 7) must be configured for a
special function to use it for the Frequency Genera-
tor feature

Port 7

Port 7 is an additional bidirectional port that was not
available on the 8XC196MC device Port 7 can be
used as I O or some of the pins have special func-
tions The pins are listed below followed by their
special functions

Table 4 Port 7 Special Function Pins

Special Function

P7 0

CAPCOMP4

P7 1

CAPCOMP5

P7 2

CAPCOMP4

P7 3

CAPCOMP5

P7 4

P7 5

P7 6

P7 7

FREQOUT

The special functions of the pins are selected in the
Port 7 SFRs The Port 2 I O Port section of the
8XC196MC User's Manual can be referenced when
setting up the Port 7 SFRs Port 7 SFRs are located
in the following locations

Table 5 Port 7 Special Function Registers

SFR

Address

MODE

1FD1h

DIR

1FD3h

REG

1FD5h

1FD7h

8XC196MD

PIN DESCRIPTIONS

(Alphabetically Ordered)

Symbol

Function

ACH0 ACH13

Analog inputs to the on-chip A D converter ACH0 7 share the input pins
with P0 0 7 and ACH8 13 share pins with P1 0 5 If the A D is not used

(P0 0 P0 7 P1 0 P1 5)

the port pins can be used as standard input ports

ANGND

Reference ground for the A D converter Must be held at nominally the
same potential as V

ALE ADV(P5 0)

Address Latch Enable or Address Valid output as selected by CCR Both
options allow a latch to demultiplex the address data bus on the signal's
falling edge When the pin is ADV it goes inactive (high) at the end of the
bus cycle ALE ADV is active only during external memory accesses Can be
used as standard I O when not used as ALE ADV

BHE WRH (P5 5)

Byte High Enable or Write High output as selected by the CCR BHE will go
low for external writes to the high byte of the data bus WRH will go low for
external writes where an odd byte is being written BHE WRH is activated
only during external memory writes

BUSWIDTH (P5 7)

Input for bus width selection If CCR bits 1 and 2 e 1 this pin dynamically
controls the bus width of the bus cycle in progress If BUSWIDTH is low an
8-bit cycle occurs If it is high a 16-bit cycle occurs This pin can be used as
standard I O when not used as BUSWIDTH

CAPCOMP0 CAPCOMP5

The EPA Capture Compare pins CAPCOMP0 3 share the pins with
P2 0 P2 3 CAPCOMP4 5 share the pins with P7 0 P7 1 If not used for the

(P2 0 P2 3 P7 0 P7 1)

EPA they can be configured as standard I O pins

CLKOUT

Output of the internal clock generator The frequency is

of the oscillator

frequency It has a 50% duty cycle

COMPARE0 COMPARE5

The EPA Compare pins COMPARE0 3 share the pins with P2 4 P2 7
COMPARE4 5 share the pins with P7 2 P7 3 If not used for the EPA they

(P2 4 P2 7 P7 2 P7 3)

can be configured as standard I O pins

External Access enable pin EA e 0 causes all memory accesses to be
external to the chip EA e 1 causes memory accesses from location 2000H
to 5FFFH to be from the on-chip OTPROM ROM EA e 12 5V causes
execution to begin in the programming mode EA is latched at reset

EXTINT

A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH The input may be selected to be a
positive negative edge or a high low level using WG

PROTECT (1FCEH)

FREQOUT

Programmable frequency output pin The frequency can vary from 4 KHz to 1
MHz (16 MHz input clock) It has a 50% duty cycle Pin may be configured as
standard I O if FREQOUT is not used

INST (P5 1)

INST is high during the instruction fetch from the external memory and
throughout the bus cycle It is low otherwise This pin can be configured as
standard I O if not used as INST

NMI

A positive transition on this pin causes a non-maskable interrupt which
vectors to memory location 203EH If not used it should be tied to V

May

be used by Intel Evaluation boards

PORT0

8-bit high impedance input-only port Also used as A D converter inputs
Port0 pins should not be left floating These pins also used to select
programming modes in the OTPROM devices

PORT1

8-bit high impedance input-only port P1 0 P1 5 are also used as A D
converter inputs In addition P1 2 and P1 3 can be used as Timer 1 clock
input and direction select respectively P1 6 P1 7 can be used as input-only
pins

8XC196MD

PIN DESCRIPTIONS

(Alphabetically Ordered) (Continued)

Symbol

Function

PORT2

8-bit bidirectional I O port All of the Port2 pins are shared with the EPA I O
pins (CAPCOMP0 3 and COMPARE0 3)

PORT3

8-bit bidirectional I O ports with open drain outputs These pins are shared
with the multiplexed address data bus which uses strong internal pullups

PORT4

PORT5

8-bit bidirectional I O port 7 of the pins are shared with bus control signals
(ALE INST WR RD BHE READY BUSWIDTH) Can be used as standard
I O

PORT6

8-bit output port P6 6 and P6 7 output PWM the others are used as the Wave
Form Generator outputs Can be used as standard output ports

PORT7

8-bit bidirectional I O port P7 0 P7 3 can be used as EPA I O pins
(CAPCOMP4 5 and COMPARE4 5) P7 7 can be used as FREQOUT output
pin P7 4 P7 6 are standard I O pins

PWM0 PWM1

Programmable duty cycle Programmable frequency Pulse Width Modulator
pins The duty cycle has a resolution of 256 steps and the frequency can vary

(P6 6 P6 7)

from 122 Hz to 31 KHz (16 MHz input clock) Pins may be configured as
standard output if PWM is not used

RD (P5 3)

Read signal output to external memory RD is low only during external memory
reads Can be used as standard I O when not used as RD

READY (P5 6)

Ready input to lengthen external memory cycles If READY e 0 the memory
controller inserts wait states until the next positive transition of CLKOUT
occurs with READY e 1 Can be used as standard I O when not used as
READY

RESET

Reset input to and open-drain output from the chip Held low for at least 16
state times to reset the chip Input high for normal operation RESET has an
Ohmic internal pullup resistor

T1CLK

Timer 1 Clock input This pin has two other alternate functions ACH10 and
P1 2

(P1 2)

T1DIR

Timer 1 Direction input This pin has two other alternate functions ACH11 and
P1 3

(P1 3)

The programming voltage is applied to this pin It is also the timing pin for the
return from Power Down circuit Connect this pin with a 1 mF capacitor to V

and a 1 MX resistor to V

If the Power Down feature is not used connect

the pin to V

WG1 WG3 WG1 WG3

3 phase output signals and their complements used in motor control
applications The pins can also be configured as standard output pins

(P6 0 P6 5)

WR WRL (P5 2)

Write and Write Low output to external memory WR will go low every external
write WRL will go low only for external writes to an even byte Can be used as
standard I O when not used as WR WRL

XTAL1

Input of the oscillator inverter and the internal clock generator This pin should
be used when using an external clock source

XTAL2

Output of the oscillator inverter

PMODE

Determines the EPROM programming mode

(P0 4 7)

PACT

A low signal in Auto Programming mode indicates that programming is in
process A high signal indicates programming is complete

(P2 5)

8XC196MD

PIN DESCRIPTIONS

(Alphabetically Ordered) (Continued)

Symbol

Function

PALE

A falling edge in Slave Programming Mode and Auto Configuration Byte
Programming Mode indicates that ports 3 and 4 contain valid programming

(P2 1)

address command information (input to slave)

PROG

A falling edge in Slave Programming Mode begins programming A rising edge
ends programming

(P2 2)

PVER

A high signal in Slave Programming Mode and Auto Configuration Byte
Programming Mode indicates the byte programmed correctly

(P2 0)

CPVER

Cumulative Program Verification Pin is high if all locations since entering a
programming mode have programmed correctly

(P2 6)

AINC

Auto Increment Active low input enables the auto increment mode Auto
increment will allow reading or writing of sequential EPROM locations without

(P2 4)

address transactions across the PBUS for each read or write

8XC196MD

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature

Under Bias

40 C to a85 C

Storage Temperature

65 C to a150 C

Voltage from EA or V

to V

or ANGND

0 5V to a13 00V

Voltage on Any Other Pin

to V

or ANGND

0 5V to a7 0V

(1)

Power Dissipation

1 5W

(2)

NOTES
1 This includes V

and EA on ROM or CPU only devices

2 Power dissipation is based on package heat transfer lim-
itations not device power consumption

NOTICE This data sheet contains preliminary infor-
mation on new products in production The specifica-
tions are subject to change without notice Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

Ambient Temperature Under Bias

Digital Supply Voltage

4 50

5 50

REF

Analog Supply Voltage

4 00

5 50

OSC

Oscillator Frequency

MHz

NOTE
ANGND and V

should be nominally at the same potential Also V

and V

SS1

must be at the same potential

DC ELECTRICAL CHARACTERISTICS

(Over Specified Operating Conditions)

Symbol

Parameter

Min

Max

Units

Test Conditions

Input Low Voltage

0 5

0 3 V

Input High Voltage

0 7 V

0 5

Output Low Voltage

0 3

200 mA

Port 2 5 and 7 P6 6 P6 7

0 45

3 2 mA

CLKOUT

1 5

7 mA

OL1

Output Low Voltage on Port 3 4

1 0

15 mA

OL2

Output Low Voltage on

0 45

10 mA

Port 6 0 6 5

Output High Voltage

0 3

e b

200 mA

0 7

e b

3 2 mA

1 5

e b

7 mA

Hysteresis Voltage Width on

0 2

Typical

RESET

8XC196MD

DC ELECTRICAL CHARACTERISTICS

(Over Specified Operating Conditions) (Continued)

Symbol

Parameter

Min Typ

Max

Units

Test Conditions

Input Leakage Current on All Input

0 3V (in RESET)

Only Pins

LI1

Input Leakage Current on Port0

REF

and Port1

Input Low Current on BD Ports

0 3 V

(Note 1)

IL1

Input Low Current on P5 4 and

0 2 V

P2 6 during Reset (Note 3)

Output High Current on P5 4 and

0 7 V

P2 6 during Reset (Note 4)

Active Mode Current in Reset

XTAL1 e 16 MHz

REF

A D Conversion Reference Current

REF

5 5V

IDL

Idle Mode Current

Power-Down Mode Current

REF

5 5V

RST

RESET Pin Pullup Resistor

65k

Pin Capacitance (Any Pin to V

)

TEST

1 0 MHz

NOTES
1 BD (Bidirectional ports) include

P2 0 P2 7 except P2 6
P3 0 P3 7
P4 0 P4 7
P5 0 P5 3
P5 5 P5 7
P7 0 P7 7

2 During normal (non-transient) conditions the following total current limits apply

P6 0 P6 5

40 mA

28 mA

90 mA

42 mA

90 mA

42 mA

P5 CLKOUT

35 mA

P2 P6 6 P6 7 P7

63 mA

3 Maximum current that must be sunk by external device to ensure test mode entry
4 Do not exceed minimum current or device may enter test mode

8XC196MD

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by ``T'' for time The characters in a pair indicate a signal and its
condition respectively Symbols represent the time between the two signal condition points

Conditions

Signals

High

Low

Valid

No Longer Valid

Floating

Address

BHE

CLKOUT

DATA

Buswidth

HOLD

HLDA

ALE ADV

BREQ

WR WRH WRL

XTAL1

READY

Data Out

AC ELECTRICAL CHARACTERISTICS

(Over Specified Operating Conditions)

Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns F

OSC

16 MHz

The system must meet the following specifications to work with the 87C196MD

Symbol

Parameter

Min

Max

Units

Notes

XTAL

Frequency on XTAL1

MHz

OSC

1 F

XTAL

62 5

125

AVYV

Address Valid to READY Setup

2 T

OSC

LLYV

ALE Low to READY Setup

OSC

YLYH

Not READY Time

No Upper Limit

CLYX

READY Hold after CLKOUT Low

OSC

LLYX

READY Hold after ALE Low

OSC

2 T

OSC

AVGV

Address Valid to BUSWIDTH Setup

2 T

OSC

LLGV

ALE Low to BUSWIDTH Setup

OSC

CLGX

Buswidth Hold after CLKOUT Low

AVDV

Address Valid to Input Data Valid

3 T

OSC

RLDV

RD Active to Input Data Valid

OSC

CLDV

CLKOUT Low to Input Data Valid

OSC

RHDZ

End of RD to Input Data Float

OSC

RXDX

Data Hold after RD Inactive

NOTES
1 If Max is exceeded additional wait states will occur
2 If wait states are used add 2 T

OSC

N where N

number of wait states

3 Testing performed at 8 MHz However the device is static by design and will typically operate below 1 Hz
4 These timings are included for compatibility with older

90 and BH products They should not be used for newer high-

speed designs

8XC196MD

AC ELECTRICAL CHARACTERISTICS

(Continued)

Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns F

OSC

16 MHz

The 87C196MD will meet the following timing specifications

Symbol

Parameter

Min

Max

Units

Notes

XHCH

XTAL1 to CLKOUT High or Low

110

CLCL

CLKOUT Cycle Time

2 T

OSC

CHCL

CLKOUT High Period

OSC

CLLH

CLKOUT Falling Edge to ALE Rising

LLCH

ALE Falling Edge to CLKOUT Rising

LHLH

ALE Cycle Time

4 T

OSC

LHLL

ALE High Period

OSC

AVLL

Address Setup to ALE Falling Edge

OSC

LLAX

Address Hold after ALE Falling

OSC

LLRL

ALE Falling Edge to RD Falling

OSC

RLCL

RD Low to CLKOUT Falling Edge

RLRH

RD Low Period

OSC

RHLH

RD Rising Edge to ALE Rising Edge

OSC

RLAZ

RD Low to Address Float

LLWL

ALE Falling Edge to WR Falling

OSC

CLWL

CLKOUT Low to WR Falling Edge

QVWH

Data Stable to WR Rising Edge

OSC

CHWH

CLKOUT High to WR Rising Edge

WLWH

WR Low Period

OSC

WHQX

Data Hold after WR Rising Edge

OSC

WHLH

WR Rising Edge to ALE Rising Edge

OSC

WHBX

BHE INST Hold after WR Rising

OSC

WHAX

AD8 15 Hold after WR Rising

OSC

RHBX

BHE INST Hold after RD Rising

OSC

RHAX

AD8 15 Hold after RD Rising

OSC

NOTES
1 Assuming back to back cycles
2 8-bit bus only
3 If wait states are used add 2 T

OSC

N where N

number of wait states

8XC196MD

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

Max

Units

1 T

XLXL

Oscillator Frequency

16 0

MHz

XLXL

Oscillator Period

62 5

125

XHXX

High Time

XLXX

Low Time

XLXH

Rise Time

XHXL

Fall Time

EXTERNAL CRYSTAL CONNECTIONS

272323 8

NOTE
Keep oscillator components close to chip and use
short direct traces to XTAL1 XTAL2 and V

When

using crystals C1

20 pF C2

20 pF When using

ceramic resonators consult manufacturer for recom-
mended circuitry

EXTERNAL CLOCK CONNECTIONS

272323 9

Required if TTL driver used
Not needed if CMOS driver is used

EXTERNAL CLOCK DRIVE WAVEFORMS

272323 10

An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up This is due to
interaction between the amplifier and its feedback capacitance Once the external signal meets the V

and

specifications the capacitance will not exceed 20 pF

AC TESTING INPUT OUTPUT WAVEFORMS

272323 11

AC Testing inputs are driven at 3 5V for a Logic ``1'' and 0 45V for
a Logic ``0'' Timing measurements are made at 2 0V for a Logic
``1'' and 0 8V for a Logic ``0''

FLOAT WAVEFORMS

272323 12

For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded V

Level occurs

15 mA

8XC196MD

A TO D CHARACTERISTICS

The sample and conversion time of the A D convert-
er in the 8-bit or 10-bit modes is programmed by
loading a byte into the AD

TIME Special Function

TIME register is

functional for all possible values but the accuracy of
the A D converter is only guaranteed for the times
specificed in the operating conditions table

The value loaded into AD

TIME bits 5 6 7 deter-

mines the sample time T

SAM

and is calculated us-

ing the following formula

SAM e

SAM

OSC

) b 2

SAM

Sample time ms

OSC

Processor frequency MHz

SAM e Value loaded into AD

TIME

bits 5 6 7

SAM must be in the range 1 through 7

The value loaded into AD

TIME bits 0 5 deter-

mines the conversion time T

CONV

and is calculated

using the following formula

CONV e

CONV

OSC

) b 3

CONV

Conversion time ms

OSC

Processor frequency MHz

B e 8 for 8-bit conversion
B e 10 for 10-bit conversion
CONV e Value loaded into AD

TIME

bits 0 5

CONV must be in the range 2 through 31

The converter is ratiometric so absolute accuracy is
dependent on the accuracy and stability of V

REF

must be close to V

since it supplies both the

resistor ladder and the analog portion of the convert-
er and input port pins There is also an AD

TEST

SFR that allows for conversion on ANGND and
V

REF

as well as adjusting the zero offset The abso-

lute error listed is WITHOUT doing any adjustments

A D CONVERTER SPECIFICATION

The specifications given assume adherence to the
operating conditions section of this data sheet Test-
ing is performed with V

REF

5 12V and 16 0 MHz

operating frequency After a conversion is started
the device is placed in the IDLE mode until the con-
version is complete

8XC196MD

10-BIT MODE A D OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

Ambient Temperature

Digital Supply Voltage

4 50

5 50

REF

Analog Supply Voltage

4 00

5 50

(1)

SAM

Sample Time

1 0

(2)

CONV

Conversion Time

10 0

20 0

(2)

OSC

Oscillator Frequency

8 0

16 0

MHz

NOTES
ANGND and V

should nominally be at the same potential

1 V

REF

must be within 0 5V of V

2 The value of AD

TIME is selected to meet these specifications

10-BIT MODE A D CHARACTERISTICS

(Over Specified Operating Conditions)

Parameter

Typical

(1)

Min

Max

Units

Resolution

1024

Levels

Bits

Absolute Error

LSBs

Full Scale Error

0 25

0 5

LSBs

Zero Offset Error

0 25

0 5

LSBs

Non-Linearity

1 0

2 0

LSBs

Differential Non-Linearity

LSBs

Channel-to-Channel Matching

0 1

1 0

LSBs

Repeatability

0 25

LSBs

Temperature Coefficients

Offset

0 009

LSB C

Full Scale

0 009

LSB C

Differential Non-Linearity

0 009

LSB C

Off Isolation

(2 3)

Feedthrough

(2)

Power Supply Rejection

(2)

Input Series Resistance

750

(4)

Voltage on Analog Input Pin

ANGND b 0 5

REF

0 5

(5 6)

Sampling Capacitor

DC Input Leakage

3 0

NOTES

An ``LSB'' as used here has a value of approximately 5 mV (See Embedded Microcontrollers and Processors Handbook

for A D glossary of terms)
1 These values are expected for most parts at 25 C but are not tested or guaranteed
2 DC to 100 KHz
3 Multiplexer Break-Before-Make is guaranteed
4 Resistance from device pin through internal MUX to sample capacitor
5 These values may be exceeded if the pin current is limited to

2 mA

6 Applying voltages beyond these specifications will degrade the accuracy of other channels being converted
7 All conversions performed with processor in IDLE mode

8XC196MD

8-BIT MODE A D OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

Ambient Temperature

Digital Supply Voltage

4 50

5 50

REF

Analog Supply Voltage

4 00

5 50

(1)

SAM

Sample Time

1 0

(2)

CONV

Conversion Time

7 0

20 0

(2)

OSC

Oscillator Frequency

8 0

16 0

MHz

NOTES
ANGND and V

should nominally be at the same potential

1 V

REF

must be within 0 5V of V

2 The value of AD

TIME is selected to meet these specifications

8-BIT MODE A D CHARACTERISTICS

(Over the Above Operating Conditions)

Parameter

Typical

(1)

Min

Max

Units

Resolution

256

Level

Bits

Absolute Error

LSBs

Full Scale Error

0 5

LSBs

Zero Offset Error

0 5

LSBs

Non-Linearity

LSBs

Differential Non-Linearity

LSBs

Channel-to-Channel Matching

1 0

LSBs

Repeatability

0 25

LSBs

Temperature Coefficients

Offset

0 003

LSB C

Full Scale

0 003

LSB C

Differential Non-Linearity

0 003

LSB C

Off Isolation

(2 3)

Feedthrough

(2)

Power Supply Rejection

(2)

Input Series Resistance

750

(4)

Voltage on Analog Input Pin

0 5

REF

0 5

(5 6)

Sampling Capacitor

DC Input Leakage

3 0

NOTES

An ``LSB'' as used here has a value of approximately 20 mV (See Embedded Microcontrollers and Processors Handbook

2 mA

6 Applying voltages beyond these specifications will degrade the accuracy of other channels being converted
7 All conversions performed with processor in IDLE mode

8XC196MD

EPROM SPECIFICATIONS

OPERATING CONDITIONS DURING PROGRAMMING

Symbol

Description

Min

Max

Units

Ambient Temperature during Programming

Supply Voltage during Programming

4 5

5 5

(1)

REF

Reference Supply Voltage during Programming

4 5

5 5

(1)

Programming Voltage

12 25

12 75

(2)

EA Pin Voltage

12 25

12 75

(2)

OSC

Oscillator Frequency during Auto

6 0

8 0

MHz

and Slave Mode Programming

OSC

Oscillator Frequency during

6 0

12 0

MHz

Run-Time Programming

NOTES
1 V

and V

REF

should nominally be at the same voltage during programming

2 V

and V

must never exceed the maximum specification or the device may be damaged

3 V

and ANGND should nominally be at the same potential (0V)

4 Load capacitance during Auto and Slave Mode programming

150 pF

AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)

Symbol

Parameter

Min

Max

Units

SHLL

Reset High to First PALE Low

1100

OSC

LLLH

PALE Pulse Width

OSC

AVLL

Address Setup Time

OSC

LLAX

Address Hold Time

100

OSC

PLDV

PROG Low to Word Dump Valid

OSC

PHDX

Word Dump Data Hold

OSC

DVPL

Data Setup Time

OSC

PLDX

Data Hold Time

400

OSC

PLPH

(1)

PROG Pulse Width

OSC

PHLL

PROG High to Next PALE Low

220

OSC

LHPL

PALE High to PROG Low

220

OSC

PHPL

PROG High to Next PROG Low

220

OSC

PHIL

PROG High to AINC Low

OSC

ILIH

AINC Pulse Width

240

OSC

ILVH

PVER Hold after AINC Low

OSC

ILPL

AINC Low to PROG Low

170

OSC

PHVL

PROG High to PVER Valid

220

OSC

NOTE
1 This specification is for the Word Dump Mode For programming pulses use the Modified Quick Pulse Algorithm

8XC196MD

87C196MD DESIGN
CONSIDERATIONS

When an indirect shift during divide occurs the upper
3 bits of the shift count are not masked completely
If the shift count register has the value 32

n where

n e 1 3 5 or 7 the operand will be shifted 32 times
This should have resulted in no shift taking place

8XC196MC to 8XC196MD Design
Considerations

8XC196MC and 8XC196MD are pin compatible
However there were several pins that were not con-
nected (NC) on the 8XC196MC that are I O pins on

the 8XC196MD Port 7 is a bidirectional port added
to the 8XC196MD Port 1 has one additional analog
or digital input that was connected to V

on the

8XC196MC Port 1 also has two additional digital in-
puts See 8XC196MC and 8XC196MD Differences
Section of this data sheet

DATA SHEET REVISION HISTORY

This is the initial data sheet (272323-001) It is valid
for devices with a ``B'' at the end of the topside
tracking number Data sheets are changed as new
device information becomes available Verify with
your local Intel sales office that you have the latest
version before finalizing a design or ordering devic-
es

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