Электронный компонент: LXT362

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LXT362

Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications

Datasheet

The LXT362 is a fully integrated, combination transceiver for T1 ISDN Primary Rate Interface
and general T1 long and short haul applications. It operates over 22 AWG twisted-pair cables
from 0 to 6 kft and offers Line Build Outs and pulse equalization settings for all T1 Line
Interface Unit (LIU) applications.

LXT362 provides both a serial port for microprocessor control (Host mode) as well as stand-
alone operation (Hardware mode). The device incorporates advanced crystal-less digital jitter
attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS encoding/decoding
and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety of
diagnostic loopback modes can also be selected.

Applications

Product Features

s

ISDN Primary Rate Interface (ISDN PRI)

s

CSU/NTU interface to T1 Service

s

Wireless Base Station interface

s

T1 LAN/WAN bridge/routers

s

T1 Mux; Channel Banks

s

Digital Loop Carrier - Subscriber Carrier
Systems

s

Fully integrated transceiver for Long or
Short-Haul T1 interfaces

-- Crystal-less digital jitter attenuation

-- Select either transmit or receive path

s

No crystal or high speed external clock
required

s

Meets or exceeds specifications in ANSI
T1.102, T1.403 and T1.408; and AT&T
Pub 62411

s

Supports 100

(T1 twisted-pair)

applications

s

Selectable receiver sensitivity � fully
restores the received signal after
transmission through a cable with
attenuation of either 0 to 26 dB, or 0 to
36 dB @ 772 kHz

s

Five Pulse Equalization Settings for T1
short-haul applications

s

Four Line Build-Outs for T1 long-haul
applications from 0 dB to -22.5 dB

s

Transmit/receive performance monitors
with Driver Fail Monitor Open and Loss of
Signal outputs

s

Selectable unipolar or bipolar data I/O and
B8ZS encoding/decoding

s

Line attenuation indication output in 2.9 dB
steps

s

QRSS generator/detector for testing or
monitoring

s

Local, remote, and analog loopback, plus
in-band network loopback code generation
and detection

s

Multiple register serial interface for
microprocessor control

s

Available in 28-pin PLCC, 44-pin PQFP,
and 44-pin LQFP packages

As of January 15, 2001, this document replaces the Level One document

Order Number:

249033-001

known as LXT362 -- Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications.

January 2001

Datasheet

Information in this document is provided in connection with Intel

�

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The LXT362 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright � Intel Corporation, 2001

*Third-party brands and names are the property of their respective owners.

Datasheet

3

Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications -- LXT362

Contents

1.0

Pin Assignments and Signal Descriptions

...................................................... 8

1.1

Mode Dependent Signals ...................................................................................... 9

2.0

Functional Description

........................................................................................... 14

2.1

Initialization.......................................................................................................... 14
2.1.1

Reset Operation ..................................................................................... 14

2.2

Transmitter .......................................................................................................... 14
2.2.1

Transmit Digital Data Interface ...............................................................14

2.2.2

Transmit Monitoring................................................................................ 15

2.2.3

Transmit Drivers ..................................................................................... 15

2.2.4

Transmit Idle Mode................................................................................. 15

2.2.5

Transmit Pulse Shape ............................................................................15

2.3

Receiver .............................................................................................................. 16
2.3.1

Receive Equalizer ..................................................................................16

2.3.2

Receive Data Recovery.......................................................................... 16

2.3.3

Receive Digital Data Interface................................................................ 16

2.3.4

Receiver Monitor Mode .......................................................................... 16

2.4

Jitter Attenuation ................................................................................................. 16

2.5

Hardware Mode................................................................................................... 17

2.6

Host Mode ........................................................................................................... 17
2.6.1

Interrupt Handling................................................................................... 18

2.7

Diagnostic Mode Operation................................................................................. 20
2.7.1

Loopback Modes .................................................................................... 21

2.7.2

Internal Pattern Generation and Detection............................................. 24

2.7.3

Error Insertion and Detection ................................................................. 26

2.7.4

Alarm Condition Monitoring .................................................................... 27

2.7.5

Other Diagnostic Reports ....................................................................... 28

3.0

Register Definitions

................................................................................................. 29

4.0

Application Information

.........................................................................................34

4.1

Transmit Return Loss .......................................................................................... 34

4.2

Transformer Data ................................................................................................ 34

4.3

Application Circuits.............................................................................................. 34
4.3.1

Hardware Mode Circuit........................................................................... 35

4.3.2

Host Mode Circuit................................................................................... 36

5.0

Test Specifications

.................................................................................................. 38

6.0

Mechanical Specifications

.................................................................................... 46

LXT362 -- Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications

4

Datasheet

Figures

1

LXT362 Block Diagram ......................................................................................... 7

2

LXT362 Pin Assignments...................................................................................... 8

3

50% Duty Cycle Coding ...................................................................................... 15

4

Serial Port Data Structure ................................................................................... 19

5

TAOS with LLOOP .............................................................................................. 21

6

Local Loopback ................................................................................................... 22

7

Analog Loopback ................................................................................................ 22

8

Remote Loopback ............................................................................................... 23

9

Dual Loopback .................................................................................................... 24

10

TAOS Data Path ................................................................................................. 24

11

QRSS Mode ........................................................................................................ 25

12

Typical Hardware Mode Application.................................................................... 36

13

Typical Host Mode Application ............................................................................ 37

14

1.544 MHz T1 Pulse (DS1 and DSX-1) (See

Table 25

) ...................................... 40

15

Transmit Clock Timing ........................................................................................ 41

16

Receive Clock Timing ......................................................................................... 42

17

Serial Data Input Timing Diagram ....................................................................... 43

18

Serial Data Output Timing Diagram .................................................................... 43

19

Typical T1 Jitter Tolerance at 36 dB ................................................................... 44

20

T1 Jitter Attenuation ............................................................................................ 45

21

Plastic Leaded Chip Carrier Package Specifications .......................................... 46

22

Plastic Quad Flat Package Specifications........................................................... 47

23

Low-Profile Quad Flat Package Specifications ................................................... 48

Datasheet

5

Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications -- LXT362

Tables

1

LXT362 Clock and Data Pins by Mode1 ............................................................... 9

2

LXT362 Control Pins by Mode .............................................................................. 9

3

LXT362 Signal Descriptions ................................................................................ 10

4

CLKE Pin Settings1............................................................................................. 18

5

Control and Operational Mode Selection ............................................................ 19

6

Diagnostic Mode Availability................................................................................ 20

7

Register Addresses ............................................................................................. 29

8

Register and Bit Summary ..................................................................................29

9

Control Register #1 Read/Write, Address (A7-A0) = x010000x .......................... 30

10

Equalizer Control Input Settings.......................................................................... 30

11

Control Register #2 Read/Write, Address (A7-A0) = x010001x .......................... 31

12

Control Register #3 Read/Write, Address (A7-A0) = x010010x .......................... 31

13

Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x.................... 32

14

Transition Status Register Read Only, Address (A7-A0) = x010100x................. 32

15

Performance Status Register Read Only, Address (A7-A0) = x010101x ............ 33

16

Equalizer Status Register Read Only, Address (A7-A0) = x010110x ................. 33

17

Control Register #4 Read/Write, Address (A7-A0) = x010111x .......................... 33

18

Transmit Return Loss .......................................................................................... 34

19

Transformer Specifications for LXT362...............................................................34

20

Recommended Transformers for LXT362........................................................... 35

21

Absolute Maximum Ratings................................................................................. 38

22

Recommended Operating Conditions ................................................................. 38

23

Digital Characteristics.......................................................................................... 39

24

Analog Characteristics ........................................................................................ 39

25

1.544 MHz T1 Pulse Mask Corner Point Specifications...................................... 40

26

Master and Transmit Clock Timing Characteristics (See

Figure 15

)................... 40

27

Receive Timing Characteristics (See

Figure 16

)................................................. 41

28

Serial I/O Timing Characteristics (See

Figure 17

and

Figure 18

)........................42

Document Outline

• Figure 1. LXT362 Block Diagram
• 1.0 Pin Assignments and Signal Descriptions
  • Figure 2. LXT362 Pin Assignments
  • 1.1 Mode Dependent Signals
    • Table 1. LXT362 Clock and Data Pins by Mode1
    • Table 2. LXT362 Control Pins by Mode
    • Table 3. LXT362 Signal Descriptions
• 2.0 Functional Description
  • 2.1 Initialization
    • 2.1.1 Reset Operation
  • 2.2 Transmitter
    • 2.2.1 Transmit Digital Data Interface
    • 2.2.2 Transmit Monitoring
    • 2.2.3 Transmit Drivers
      • Figure 3. 50% Duty Cycle Coding
    • 2.2.4 Transmit Idle Mode
    • 2.2.5 Transmit Pulse Shape
  • 2.3 Receiver
    • 2.3.1 Receive Equalizer
    • 2.3.2 Receive Data Recovery
    • 2.3.3 Receive Digital Data Interface
    • 2.3.4 Receiver Monitor Mode
  • 2.4 Jitter Attenuation
  • 2.5 Hardware Mode
  • 2.6 Host Mode
    • 2.6.1 Interrupt Handling
      • Table 4. CLKE Pin Settings1
      • Figure 4. Serial Port Data Structure
      • Table 5. Control and Operational Mode Selection
  • 2.7 Diagnostic Mode Operation
    • Table 6. Diagnostic Mode Availability
    • 2.7.1 Loopback Modes
      • 2.7.1.1 Local Loopback (LLOOP)
        • Figure 5. TAOS with LLOOP
        • Figure 6. Local Loopback
      • 2.7.1.2 Analog Loopback (ALOOP)
        • Figure 7. Analog Loopback
      • 2.7.1.3 Remote Loopback (RLOOP)
      • 2.7.1.4 Network Loopback (NLOOP)
        • Figure 8. Remote Loopback
      • 2.7.1.5 Dual Loopback (DLOOP)
        • Figure 9. Dual Loopback
    • 2.7.2 Internal Pattern Generation and Detection
      • 2.7.2.1 Transmit All Ones (TAOS)
        • Figure 10. TAOS Data Path
      • 2.7.2.2 QuasiRandom Signal Source (QRSS)
        • Figure 11. QRSS Mode
      • 2.7.2.3 InBand Network Loop Up or Down Code Generator
    • 2.7.3 Error Insertion and Detection
      • 2.7.3.1 Bipolar Violation Insertion (INSBPV)
      • 2.7.3.2 Logic Error Insertion (INSLER)
      • 2.7.3.3 Logic Error Detection (QPD)
      • 2.7.3.4 Bipolar Violation Detection (BPV)
    • 2.7.4 Alarm Condition Monitoring
      • 2.7.4.1 Loss of Signal (LOS)
      • 2.7.4.2 Alarm Indication Signal Detection (AIS)
      • 2.7.4.3 Driver Failure Monitor Open (DFMO)
      • 2.7.4.4 Elastic Store Overflow/Underflow (ESOVR and ESUNF)
    • 2.7.5 Other Diagnostic Reports
      • 2.7.5.1 Receive Line Attenuation Indication
      • 2.7.5.2 BuiltIn Self Test (BIST)
• 3.0 Register Definitions
  • Table 7. Register Addresses
  • Table 8. Register and Bit Summary
  • Table 9. Control Register #1 Read/Write, Address (A7-A0) = x010000x
  • Table 10. Equalizer Control Input Settings
  • Table 11. Control Register #2 Read/Write, Address (A7-A0) = x010001x
  • Table 12. Control Register #3 Read/Write, Address (A7-A0) = x010010x
  • Table 13. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
  • Table 14. Transition Status Register Read Only, Address (A7-A0) = x010100x
  • Table 15. Performance Status Register Read Only, Address (A7-A0) = x010101x
  • Table 16. Equalizer Status Register Read Only, Address (A7-A0) = x010110x
  • Table 17. Control Register #4 Read/Write, Address (A7-A0) = x010111x
• 4.0 Application Information
  • 4.1 Transmit Return Loss
  • 4.2 Transformer Data
  • 4.3 Application Circuits
    • Table 18. Transmit Return Loss
    • Table 19. Transformer Specifications for LXT362
    • Table 20. Recommended Transformers for LXT362
    • 4.3.1 Hardware Mode Circuit
      • Figure 12. Typical Hardware Mode Application
    • 4.3.2 Host Mode Circuit
      • Figure 13. Typical Host Mode Application
• 5.0 Test Specifications
  • Table 21. Absolute Maximum Ratings
  • Table 22. Recommended Operating Conditions
  • Table 23. Digital Characteristics
  • Table 24. Analog Characteristics
  • Figure 14. 1.544 MHz T1 Pulse (DS1 and DSX-1) (See Table 25)
  • Table 25. 1.544 MHz T1 Pulse Mask Corner Point Specifications
  • Table 26. Master and Transmit Clock Timing Characteristics (See Figure 15)
  • Figure 15. Transmit Clock Timing
  • Table 27. Receive Timing Characteristics (See Figure 16)
  • Figure 16. Receive Clock Timing
  • Table 28. Serial I/O Timing Characteristics (See Figure 17 and Figure 18)
  • Figure 17. Serial Data Input Timing Diagram
  • Figure 18. Serial Data Output Timing Diagram
  • Figure 19. Typical T1 Jitter Tolerance at 36 dB
  • Figure 20. T1 Jitter Attenuation
• 6.0 Mechanical Specifications
  • Figure 21. Plastic Leaded Chip Carrier Package Specifications
  • Figure 22. Plastic Quad Flat Package Specifications
  • Figure 23. Low-Profile Quad Flat Package Specifications