7-733
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4016BMS
CMOS Quad Bilateral Switch
Applications
Analog Signal Switching/Multiplexing
Signal Gating
Squelch Control
Chopper
Modulator
Demodulator
Commutating Switch
Digital Signal Switching/Multiplexing
CMOS Logic Implementation
Analog to Digital & Digital to Analog Conversion
Digital Control of Frequency, Impedance, Phase, and
Analog Signal Gain
Description
CD4016BMS Series types are quad bilateral switches intended
for the transmission or multiplexing of analog or digital signals.
Each of the four independent bilateral switches has a single con-
trol signal input which simultaneously biases both the p and n
device in a given switch on or off.
The CD4016BMS is supplied in these 14 lead outline packages:
Braze Seal DIP
H4Q
Frit Seal DIP
H1B
Ceramic Flatpack
H3W
Features
Transmission or Multiplexing of Analog or Digital Signals
High Voltage Type (20V Rating)
20V Digital or
10V Peak-to-Peak Switching
280
Typical On-State Resistance for 15V Operation
Switch On-State Resistance Matched to Within 10
Typ. Over 15V Signal Input Range
High On/Off Output Voltage Ratio: 65dB Typ. at FIS =
10kHz, RL = 10k
High Degree of Linearity: <0.5% Distortion Typ. at FIS
= 1kHz, VIS = 5Vp-p, VDD-VSS
10V, RL = 10k
Extremely Low Off State Switch Leakage Resulting in
Very Low Offset Current and High Effective Off State
Resistance: 100pA Typ. at VDD-VSS = 18V, T
A
= 25
o
C
Extremely High Control Input Impedance (Control cir-
cuit Isolated from Signal Circuit: 10
12
Typ.
Low Crosstalk Between Switches: -50dB Typ. at FIS =
0.9MHz, RL = 1k
Matched Control Input to Signal Output
Capacitance: Reduces Output Signal Transients
Frequency Response, Switch On = 40MHz (Typ.)
100% Tested for Quiescent Current at 20V
Maximum Control Input Current of 1
A at 18V Over Full
Package Temperature Range; 100nA at 18V at +25
o
C
5V, 10V and 15V Parametric Ratings
November 1994
File Number
3296
Pinout
CD4016BMS
TOP VIEW
SIG A IN
SIG A OUT
SIG B IN
SIG B OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
SIG D IN
SIG D OUT
SIG C OUT
SIG C IN
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Functional Diagram
IN/OUT
OUT/IN
OUT/IN
IN/OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
IN/OUT
OUT/IN
OUT/IN
IN/OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SW
A
SIG A
SW
D
SW
B
SW
C
SIG B
SIG C
SIG D
7-734
Specifications CD4016BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
1/32 Inch (1.59mm
0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . .
80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . .
70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1
+25
o
C
-
0.5
A
2
+125
o
C
-
50
A
VDD = 18V, VIN = VDD or GND
3
-55
o
C
-
0.5
A
Input Leakage Current
IIL
VC = VDD or GND
VDD = 20
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
VDD = 18V
3
-55
o
C
-100
-
nA
Input Leakage Current
IIH
VC = VDD or GND
VDD = 20
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
VDD = 18V
3
-55
o
C
-
100
nA
Input/Output Leakage
Current (Switch Off)
IOZL
VDD = 18V, VC = 0V, VIS = 18V,
VOS = 0V
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
3
-55
o
C
-100
-
nA
Input/Output Leakage
Current (Switch Off)
IOZH
VDD = 18V, VIS = 18V, VOS = 0V
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
3
-55
o
C
-
100
nA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1
+25
o
C
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
A
1
+25
o
C
0.7
2.8
V
On-State Resistance
RL = 10K Returned to
VDD-VSS/2
RON10
VIS = VDD or VSS, VDD = 10V
1
+25
o
C
-
660
2
+125
o
C
-
960
3
-55
o
C
-
600
RON10
VIS = 4.75V or 5.75V, VDD = 10V
1
+25
o
C
-
2000
2
+125
o
C
-
2600
3
-55
o
C
-
1870
RON15
VIS = VDD or VSS, VDD = 15V
1
+25
o
C
-
400
2
+125
o
C
-
600
3
-55
o
C
-
360
RON15
VIS = 7.25 or 7.75, VDD = 15V
1
+25
o
C
-
850
2
+125
o
C
-
1230
3
-55
o
C
-
775
Functional
(Note 3)
F
VDD = 2.8V, VIN = VDD or GND
7
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND
7
+25
o
C
VDD = 18V, VIN = VDD or GND
8A
+125
o
C
VDD = 3V, VIN = VDD or GND
8B
-55
o
C
Switch Threshold
RL = 100K to VDD
SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
4.1
-
V
SWTHRH15 VDD = 15V, VC = 2V, VIS = GND
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
14.1
-
V
7-735
Specifications CD4016BMS
Input Voltage Control,
Low (Note 2)
VILC
VDD = 5V, VOS = VDD, VIS = VSS,
and VDD = 5V, VOS = VSS, VIS =
VDD, |IIS| < 10
A
1
+25
o
C
-
0.7
V
2
+125
o
C
-
0.4
V
3
-55
o
C
-
0.9
V
Control Input High
Voltage
(Note 2, Figure 12)
VIS = VSS, and
VIS = VDD
VIHC
VDD = 5V, |IIS| = .16mA, 4.6V <
VOS < 0.4V
1
+25
o
C
3.5
-
V
VDD = 5V, |IIS| = .14mA, 4.6V <
VOS < 0.4V
2
+125
o
C
3.5
-
V
VDD = 5V, |IIS| = .25mA, 4.6V <
VOS < 0.4V
3
-55
o
C
3.5
-
V
VIHC
VDD = 15V, |IIS| = 1.2mA, 13.5V <
VOS < 1.5V
1
+25
o
C
11
-
V
VDD = 15V, |IIS| = 1.1mA, 13.5V <
VOS < 1.5V
2
+125
o
C
11
-
V
VDD = 15V, |IIS| = 1.8mA, 13.5V <
VOS < 1.5V
3
-55
o
C
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented.
2. Go/No Go test with limits applied to inputs
3. VDD = 2.8V/3V, RL = 100K to VDD
VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
Signal Input to Signal
Output
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
9
+25
o
C
-
100
ns
10, 11
+125
o
C, -55
o
C
-
135
ns
Propagation Delay
Turn On
TPZH
TPZL
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
9
+25
o
C
-
70
ns
10, 11
+125
o
C, -55
o
C
-
95
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
0.25
A
+125
o
C
-
7.5
A
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
0.5
A
+125
o
C
-
15
A
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
0.5
A
+125
o
C
-
30
A
Input Voltage Control,
Low
VILC
VDD = 10V, VOS = VDD, VIS =
VSSand VOS = VSS, VIS = VDD
|IIS| < 10
A
1, 2
+25
o
C-55
o
C
-
0.7
V
+125
o
C
-
0.4
V
-55
o
C
-
0.9
V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
7-736
Specifications CD4016BMS
Input Voltage Control,
High (See Figure 12)
VIHC
VDD = 10V, VIS = VDD or GND
1, 2
+25
o
C-55
o
C
7
-
V
1, 2
+125
o
C
7
-
V
1, 2
-55
o
C
7
-
V
Propagation Delay Signal
Input to Signal Output
TPHL
TPLH
VDD = 10V
1, 2, 3
+25
o
C
-
40
ns
VDD = 15V
1, 2, 3
+25
o
C
-
30
ns
Propagation Delay
Turn On
TPZH
TPZL
VDD = 10V
1, 2, 4
+25
o
C
-
40
ns
VDD = 15V
1, 2, 4
+25
o
C
-
30
ns
Input Capacitance
CIN
Any Input
1, 2
+25
o
C
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K. Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25
o
C
-
2.5
A
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-2.8
-0.2
V
N Threshold Voltage
Delta
VNTH
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-
1
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
0.2
2.8
V
P Threshold Voltage
Delta
VPTH
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
-
1
V
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
-
1.35 x
+25
o
C
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - SSI
IDD
0.1
A
ON Resistance
RONDEL10
20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
737
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Specifications CD4016BMS
Schematic Diagram
FIGURE 1. 1 OF 4 IDENTICAL SECTIONS
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
METHOD
TEST
READ AND RECORD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
-0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1
Note 1
2, 3, 9, 10
1, 4-8, 11-13
14
Static Burn-In 2
Note 1
2, 3, 9, 10
7
1, 4-6, 8, 11-14
Dynamic Burn-
In Note 1
-
7
14
2, 3, 9, 10
5, 6, 12, 13
1, 4, 8, 11
Irradiation
Note 2
2, 3, 9, 10
7
1, 4-6, 8, 11-14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
5%, VDD = 18V
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
0.5V
TABLE 6. APPLICABLE SUBGROUPS
(Continued)
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
READ AND RECORD
VDD
VSS
IN/OUT
OUT/IN
CONTROL
VC
n
p
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