4-82
CDP1877,
CDP1877C
Programmable Interrupt Controller (PIC)
Description
The CDP1877 and CDP1877C are programmable 8-level interrupt control-
lers designed for use in CDP1800 series microprocessor systems. They
provide added versatility by extending the number of permissible interrupts
from 1 to N in increments of 8.
When a high to low transition occurs on any of the PIC interrupt lines (IR0 to
IR7), it will be latched and, unless the request is masked, it will cause the
INTERRUPT line on the PIC and consequently the INTERRUPT input on
the CPU to go low.
The CPU accesses the PIC by having interrupt vector register R(1) loaded
with the memory address of the PIC. After the interrupt S3 cycle, this regis-
ter value will appear at the CPU address bus, causing the CPU to fetch an
instruction from the PIC. This fetch cycle clears the interrupt request latch
bit to accept a new high-to-low transition, and also causes the PIC to issue a
long branch instruction (CO) followed by the preprogrammed vector address
written into the PIC's address registers, causing the CPU to branch to the
address corresponding to the highest priority active interrupt request.
If no other unmasked interrupts are pending, the INTERRUPT output of the
PIC will return high. When an interrupt is requested on a masked interrupt
line, it will be latched but it will not cause the PIC INTERRUPT output to go
low. All pending interrupts, masked and unmasked, will be indicated by a "1"
in the corresponding bit of the status register. Reading of the status register
will clear all pending interrupt request latches.
Several PICs can be cascaded together by connecting the INTERRUPT out-
put of one chip to the CASCADE input of another. Each cascaded PIC pro-
vides 8 additional interrupt levels to the system. The number of units
cascadable depends on the amount of memory space and the extent of the
address decoding in the system.
Interrupts are prioritized in descending order; IR7 has the highest and IR0
has the lowest priority.
The CDP1877 and CDP1877C are functionally identical. They differ in that
the CDP1877 has a recommended operating voltage range of 4V to 10.5V,
and the CDP1877C has a recommended operating voltage range of 4V to
6.5V.
Features
Compatible with CDP1800 Series
Programmable Long Branch Vector Address and
Vector Interval
8 Levels of Interrupt Per Chip
Easily Expandable
Latched Interrupt Requests
Hard Wired Interrupt Priorities
Memory Mapped
Multiple Chip Select Inputs to Minimize Address
Space Requirements
Ordering Information
PACKAGE
TEMP.
RANGE
5V
10V
PKG.
NO.
PDIP
-40
o
C to
+85
o
C
CDP1877CE CDP1877E E28.6
March 1997
File Number
1319.2
Pinout
CDP1877, CDP1877C (PDIP)
TOP VIEW
CASCADE
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
TPA
TPB
MWR
MRD
V
SS
V
DD
BUS 6
BUS 5
BUS 4
BUS 3
BUS 1
CS/Ax
CS/Ay
CS
CS
INT
BUS 7
BUS 2
BUS 0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Programming Model
PROGRAMMABLE INTERRUPT CONTROLLER (PIC)
BUS 7
BUS 0
PAGE REGISTER
WRITE
ONLY
A15
A14
A13
A12
A11
A10
A9
A8
BUS 7
BUS 0
CONTROL REGISTER
WRITE
ONLY
B7
B6
B5
B4
B3
B2
B1
B0
BUS 7
BUS 0
MASK REGISTER
WRITE
ONLY
M7
M6
M5
M4
M3
M2
M1
M0
BUS 7
BUS 0
STATUS REGISTER
READ
ONLY
S7
S6
S5
S4
S3
S2
S1
S0
BUS 7
BUS 0
POLLING REGISTER
READ
ONLY
P7
P6
P5
P4
P3
P2
P1
P0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
4-83
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range, (V
DD
)
(All Voltages Referenced to V
SS
Terminal)
CDP1877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1877C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . . .
10mA
Thermal Resistance (Typical)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Device Dissipation Per Output Transistor
T
A
= Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T
A
)
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Storage Temperature Range (T
STG
) . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering)
At distance 1/16
1/32 In. (1.59
0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Static Electrical Specifications
At T
A
= -40 to +85
o
C, V
DD
5%, Unless Otherwise Specified
PARAMETER
CONDITIONS
LIMITS
UNITS
V
O
(V)
V
IN
(V)
V
DD
(V)
CDP1877
CDP1877C
MIN
(NOTE1)
TYP
MAX
MIN
(NOTE1)
TYP
MAX
Quiescent Device
Current
I
DD
-
0, 5
5
-
0.01
50
-
0.02
200
A
-
0, 10
10
-
1
200
-
-
-
A
Output Low Drive (Sink)
Current
I
OL
0.4
0, 5
5
1.6
3.2
-
1.6
3.2
-
mA
0.5
0, 10
10
2.6
5.2
-
-
-
-
mA
Output High Drive
(Source) Current
I
OH
4.6
0, 5
5
-1.15
-2.3
-
-1.15
-2.3
-
mA
9.5
0, 10
10
-2.6
-5.2
-
-
-
-
mA
Output Voltage Low Level
(Note 2)
V
OL
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
Output Voltage High Level
(Note 2)
V
OH
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
Input Low Voltage
V
IL
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
0.5, 9.5
-
10
-
-
3
-
-
-
V
Input High Voltage
V
IH
0.5, 4.5
-
5
3.5
-
-
3.5
-
-
V
0.5, 9.5
-
10
7
-
-
-
-
-
V
Input Leakage Current
I
IN
Any
Input
0, 5
5
-
-
1
-
-
1
A
0, 10
10
-
-
2
-
-
-
A
Three-State Output
Leakage Current
I
OUT
0, 5
0, 5
5
-
10
-4
1
-
10
-4
1
A
0, 10
0, 10
10
-
10
-4
10
-
-
-
A
Operating Device Current
(Note 3)
I
OPER
-
-
5
-
0.5
1.0
-
0.5
1.0
mA
-
-
10
-
1.9
3.0
-
-
-
mA
Input Capacitance
C
IN
-
-
-
-
5
7.5
-
5
7.5
pF
Output Capacitance
C
OUT
-
-
-
-
10
15
-
10
15
pF
NOTES:
1. Typical values are for T
A
= +25
o
C and nominal V
DD
.
2. I
OL
= I
OH
= 1
A
3. Operating current is measured under worst-case conditions in a 3.2MHz CDP1802A system, one PIC access per instruction cycle.
CDP1877, CDP1877C
4-84
Operating Conditions
At T
A
= Full package temperature range. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges:
PARAMETER
LIMITS
UNITS
CDP1877
CDP1877C
MIN
MAX
MIN
MAX
DC Operating Voltage Range
4
10.5
4
6.5
V
Input Voltage Range
V
SS
V
DD
V
SS
V
DD
V
TPA
CS
CS
CA/A
X
CA/A
Y
4-BIT
LATCH
TPB
MWR
MRD
DECODER
CASC
WRITE PAGE REGISTER
WRITE CONTROL REGISTER
WRITE MASK REGISTER
READ STATUS REGISTER
READ POLLING REGISTER
READ LONG BRANCH
INT
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
DATA
BUS
BUFFERS
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
INTERRUPT
LATCH/
STATUS
CONTROL REGISTER
WRITE
CONTROL
REGISTER
MWR
MRD
READ
STATUS
REGISTER
WRITE
MASK
REGISTER
EN
CLEAR
REGISTER
CLEAR
MASK
REGISTER
EN
CLEAR
PRIORITY
INTERVAL
READ POLLING
REGISTER
LOW
EN
VECTOR
UPPER BITS
EN
ADDRESS
HIGH
VECTOR
ADDRESS
WRITE
PAGE
REGISTER
READ
LONG
BRANCH
ENCODER/
VECTOR
ADDRESS
GENERATION
LONG
BRANCH
INSTRUCTION
GENERATE
LOGIC
CS
FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1877
CDP1877, CDP1877C
4-85
PIC Programming Model
INTERNAL REGISTERS
The PIC has three write-only programmable registers and
two read-only registers.
Page Register
This write only register contains the high order vector
address the device will issue in response to an interrupt
request. This high-order address will be the same for any of
the 8 possible interrupt requests; thus, interrupt vectoring dif-
fers only in location within a specified page.
Control Register
The upper nibble of this write-only register contains the low
order vector address the device will issue in response to an
interrupt request. The lower nibble is used for a master
interrupt reset, master mask reset and for interval select.
Functional Definitions for CDP1877 and CDP1877C Terminals
TERMINAL
USAGE
TYPE
V
DD
- V
SS
Power
BUS0 - BUS7
Data Bus - Communicates Information to and from CPU
Bidirectional
IR0 - IR7
Interrupt Request Lines
Input
INTERRUPT
Interrupt to CPU
Output
MRD, MWR
Read/Write Controls from CPU
Input
TPA, TPB
Timing Pulses from CPU
Input
CS, CS
Chip Selects, Enable Chip if Valid during TPA
Input
CS/A
X
, CS/A
Y
Used as a Chip Select during TPA and as a Register Address During Read/Write Operations
Input
CASCADE
Used for Cascading Several PIC Units. The INTERRUPT Output from a Higher
Priority PIC can be Tied to this Input, or the Input can be Tied to V
DD
if Cascading is Not Used.
Input
BUS 7
BUS 0
PAGE REGISTER BITS
WRITE ONLY
A15
A14
A13
A12
A11
A10
A9
A8
BUS 7
BUS 0
CONTROL REGISTER BITS
WRITE ONLY
B7
B6
B5
B4
B3
B2
B1
B0
INTERVAL SELECT DETERMINES
NUMBER OF BYTES ALLOCATED TO
EACH INTERRUPT SERVICE ROUTINE
BIT 1
BIT 0
INTERVAL
0
0
2
0
1
4
1
0
8
1
1
16
MASTER MASK RESET
0 RESETS ALL MASK REGISTER BITS
1 NO CHANGE
MASTER INTERRUPT RESET
0 RESETS ALL INTERRUPT LATCHES, CLEARS ANY
PENDING INTERRUPTS
1 NO CHANGE
SETS UPPER BITS OF THE LOW ORDER VECTOR ADDRESS AS A
FUNCTION OF THE INTERVAL SELECT
CDP1877, CDP1877C
4-86
The Low Order Vector Address will be set according to the table below:
Mask Register
A "1" written into any location in this write only register will
mask the corresponding interrupt request line. All interrupt
inputs (except CASCADE) are maskable.
Status Register
In this read only register a "1" will be present in the
corresponding bit location for every masked or unmasked
pending interrupt.
Polling Register
This read only register provides the low order vector address
and is used to identify the source of interrupt if a polling
technique, rather than interrupt servicing, is used.
RESPONSE TO INTERRUPT (AFTER S3 CYCLE)
The PIC's response to interrogation by the CPU is always 3
bytes long, placed on the data bus in consecutive bytes in
the following format:
First (Instruction) Byte:
LONG BRANCH INSTRUCTION - CO (Hex)
INTERVAL SELECTED NO. OF BYTES
LOW ADDRESS BITS
BIT B7
BIT B6
BIT B5
BIT B4
2
SETS A7
SETS A6
SETS A5
SET A4
4
SETS A7
SETS A6
SETS A5
X
8
SETS A7
SETS A6
X
X
16
SETS A7
X
X
X
NOTES:
1. X = Don't Care
2. All Don't Care addresses and addresses A0-A3 are determined by interrupt request.
BUS 7
BUS 0
MASK REGISTER BITS
WRITE ONLY
M7
M6
M5
M4
M3
M2
M1
M0
BUS 7
BUS 0
STATUS REGISTER BITS
READ ONLY
S7
S6
S5
S4
S3
S2
S1
S0
BUS 7
BUS 0
POLLING REGISTER BITS
READ ONLY
P7
P6
P5
P4
P3
P2
P1
P0
BUS 7
BUS 0
1
1
0
0
0
0
0
0
CDP1877, CDP1877C
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