File Number

4321.4

HI5728

10-Bit, 125/60MSPS, Dual High Speed
CMOS D/A Converter

The HI5728 is a 10-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. Operating from a
single +5V or +3V supply, the converter provides 20.48mA of
full scale output current and includes an input data register.
Low glitch energy and excellent frequency domain
performance are achieved using a segmented architecture.
A 60MSPS version and an 8-bit (HI5628) version are also
available. Comparable single DAC solutions are the HI5760
(10-bit) and the HI5660 (8-bit). This DAC is a member of the
CommLinkTM family of communication devices.

Features

· Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS

· Low Power . . . . . . . . . . . . . . . 330mW at 5V, 54mW at 3V

· Integral Linearity Error . . . . . . . . . . . . . . . . . . . . .

1 LSB

· Differential Linearity . . . . . . . . . . . . . . . . . . . . . .

0.5 LSB

· Gain Matching (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .0.5%

· SFDR at 5MHz Output . . . . . . . . . . . . . . . . . . . . . . .68dBc

· Single Power Supply from +5V to +3V

· CMOS Compatible Inputs

· Excellent Spurious Free Dynamic Range

· Internal Voltage Reference

· Dual 10-Bit D/A Converters on a Monolithic Chip

Applications

· Wireless Local Loop

· Direct Digital Frequency Synthesis

· Wireless Communications

· Signal Reconstruction

· Arbitrary Waveform Generators

· Test Equipment/Instrumentation

· High Resolution Imaging Systems

Pinout

HI5728

(LQFP)

TOP VIEW

Ordering Information

PART

NUMBER

TEMP.

RANGE

(

PACKAGE

PKG. NO.

MAX

CLOCK

SPEED

HI5728IN

-40 to 85 48 Ld LQFP

Q48.7x7A

125MHz

HI5728/6IN

-40 to 85 48 Ld LQFP

Q48.7x7A

60MHz

HI5728EVAL1

Evaluation Platform

125MHz

2
3

32
31

30
29

11
12

13 14 15 16

QD6

QD5

QD4

QD3
QD2
QD1

QD0 (LSB)

DGND

AGND

ID6

ID5

ID4
ID3

ID2

SLEEP

DGND

ID1

ID0 (LSB)

ID7

ID8

ID9 (MSB)

DGND

QCLK

DGND

QD9 (MSB)

QD8

QD7

ICLK

GND

ICOMP1

REFLO

IOUT

IOUTB

GND

QOUTB

QOUT

FSADJ

REFIO

QCOMP1

Data Sheet

July 1999

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil Corporation 1999

CommLinkTM is a trademark of Intersil Corporation.

Functional Block Diagram

UPPER

VOLTAGE

REFERENCE

(LSB) ID0

ID1

ID2

ID3

ID4

ID5

ID6

(MSB) ID9

ICLK

ID7

ID8

5-BIT

DECODER

REFIO

LATCH

AGND

DGND

LATCH

CASCODE

CURRENT

SOURCE

SWITCH

MATRIX

BIAS

GENERATION

INT/EXT

FSADJ

REFERENCE

INT/EXT

SELECT

REFLO

31 MSB

SEGMENTS

5 LSBs

ICOMP1

SLEEP

IOUTA

IOUTB

UPPER

(LSB) QD0

QD1

QD2

QD3

QD4

QD5

QD6

QCLK

QD7

QD8

5-BIT

DECODER

LATCH

CASCODE

CURRENT

SOURCE

SWITCH

MATRIX

31 MSB

SEGMENTS

5 LSBs

QCOMP1

QOUTA QOUTB

HI5728

Typical Applications Circuit

IOUTB

IOUTA

+5V OR +3V SUPPLY

0.1

FERRITE

BEAD

SET

1
2
3
4
5
6

7
8

32
31
30
29
28
27
26
25

10
11
12

13 14 15 16

(POWER PLANE)

ID7

ID6
ID5

ID8

ID9 (MSB)

QD9 (MSB)

ID4
ID3
ID2
ID1

ID0 (LSB)

QD8

QD7

QD6
QD5
QD4
QD3
QD2
QD1
QD0 (LSB)

CLK

0.1

SLEEP

0.1

DGND
NC (GROUND)

AGND

ICOMP1

0.1

GND

QOUTA

QOUTB

0.1

REFIO

QCOMP1

0.1

AGND

0.1

DGND

NC (GROUND)

+5V OR +3V SUPPLY

0.1

FERRITE

BEAD

(POWER PLANE)

ANALOG
GROUND
PLANE

DIGITAL
GROUND
PLANE

NOTE: ICOMP1 AND QCOMP1
PINS (24, 14) MUST BE TIED
TOGETHER EXTERNALLY

HI5728

Pin Descriptions

PIN NO.

PIN NAME

PIN DESCRIPTION

39-30

QD9 (MSB) Through

QD0 (LSB)

Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
channel.

1-6, 48-46

ID9 (MSB) Through

ID0 (LSB)

Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I chan-
nel.

SLEEP

Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20

A active pull-down current.

REFLO

Connect to analog ground to enable internal 1.2V reference or connect to AV

to disable.

REFIO

Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1

F cap to ground when internal reference is enabled.

FSADJ

Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x I

FSADJ

14, 24

ICOMP1, QCOMP1

Reduces noise. Connect each to AV

with 0.1

F capacitor near each pin. The ICOMP1 and QCOMP1

pins MUST be tied together externally.

13, 18, 19, 25

AGND

Analog Ground Connections.

IOUTB

The complimentary current output of the I channel. Bits set to all 0s gives full scale current.

IOUTA

Current output of the I channel. Bits set to all 1s gives full scale current.

QOUTB

The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.

QOUTA

Current output of the Q channel. Bits set to all 1s gives full scale current.

11, 27

No Connect. Recommended: connect to ground.

12, 26

Analog Supply (+2.7V to +5.5V).

10, 28, 41, 44

DGND

Digital Ground.

9, 29, 40, 45

Supply voltage for digital circuitry (+2.7V to +5.5V).

ICLK

Clock input for I channel. Positive edge of clock latches data.

QCLK

Clock input for Q channel. Positive edge of clock latches data.

HI5728

Absolute Maximum Ratings

Thermal Information

Digital Supply Voltage DV

to DCOM . . . . . . . . . . . . . . . . . +5.5V

Analog Supply Voltage AV

to ACOM . . . . . . . . . . . . . . . . . +5.5V

Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . . . . DV

+0.3V

Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . .

Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AV

+0.3V

Analog Output Current (I

OUT

) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to 85

Thermal Resistance (Typical, Note 1)

(

C/W)

TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Power Dissipation

TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .930mW

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

= DV

5V, V

REF

= Internal 1.2V, IOUTFS = 20mA, T

= 25

C for All Typical Values. Data given is

per channel except for `Power Supply Characteristics.'

PARAMETER

TEST CONDITIONS

HI5728IN

= -40

C TO 85

UNITS

MIN

TYP

MAX

SYSTEM PERFORMANCE (Per Channel)

Resolution

Bits

Integral Linearity Error, INL

"Best Fit" Straight Line (Note 7)

-1

0.5

LSB

Differential Linearity Error, DNL

(Note 7)

-0.5

0.25

+0.5

LSB

Offset Error, I

(Note 7)

-0.025

+0.025

% FSR

Offset Drift Coefficient

(Note 7)

0.1

ppm

FSR/

Full Scale Gain Error, FSE

With External Reference (Notes 2, 7)

-10

+10

% FSR

With Internal Reference (Notes 2, 7)

-10

+10

% FSR

Full Scale Gain Drift

With External Reference (Note 7)

ppm

FSR/

With Internal Reference (Note 7)

100

ppm

FSR/

Gain Matching Between Channels

-0.5

0.1

0.5

I/Q Channel Isolation

OUT

= 10MHz

Output Voltage Compliance Range

(Note 3)

-0.3

1.25

Full Scale Output Current, I

DYNAMIC CHARACTERISTICS (Per Channel)

Maximum Clock Rate, f

CLK

(Note 3)

125

MHz

Output Settling Time, (t

SETT

)

0.1% (

1 LSB, equivalent to 9 Bits) (Note 7)

0.05% (

1/2 LSB, equivalent to 10 Bits) (Note 7)

Singlet Glitch Area (Peak Glitch)

= 25

(Note 7)

pV·s

Output Rise Time

Full Scale Step

1.5

Output Fall Time

Full Scale Step

1.5

Output Capacitance

Output Noise

IOUTFS = 20mA

pA/

IOUTFS = 2mA

pA/

HI5728

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