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December 1996

HIP4080

80V/2.5A Peak, High Frequency

Full Bridge FET Driver

Features

· Drives N-Channel FET Full Bridge Including High Side

Chop Capability

· Bootstrap Supply Max Voltage to 95V

· Drives 1000pF Load at 1MHz in Free Air at 50

C with

Rise and Fall Times of 10ns (Typ)

· User-Programmable Dead Time

· Charge-Pump and Bootstrap Maintain Upper Bias

Supplies

· DIS (Disable) Pin Pulls Gates Low

· Input Logic Thresholds Compatible with 5V to 15V

Logic Levels

· Very Low Power Consumption

Applications

· Medium/Large Voice Coil Motors

· Full Bridge Power Supplies

· Class D Audio Power Amplifiers

· High Performance Motor Controls

· Noise Cancellation Systems

· Battery Powered Vehicles

· Peripherals

· U.P.S.

Description

The HIP4080 is a high frequency, medium voltage Full Bridge
N-Channel FET driver IC, available in 20 lead plastic SOIC and
DIP packages. The HIP4080 includes an input comparator,
used to facilitate the "hysteresis" and PWM modes of operation.
Its HEN (high enable) lead can force current to freewheel in the
bottom two external power MOSFETs, maintaining the upper
power MOSFETs off. Since it can switch at frequencies up to
1MHz, the HIP4080 is well suited for driving Voice Coil Motors,
switching amplifiers in class D high-frequency switching audio
amplifiers and power supplies.

HIP4080 can also drive medium voltage brush motors, and
two HIP4080s can be used to drive high performance step-
per motors, since the short minimum "on-time" can provide
fine micro-stepping capability.

Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.

The similar HIP4081 IC allows independent control of all 4
FETs in an Full Bridge configuration.

See also, Application Note AN9324 for the HIP4080.

Similar part, HIP4080A, includes under voltage circuitry
which doesn't require the circuitry shown in Figure 30 of this
data sheet.

Pinout

HIP4080 (PDIP, SOIC)

TOP VIEW

Ordering Information

PART

NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

NO.

HIP4080IP

-40 to 85

20 Lead PDIP

E20.3

HIP4080IB

-40 to 85

20 Lead SOIC

M20.3

BHB

HEN

DIS

OUT

IN+

HDEL

IN-

LDEL

AHB

BHO

BLO

BLS

BHS

ALS

ALO

AHS

AHO

File Number

3178.10

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

and V

. . . . . . . . . . . . . . . . . . . -0.3V to 16V

Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

+0.3V

Voltage on AHS, BHS . . . . -6.0V (Transient) to 80V (25

C to 125

Voltage on AHS, BHS . . . . -6.0V (Transient) to 70V (-55

C to 125

Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHBV

AHS, BHS

-0.3V to V

AHS, BHS

+16VVoltage on

Voltage on ALO, BLO . . . . . . . . . . . . V

ALS, BLS

-0.3V to V

+0.3V

Voltage on AHO, BHO . . . . . . V

AHS, BHS

-0.3V to V

AHB, BHB

+0.3V

Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
NOTE: All Voltages relative to pin 4, V

, unless otherwise specified.

Thermal Resistance (Typical, Note 1)

(

C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Power Dissipation at 85

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470mW
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mW

Storage Temperature Range . . . . . . . . . . . . . . . . . . -65

C to 150

Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . 125

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Operating Conditions

Supply Voltage, V

and V

. . . . . . . . . . . . . . . . . . . +8V to +15V

Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . . V

AHS, BHS

+5V to V

AHS, BHS

+15V

Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500

A to -50

Operating Ambient Temperature Range . . . . . . . . . . .-40

C to 85

Electrical Specifications

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 100K,

and T

= 25

C, Unless Otherwise Specified

PARAMETERS

SYMBOL

TEST CONDITIONS

= 25

= - 40

TO 125

UNITS

MIN

TYP

MAX

MIN

MAX

SUPPLY CURRENTS AND CHARGE PUMPS

Quiescent Current

IN- = 2.5V, Other Inputs = 0V

10.5

Operating Current

DDO

Outputs switching f = 500kHz

Quiescent Current

IN- = 2.5V, Other Inputs = 0V,
I

ALO

= I

BLO

= 0

100

Operating Current

CCO

f = 500kHz, No Load

1.5

2.0

0.8

AHB, BHB Quiescent Current -
Qpump Output Current

AHB

, I

BHB

IN- = 2.5V, Other Inputs = 0V, I

AHO

BHO

= 0, V

= V

AHB

BHB

= 10V

-50

-30

-15

-60

-10

AHB, BHB Operating Current

AHBO

BHBO

f = 500kHz, No Load

0.5

0.9

1.3

0.4

1.7

AHS, BHS, AHB, BHB Leakage Current

HLK

AHS

= V

BHS

= V

AHB

= V

BHB

= 95V

0.02

1.0

AHB-AHS, BHB-BHS Qpump
Output Voltage

AHB

- V

AHS

BHB

- V

BHS

AHB

= I

AHB

= 0, No Load

11.5

12.6

14.0

10.5

14.5

INPUT COMPARATOR PINS: IN+, IN-, OUT

Offset Voltage

Over Common Mode Voltage Range

-10

+10

-15

+15

Input Bias Current

0.5

Input Offset Current

-1

-2

Input Common Mode Voltage Range

CMVR

-1.5

Voltage Gain

AVOL

V/mV

OUT High Level Output Voltage

IN+ > IN-, I

= -300

-0.4

- 0.5

OUT Low Level Output Voltage

IN+ < IN-, I

= 300

0.3

0.4

High Level Output Current

OUT

-9

-7

-4

-11

-2

Low Level Output Current

OUT

INPUT PINS: DIS

Low Level Input Voltage

Full Operating Conditions

1.0

0.8

High Level Input Voltage

Full Operating Conditions

2.5

2.7

Input Voltage Hysteresis

HIP4080

Low Level Input Current

= 0V, Full Operating Conditions

-130

-100

-75

-135

-65

High Level Input Current

= 5V, Full Operating Conditions

-1

-10

+10

INPUT PINS: HEN

Low Level Input Voltage

Full Operating Conditions

1.0

0.8

High Level Input Voltage

Full Operating Conditions

2.5

2.7

Input Voltage Hysteresis

Low Level Input Current

= 0V, Full Operating Conditions

-260

-200

-150

-270

-130

High Level Input Current

= 5V, Full Operating Conditions

-1

-10

+10

TURN-ON DELAY PINS: LDEL AND HDEL

LDEL, HDEL Voltage

HDEL,

HDEL

= I

LDEL

= -100

4.9

5.1

5.3

4.8

5.4

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO

Low Level Output Voltage

OUT

= 100mA

.70

0.85

1.0

0.5

1.1

High Level Output Voltage

- V

OUT

= -100mA

0.8

0.95

1.1

0.5

1.2

Peak Pull-up Current

OUT

= 0V

1.7

2.6

3.8

1.4

4.1

Peak Pull-down Current

OUT

= 12V

1.7

2.4

3.3

1.3

3.6

Electrical Specifications

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 100K,

and T

= 25

C, Unless Otherwise Specified (Continued)

PARAMETERS

SYMBOL

TEST CONDITIONS

= 25

= - 40

TO 125

UNITS

MIN

TYP

MAX

MIN

MAX

Switching Specifications

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 10K,

= 1000pF, and T

= 25

C, Unless Otherwise Specified

PARAMETERS

SYMBOL

TEST CONDITIONS

= 25

= - 40

TO 125

UNITS

MIN

TYP MAX

MIN

MAX

Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO)

LPHL

Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO)

HPHL

110

Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO)

LPLH

HDEL

= R

LDEL

= 10K

Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO)

HPLH

HDEL

= R

LDEL

= 10K

110

140

Rise Time

Fall Time

Turn-on Input Pulse Width

PWIN-ON

HDEL

= R

LDEL

= 10K

Turn-off Input Pulse Width

PWIN-OFF

HDEL

= R

LDEL

= 10K

Disable Turn-off Propagation Delay
(DIS - Lower Outputs)

DISLOW

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

DISHIGH

105

Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)

DLPLH

Refresh Pulse Width (ALO and BLO)

REF-PW

160

260

380

140

420

Disable to Upper Enable (DIS - AHO and BHO)

UEN

335

500

550

HEN-AHO, BHO Turn-off, Propagation Delay

HEN-PHL

HDEL

= R

LDEL

= 10K

HEN-AHO, BHO Turn-on, Propagation Delay

HEN-PLH

HDEL

= R

LDEL

= 10K

110

TRUTH TABLE

INPUT

OUTPUT

IN+ > IN-

HEN

DIS

ALO

AHO

BLO

BHO

HIP4080

Pin Descriptions

PIN

NUMBER

SYMBOL

DESCRIPTION

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30

A out of this

pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

HEN

High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO
drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs.
The pin can be driven by signal levels of 0V to 15V (no greater than V

). An internal 100

A pull-up to V

will

hold HEN high, so no connection is required if high-side and low-side outputs are to be controlled by IN+/IN-
inputs.

DIS

DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of
0V to 15V (no greater than V

). An internal 100

A pull-up to V

will hold DIS high if this pin is not driven.

Chip negative supply, generally will be ground.

OUT

OUTput of the input control comparator. This output can be used for feedback and hysteresis.

IN+

Non-inverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level
outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level out-
puts and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs.
HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode,
dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9).

IN-

Inverting input of control comparator. See IN+ (Pin 6) description.

HDEL

High-side turn-on DELay. Connect resistor from this pin to V

to set timing current that defines the turn-on delay

of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.

LDEL

Low-side turn-on DELay. Connect resistor from this pin to V

to set timing current that defines the turn-on delay

of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30

A out of this

pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

ALO

A Low-side Output. Connect to gate of A Low-side power MOSFET.

ALS

A Low-side Source connection. Connect to source of A Low-side power MOSFET.

Positive supply to gate drivers. Must be same potential as V

(Pin 16). Connect to anodes of two bootstrap

diodes.

Positive supply to lower gate drivers. Must be same potential as V

(Pin 15). De-couple this pin to V

(Pin 4).

BLS

B Low-side Source connection. Connect to source of B Low-side power MOSFET.

BLO

B Low-side Output. Connect to gate of B Low-side power MOSFET.

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

BHO

B High-side Output. Connect to gate of B High-side power MOSFET.

HIP4080

Typical Performance Curves

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V,

HDEL

= R

LDEL

= 100K, and T

= 25

C, Unless Otherwise Specified

FIGURE 4. QUIESCENT I

SUPPLY CURRENT vs V

SUPPLY VOLTAGE

FIGURE 5. I

DDO

, NO-LOAD I

SUPPLY CURRENT vs

FREQUENCY (kHz)

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs

FREQUENCY (LOAD = 1000pF)

FIGURE 7. I

CCO

, NO-LOAD I

SUPPLY CURRENT vs

FREQUENCY (kHz) TEMPERATURE

FIGURE 8. I

AHB

, I

BHB

, NO-LOAD FLOATING SUPPLY BIAS

CURRENT vs FREQUENCY

FIGURE 9. COMPARATOR INPUT CURRENT I

TEMPERATURE AT V

= 5V

2.0

4.0

6.0

8.0

10.0

12.0

14.0

SUPPL

Y CURRENT (mA)

SUPPLY VOLTAGE (V)

12.5

12.0

11.5

11.0

10.5

200

400

600

800

1000

SUPPL

Y CURRENT (mA)

SWITCHING FREQUENCY (kHz)

100

200

300

400

500

600

700

800

900 1000

0.0

5.0

10.0

15.0

20.0

25.0

30.0

FLO

TING SUPPL

Y BIAS CURRENT (mA)

SWITCHING FREQUENCY (kHz)

100

200

300

400

500

600

700

800

900 1000

0.0

1.0

2.0

3.0

4.0

5.0

SUPPL

Y CURRENT (mA)

SWITCHING FREQUENCY (kHz)

125

-40

200

400

600

800

1000

-0.2

0.2

0.6

1.0

1.4

1.8

FREQUENCY (kHz)

FLO

TING SUPPL

Y BIAS CURRENT (mA)

-40

-20

100

120

0.5

1.0

COMP

ARA

OR INPUT CURRENT (

JUNCTION TEMPERATURE (

HIP4080

FIGURE 10. DIS LOW LEVEL INPUT CURRENT I

TEMPERATURE

FIGURE 11. HEN LOW LEVEL INPUT CURRENT I

TEMPERATURE

FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP

VOLTAGE vs TEMPERATURE

FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION

DELAY T

DISHIGH

vs TEMPERATURE

FIGURE 14. DISABLE TO UPPER ENABLE T

UEN

PROPAGATION DELAY vs TEMPERATURE

FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION

DELAY T

DISLOW

vs TEMPERATURE

Typical Performance Curves

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V,

HDEL

= R

LDEL

= 100K, and T

= 25

C, Unless Otherwise Specified (Continued)

-50

-25

100

125

-120

-110

-100

-90

W LEVEL INPUT CURRENT (

JUNCTION TEMPERATURE (

-40

-20

100

120

-230

-220

-210

-200

-190

-180

W LEVEL INPUT CURRENT (

JUNCTION TEMPERATURE (

-40

-20

100

120

10.0

11.0

12.0

13.0

14.0

15.0

NO-LO

AD FLO

TING CHARGE PUMP V

JUNCTION TEMPERATURE (

-40

-20

100

120

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

300

320

340

360

380

400

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

HIP4080

FIGURE 16. T

REF-PW

REFRESH PULSE WIDTH vs

TEMPERATURE

FIGURE 17. DISABLE TO LOWER ENABLE T

DLPLH

PROPAGATION DELAY vs TEMPERATURE

FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY T

HPHL

vs TEMPERATURE

FIGURE 19. UPPER TURN-ON PROPAGATION DELAY T

HPLH

vs TEMPERATURE

FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY T

LPHL

vs TEMPERATURE

FIGURE 21. LOWER TURN-ON PROPAGATION DELAY T

LPLH

TEMPERATURE

Typical Performance Curves

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V,

HDEL

= R

LDEL

= 100K, and T

= 25

C, Unless Otherwise Specified (Continued)

-40

-20

100

120

175

225

275

325

375

REFRESH PULSE WIDTH (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

40.0

50.0

60.0

70.0

80.0

90.0

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

40.0

50.0

60.0

70.0

80.0

90.0

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

40.0

50.0

60.0

70.0

80.0

90.0

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

40.0

50.0

60.0

70.0

80.0

90.0

TION DELA

Y (ns)

JUNCTION TEMPERATURE (

HIP4080

FIGURE 22. GATE DRIVE FALL TIME T

vs TEMPERATURE

FIGURE 23. GATE DRIVE RISE TIME T

vs TEMPERATURE

FIGURE 24. V

LDEL

, V

HDEL

VOLTAGE vs TEMPERATURE

FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, V

- V

BIAS SUPPLY AND TEMPERATURE AT 100mA

FIGURE 26. LOW LEVEL OUTPUT VOLTAGE V

vs BIAS

SUPPLY AND TEMPERATURE AT 100mA

FIGURE 27. PEAK PULLDOWN CURRENT I

vs BIAS SUPPLY

VOLTAGE

Typical Performance Curves

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V,

HDEL

= R

LDEL

= 100K, and T

= 25

C, Unless Otherwise Specified (Continued)

-40

-20

100

120

8.5

9.5

10.5

11.5

12.5

13.5

TE DRIVE F

ALL TIME (ns)

JUNCTION TEMPERATURE (

-40

-20

100

120

8.5

9.5

10.5

11.5

12.5

13.5

TURN-ON RISE TIME (ns)

JUNCTION TEMPERATURE (C)

-40

-20

100

120

4.0

4.5

5.0

5.5

6.0

HDEL, LDEL INPUT V

GE (V)

JUNCTION TEMPERATURE (

250

500

750

1000

1250

1500

- V

(mV)

BIAS SUPPLY VOLTAGE (V)

125

-40

250

500

750

1000

1250

1500

(mV)

BIAS SUPPLY VOLTAGE (V)

125

-40

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

TE DRIVE SINK CURRENT (A)

, V

AHB

, V

BHB

(V)

HIP4080

FIGURE 28. PEAK PULLUP CURRENT I

O+

vs SUPPLY

VOLTAGE

FIGURE 29. LOW VOLTAGE BIAS CURRENT I

AND I

(LESS QUIESCENT COMPONENT) vs
FREQUENCY AND GATE LOAD CAPACITANCE

FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs

FREQUENCY AND BUS VOLTAGE

FIGURE 31. MINIMUM DEAD-TIME vs DEL RESISTANCE

Typical Performance Curves

= V

AHB

= V

BHB

= 12V, V

= V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V,

HDEL

= R

LDEL

= 100K, and T

= 25

C, Unless Otherwise Specified (Continued)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

TE DRIVE SINK CURRENT (A)

, V

AHB

, V

BHB

(V)

100

1000

500

200

0.1

100

500

0.5

200

0.2

W V

GE BIAS CURRENT (mA)

SWITCHING FREQUENCY (kHz)

3,000

1,000

10,000

100

1000

200

500

100

1000

200

500

LEVEL-SHIFT CURRENT (

SWITCHING FREQUENCY (kHz)

60V

40V

80V

20V

100

150

200

250

120

150

HDEL/LDEL RESISTANCE (k

)

DEAD-TIME (ns)

HIP4080

HIP4080 Power-up Application Information

The HIP4080 H-Bridge Driver IC requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-Bridge power MOS-
FETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.

The HIP4080 does not have an input protocol like the
HIP4081 that keeps both lower power MOSFETs off other
than through the DIS pin. IN+ and IN- are inputs to a com-
parator that control the bridge in such a way that only one of
the lower power devices is on at a time, assuming DIS is low.
However, keeping both lower MOSFETs off can be accom-

plished by controlling the lower turn-on delay pin, LDEL,
while the chip is enabled, as shown in Figure 32. Pulling
LDEL to V

will indefinitely delay the lower turn-on delays

through the input comparator and will keep the lower MOS-
FETs off. With the lower MOSFETs off and the chip enabled,
i.e. DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+/IN- switch a full cycle while LDEL
is held high, to avoid shoot-through. This start-up procedure
can be initiated by the supply voltage and/or the chip enable
command by the circuit in Figure 32.

1 BHB

HEN

DIS

OUT

IN+

HDEL

IN-

LDEL

AHB

BHO

BLO

BLS

BHS

ALS

ALO

AHS

AHO

100K

RDEL

0.1

2N3906

ENABLE

56K

8.2V

56K

100K

FIGURE 32.

DIS

LDEL

=10ms

8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)

12V, FINAL VALUE

5.1V

NOTES:

2. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If

the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+
and IN- pins must cycle at least once.

3. Another product, HIP4080A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry.

FIGURE 33. TIMING DIAGRAM FOR FIGURE 32

HIP4080

R21

R22

R23

JMPR1

R24

R30

R31

R34

CR2

CR1

JMPR5

JMPR3

JMPR2

JMPR4

R33

B+

IN2

IN1

OUT/BLI

IN-/AHI

COM

IN+/ALI

+12V

BLS

HEN/BHI

ALS

CD4069UB

HIP4080/81

SECTION

CONTROL LOGIC

POWER SECTION

DRIVER SECTION

AHO

AHB

AHS

LDEL

ALO

HDEL

ALS

IN-/AHI

IN+/ALI

OUT/BLI

BLS

BLO

DIS

BHS

HEN/BHI

BHO

BHB

R29

CD4069UB

ENABLE

100K

0.1MFD

TO DIS

2N3906

56K

8.2V

56K

NOTES:

4. Circuit inside dashed area must be hardwired and

is not included on the evaluation board.

5. Device CD4069UB PIN 7 = COM, Pin 14 = +12V.

6. Components L1, L2, C1, C2, CX, CY, R30, R31,

are not supplied. refer to Application Note for de-
scription of input logic operation to determine
jumper locations for JMPR1 - JMPR4.

FIGURE 34. HIP4080 EVALUATION PC BOARD SCHEMATIC

Supplemental Information for HIP4080
and HIP4081 Power-Up Application

The HIP4080 and HIP4081 H-Bridge Driver ICs require
external circuitry to assure reliable start-up conditions of the
upper drivers. If not addressed in the application, the
H-bridge power MOSFETs may be exposed to shoot-
through current, possibly leading to MOSFET failure. Follow-
ing the instructions below will result in reliable start-up.

HIP4081

The HIP4081 has four inputs, one for each output. Outputs
ALO and BLO are directly controlled by input ALI and BLI.
By holding ALI and BLI low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 36. As the V

supply ramps from zero

up, the DIS voltage is below its input threshold of 1.7V due to
the R1/R2 resistor divider. When V

exceeds approxi-

mately 9V to 10V, DIS becomes greater than the input
threshold and the chip disables all outputs. It is critical that
ALI and BLI be held low prior to DIS reaching its threshold

level of 1.7V while V

is ramping up, so that shoot

through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.

HIP4080

will indefinitely delay the lower turn-on delays

through the input comparator and will keep the lower MOS-
FETs off. With the lower MOSFETs off and the chip enabled,
i.e., DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+/IN- switch a full cycle while LDEL
is held high, to avoid shoot-through. This start-up procedure
can be initiated by the supply voltage and/or the chip enable
command by the circuit in Figure 37.

FIGURE 36.

FIGURE 37.

1 BHB

BHI

DIS

BLI

ALI

HDEL

AHI

LDEL

AHB

BHO

BLO

BLS

BHS

ALS

ALO

AHS

AHO

3.3K

ENABLE

15K

1 BHB

BHI

DIS

BLI

ALI

HDEL

AHI

LDEL

AHB

BHO

BLO

BLS

BHS

ALS

ALO

AHS

AHO

3.3K

15K

ENABLE

1 BHB

HEN

DIS

OUT

IN+

HDEL

IN-

LDEL

AHB

BHO

BLO

BLS

BHS

ALS

ALO

AHS

AHO

100K

RDEL

0.1

2N3906

ENABLE

56K

8.2V

56K

100K

HIP4080

NOTES:

1. Symbols are defined in the "MO Series Symbol List" in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension "D" does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.

4. Dimension "E" does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. "L" is the length of terminal for soldering to a substrate.

7. "N" is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width "B", as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

INDEX
AREA

-B-

0.25(0.010)

C A

B S

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45

0.25(0.010)

M20.3

(JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.0926

0.1043

2.35

2.65

0.0040

0.0118

0.10

0.30

0.013

0.0200

0.33

0.51

0.0091

0.0125

0.23

0.32

0.4961

0.5118

12.60

13.00

0.2914

0.2992

7.40

7.60

0.050 BSC

1.27 BSC

0.394

0.419

10.00

10.65

0.010

0.029

0.25

0.75

0.016

0.050

0.40

1.27

Rev. 0 12/93

Small Outline Plastic Packages (SOIC)

HIP4080

E20.3

(JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.210

5.33

0.015

0.39

0.115

0.195

2.93

4.95

0.014

0.022

0.356

0.558

0.045

0.070

1.55

1.77

0.008

0.014

0.204

0.355

0.980

1.060

24.89

26.9

0.005

0.13

0.300

0.325

7.62

8.25

0.240

0.280

6.10

7.11

0.100 BSC

2.54 BSC

0.300 BSC

7.62 BSC

0.430

10.92

0.115

0.150

2.93

3.81

Rev. 0 12/93

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between

English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the "MO Series Symbol List" in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated

in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru-

sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

6. E and

are measured with the leads constrained to be per-

pendicular to datum

7. e

and e

are measured at the lead tips with the leads uncon-

strained. e

must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.

Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,

E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

-B-

INDEX

1 2 3

N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25)

B S

-C-

Dual-In-Line Plastic Packages (PDIP)

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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