L520nsl.p65
IRL520NS/L
HEXFET
Power MOSFET
PD - 91534
l
Advanced Process Technology
l
Surface Mount (IRL520NS)
l
Low-profile through-hole (IRL520NL)
l
175C Operating Temperature
l
Fast Switching
l
Fully Avalanche Rated
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
3.1
R
JA
Junction-to-Ambient ( PCB Mounted,steady-state)**
40
Thermal Resistance
C/W
Parameter
Max.
Units
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ 10V
10
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ 10V
7.1
A
I
DM
Pulsed Drain Current
35
P
D
@T
A
= 25C
Power Dissipation
3.8
W
P
D
@T
C
= 25C
Power Dissipation
48
W
Linear Derating Factor
0.32
W/C
V
GS
Gate-to-Source Voltage
16
V
E
AS
Single Pulse Avalanche Energy
85
mJ
I
AR
Avalanche Current
6.0
A
E
AR
Repetitive Avalanche Energy
4.8
mJ
dv/dt
Peak Diode Recovery dv/dt
5.0
V/ns
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
C
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL520NL) is available for low-
profile applications.
Description
V
DSS
= 100V
R
DS(on)
= 0.18
I
D
= 10A
2
D P ak
T O -26 2
S
D
G
5/13/98
l
Logic-Level Gate Drive
IRL520NS/L
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
100
V
V
GS
= 0V, I
D
= 250A
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
0.11
V/C
Reference to 25C, I
D
= 1mA
0.18
V
GS
= 10V, I
D
= 6.0A
0.22
V
GS
= 5.0V, I
D
= 6.0A
0.26
V
GS
= 4.0V, I
D
= 5.0A
V
GS(th)
Gate Threshold Voltage
1.0
2.0
V
V
DS
= V
GS
, I
D
= 250A
g
fs
Forward Transconductance
3.1
S
V
DS
= 25V, I
D
= 6.0A
25
V
DS
= 100V, V
GS
= 0V
250
V
DS
= 80V, V
GS
= 0V, T
J
= 150C
Gate-to-Source Forward Leakage
100
n A
V
GS
= 16V
Gate-to-Source Reverse Leakage
-100
V
GS
= -16V
Q
g
Total Gate Charge
20
I
D
= 6.0A
Q
gs
Gate-to-Source Charge
4.6
nC
V
DS
= 80V
Q
gd
Gate-to-Drain ("Miller") Charge
10
V
GS
= 5.0V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time
4.0
V
DD
= 50V
t
r
Rise Time
35
I
D
= 6.0A
t
d(off)
Turn-Off Delay Time
23
R
G
= 11
,
V
GS
= 5.0V
t
f
Fall Time
22
R
D
= 8.2
,
See Fig. 10
Between lead,
and center of die contact
C
iss
Input Capacitance
440
V
GS
= 0V
C
oss
Output Capacitance
97
pF
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
50
= 1.0MHz, See Fig. 5
Electrical Characteristics @ T
J
= 25C (unless otherwise specified)
nH
I
GSS
R
DS(on)
Static Drain-to-Source On-Resistance
L
S
Internal Source Inductance
7.5
ns
I
DSS
Drain-to-Source Leakage Current
A
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
1.3
V
T
J
= 25C, I
S
= 6.0A, V
GS
= 0V
t
rr
Reverse Recovery Time
110
160
ns
T
J
= 25C, I
F
= 6.0A
Q
rr
Reverse Recovery Charge
410
620
nC
di/dt = 100A/s
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Source-Drain Ratings and Characteristics
S
D
G
A
10
35
Pulse width
300s; duty cycle
2%.
Notes:
Uses IRL520N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
I
SD
6.0A, di/dt
340A/s, V
DD
V
(BR)DSS
,
T
J
175C
V
DD
= 25V, starting T
J
= 25C, L = 4.7mH
R
G
= 25
, I
AS
= 6.0A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
IRL520NS/L
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 2. Typical Output Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
0.1
1
1 0
1 0 0
0.1
1
1 0
1 0 0
I , D
r
a
i
n
-
to
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
D
V , D rain-to-S o urce V oltage (V )
D S
A
2 0 s P U LS E W ID T H
T = 2 5C
J
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
0.1
1
1 0
1 0 0
0.1
1
1 0
1 0 0
I
,
Dr
ai
n
-
t
o
-
S
ou
r
c
e Cur
r
e
n
t
(
A
)
D
V , D rain-to-S ource V oltage (V )
D S
A
2 0 s P U LS E W ID T H
T = 1 75 C
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5 V
J
0 . 1
1
1 0
1 0 0
2
4
6
8
1 0
T = 2 5C
J
G S
V , G ate-to -S ou rce V oltage (V )
D
I
,
D
r
a
i
n
-
to
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
T = 1 7 5C
J
A
V = 5 0V
2 0 s P U L S E W ID TH
D S
0 . 0
0 . 5
1 . 0
1 . 5
2 . 0
2 . 5
3 . 0
- 6 0
- 4 0
- 2 0
0
2 0
4 0
6 0
8 0
1 0 0 1 2 0 1 4 0 1 6 0 1 8 0
J
T , Junction T em perature (C )
R
, D
r
a
i
n
-
to
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
DS
(
o
n
)
(
N
or
m
a
l
i
z
ed)
V = 10 V
G S
A
I = 1 0A
D
IRL520NS/L
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
2 0 0
4 0 0
6 0 0
8 0 0
1
1 0
1 0 0
C
,
Cap
ac
i
t
a
n
c
e
(
p
F
)
D S
V , D rain-to-S ourc e V oltage (V )
A
V = 0V , f = 1 M H z
C = C + C , C S H O R TE D
C = C
C = C + C
G S
iss g s g d d s
rs s g d
o ss ds g d
C
is s
C
os s
C
rs s
0
3
6
9
1 2
1 5
0
5
1 0
1 5
2 0
2 5
Q , T ota l G ate C h a rg e (n C )
G
V
, G
a
te
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
GS
V = 80 V
V = 50 V
V = 20 V
A
F O R TE S T C IR C U IT
S E E F IG U R E 1 3
I = 6.0 A
D
D S
D S
D S
0 . 1
1
1 0
1 0 0
0 . 4
0 . 6
0 . 8
1 . 0
1 . 2
1 . 4
T = 25 C
J
V = 0 V
G S
V , S ourc e-to -D rain V oltag e (V )
I , R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
S D
SD
A
T = 1 75 C
J
0.1
1
1 0
1 0 0
1
1 0
1 0 0
1 0 0 0
V , D ra in-to-S o u rce V o lta ge (V )
D S
I , D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
O P E R A T IO N IN T H IS A R E A L IM ITE D
B Y R
D
D S (o n)
1 0 s
1 0 0 s
1 m s
1 0 m s
A
T = 25 C
T = 17 5C
S ing le P u ls e
C
J
IRL520NS/L
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
V
DS
Pulse Width
1
s
Duty Factor
0.1 %
R
D
V
GS
R
G
D.U.T.
5.0V
+
-
V
DD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.01
0.1
1
10
0.00001
0.0001
0.001
0.01
0.1
Notes:
1. Duty factor D =
t / t
2. Peak T = P
x Z
+ T
1
2
J
DM
thJC
C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response
(Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
0
2
4
6
8
1 0
2 5
5 0
7 5
1 0 0
1 2 5
1 5 0
1 7 5
C
I , D
r
a
i
n
C
u
r
r
e
n
t
(
A
m
p
s
)
D
T , C ase T e m perature (C )
A
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